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Merge branches 'for-4.0/upstream-fixes', 'for-4.1/genius', 'for-4.1/huion-uclogic...
[linux-2.6-block.git] / drivers / clk / tegra / clk-tegra114.c
CommitLineData
2cb5efef
PDS		 1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/delay.h>
25c9ded6 24#include <linux/export.h>
2cb5efef 25#include <linux/clk/tegra.h>
c9e2d69a 26#include <dt-bindings/clock/tegra114-car.h>
2cb5efef
PDS		 27
28#include "clk.h"
6609dbe4 29#include "clk-id.h"
2cb5efef 30
1c472d8e 31#define RST_DFLL_DVCO 0x2F4
25c9ded6
PW		 32#define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */
33#define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */
34#define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */
2cb5efef 35
1c472d8e
PW		 36/* RST_DFLL_DVCO bitfields */
37#define DVFS_DFLL_RESET_SHIFT 0
38
25c9ded6
PW		 39/* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */
40#define CPU_FINETRIM_1_FCPU_1 BIT(0) /* fcpu0 */
41#define CPU_FINETRIM_1_FCPU_2 BIT(1) /* fcpu1 */
42#define CPU_FINETRIM_1_FCPU_3 BIT(2) /* fcpu2 */
43#define CPU_FINETRIM_1_FCPU_4 BIT(3) /* fcpu3 */
44#define CPU_FINETRIM_1_FCPU_5 BIT(4) /* fl2 */
45#define CPU_FINETRIM_1_FCPU_6 BIT(5) /* ftop */
46
47/* CPU_FINETRIM_R bitfields */
48#define CPU_FINETRIM_R_FCPU_1_SHIFT 0 /* fcpu0 */
49#define CPU_FINETRIM_R_FCPU_1_MASK (0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT)
50#define CPU_FINETRIM_R_FCPU_2_SHIFT 2 /* fcpu1 */
51#define CPU_FINETRIM_R_FCPU_2_MASK (0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT)
52#define CPU_FINETRIM_R_FCPU_3_SHIFT 4 /* fcpu2 */
53#define CPU_FINETRIM_R_FCPU_3_MASK (0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT)
54#define CPU_FINETRIM_R_FCPU_4_SHIFT 6 /* fcpu3 */
55#define CPU_FINETRIM_R_FCPU_4_MASK (0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT)
56#define CPU_FINETRIM_R_FCPU_5_SHIFT 8 /* fl2 */
57#define CPU_FINETRIM_R_FCPU_5_MASK (0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT)
58#define CPU_FINETRIM_R_FCPU_6_SHIFT 10 /* ftop */
59#define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
60
d5ff89a8
PDS		 61#define TEGRA114_CLK_PERIPH_BANKS 5
62
2cb5efef
PDS		 63#define PLLC_BASE 0x80
64#define PLLC_MISC2 0x88
65#define PLLC_MISC 0x8c
66#define PLLC2_BASE 0x4e8
67#define PLLC2_MISC 0x4ec
68#define PLLC3_BASE 0x4fc
69#define PLLC3_MISC 0x500
70#define PLLM_BASE 0x90
71#define PLLM_MISC 0x9c
72#define PLLP_BASE 0xa0
73#define PLLP_MISC 0xac
74#define PLLX_BASE 0xe0
75#define PLLX_MISC 0xe4
76#define PLLX_MISC2 0x514
77#define PLLX_MISC3 0x518
78#define PLLD_BASE 0xd0
79#define PLLD_MISC 0xdc
80#define PLLD2_BASE 0x4b8
81#define PLLD2_MISC 0x4bc
82#define PLLE_BASE 0xe8
83#define PLLE_MISC 0xec
84#define PLLA_BASE 0xb0
85#define PLLA_MISC 0xbc
86#define PLLU_BASE 0xc0
87#define PLLU_MISC 0xcc
88#define PLLRE_BASE 0x4c4
89#define PLLRE_MISC 0x4c8
90
91#define PLL_MISC_LOCK_ENABLE 18
92#define PLLC_MISC_LOCK_ENABLE 24
93#define PLLDU_MISC_LOCK_ENABLE 22
94#define PLLE_MISC_LOCK_ENABLE 9
95#define PLLRE_MISC_LOCK_ENABLE 30
96
97#define PLLC_IDDQ_BIT 26
98#define PLLX_IDDQ_BIT 3
99#define PLLRE_IDDQ_BIT 16
100
101#define PLL_BASE_LOCK BIT(27)
102#define PLLE_MISC_LOCK BIT(11)
103#define PLLRE_MISC_LOCK BIT(24)
104#define PLLCX_BASE_LOCK (BIT(26)|BIT(27))
105
106#define PLLE_AUX 0x48c
107#define PLLC_OUT 0x84
108#define PLLM_OUT 0x94
2cb5efef 109
2cb5efef
PDS		 110#define OSC_CTRL 0x50
111#define OSC_CTRL_OSC_FREQ_SHIFT 28
112#define OSC_CTRL_PLL_REF_DIV_SHIFT 26
113
114#define PLLXC_SW_MAX_P 6
115
116#define CCLKG_BURST_POLICY 0x368
2cb5efef
PDS		 117
118#define UTMIP_PLL_CFG2 0x488
119#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
120#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
121#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
122#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
123#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
124
125#define UTMIP_PLL_CFG1 0x484
126#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
127#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
128#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
129#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
130#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
131#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
132#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
133
134#define UTMIPLL_HW_PWRDN_CFG0 0x52c
135#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
136#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
137#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
138#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
139#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
140#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
141#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
142#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
143
2cb5efef 144#define CLK_SOURCE_CSITE 0x1d4
2cb5efef
PDS		 145#define CLK_SOURCE_EMC 0x19c
146
d53442e9
PDS		 147/* PLLM override registers */
148#define PMC_PLLM_WB0_OVERRIDE 0x1dc
149#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
150
31972fd9
JL		 151/* Tegra CPU clock and reset control regs */
152#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
153
167d5366
PDS		 154#define MUX8(_name, _parents, _offset, \
155 _clk_num, _gate_flags, _clk_id) \
156 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
157 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
158 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
159 NULL)
160
ad7d1140
JL		 161#ifdef CONFIG_PM_SLEEP
162static struct cpu_clk_suspend_context {
163 u32 clk_csite_src;
0017f447
JL		 164 u32 cclkg_burst;
165 u32 cclkg_divider;
ad7d1140
JL		 166} tegra114_cpu_clk_sctx;
167#endif
168
2cb5efef
PDS		 169static void __iomem *clk_base;
170static void __iomem *pmc_base;
171
172static DEFINE_SPINLOCK(pll_d_lock);
173static DEFINE_SPINLOCK(pll_d2_lock);
174static DEFINE_SPINLOCK(pll_u_lock);
2cb5efef 175static DEFINE_SPINLOCK(pll_re_lock);
4f4f85fa 176static DEFINE_SPINLOCK(emc_lock);
2cb5efef 177
fd428ad8
PDS		 178static struct div_nmp pllxc_nmp = {
179 .divm_shift = 0,
180 .divm_width = 8,
181 .divn_shift = 8,
182 .divn_width = 8,
183 .divp_shift = 20,
184 .divp_width = 4,
185};
186
2cb5efef
PDS		 187static struct pdiv_map pllxc_p[] = {
188 { .pdiv = 1, .hw_val = 0 },
189 { .pdiv = 2, .hw_val = 1 },
190 { .pdiv = 3, .hw_val = 2 },
191 { .pdiv = 4, .hw_val = 3 },
192 { .pdiv = 5, .hw_val = 4 },
193 { .pdiv = 6, .hw_val = 5 },
194 { .pdiv = 8, .hw_val = 6 },
195 { .pdiv = 10, .hw_val = 7 },
196 { .pdiv = 12, .hw_val = 8 },
197 { .pdiv = 16, .hw_val = 9 },
198 { .pdiv = 12, .hw_val = 10 },
199 { .pdiv = 16, .hw_val = 11 },
200 { .pdiv = 20, .hw_val = 12 },
201 { .pdiv = 24, .hw_val = 13 },
202 { .pdiv = 32, .hw_val = 14 },
203 { .pdiv = 0, .hw_val = 0 },
204};
205
206static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
207 { 12000000, 624000000, 104, 0, 2},
208 { 12000000, 600000000, 100, 0, 2},
209 { 13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */
210 { 16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */
211 { 19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */
212 { 26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
213 { 0, 0, 0, 0, 0, 0 },
214};
215
216static struct tegra_clk_pll_params pll_c_params = {
217 .input_min = 12000000,
218 .input_max = 800000000,
219 .cf_min = 12000000,
220 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
221 .vco_min = 600000000,
222 .vco_max = 1400000000,
223 .base_reg = PLLC_BASE,
224 .misc_reg = PLLC_MISC,
225 .lock_mask = PLL_BASE_LOCK,
226 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
227 .lock_delay = 300,
228 .iddq_reg = PLLC_MISC,
229 .iddq_bit_idx = PLLC_IDDQ_BIT,
230 .max_p = PLLXC_SW_MAX_P,
231 .dyn_ramp_reg = PLLC_MISC2,
232 .stepa_shift = 17,
233 .stepb_shift = 9,
234 .pdiv_tohw = pllxc_p,
fd428ad8 235 .div_nmp = &pllxc_nmp,
ebe142b2
PDS		 236 .freq_table = pll_c_freq_table,
237 .flags = TEGRA_PLL_USE_LOCK,
fd428ad8
PDS		 238};
239
240static struct div_nmp pllcx_nmp = {
241 .divm_shift = 0,
242 .divm_width = 2,
243 .divn_shift = 8,
244 .divn_width = 8,
245 .divp_shift = 20,
246 .divp_width = 3,
2cb5efef
PDS		 247};
248
249static struct pdiv_map pllc_p[] = {
250 { .pdiv = 1, .hw_val = 0 },
251 { .pdiv = 2, .hw_val = 1 },
252 { .pdiv = 4, .hw_val = 3 },
253 { .pdiv = 8, .hw_val = 5 },
254 { .pdiv = 16, .hw_val = 7 },
255 { .pdiv = 0, .hw_val = 0 },
256};
257
258static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
259 {12000000, 600000000, 100, 0, 2},
260 {13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */
261 {16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */
262 {19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */
263 {26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
264 {0, 0, 0, 0, 0, 0},
265};
266
267static struct tegra_clk_pll_params pll_c2_params = {
268 .input_min = 12000000,
269 .input_max = 48000000,
270 .cf_min = 12000000,
271 .cf_max = 19200000,
272 .vco_min = 600000000,
273 .vco_max = 1200000000,
274 .base_reg = PLLC2_BASE,
275 .misc_reg = PLLC2_MISC,
276 .lock_mask = PLL_BASE_LOCK,
277 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
278 .lock_delay = 300,
279 .pdiv_tohw = pllc_p,
fd428ad8
PDS		 280 .div_nmp = &pllcx_nmp,
281 .max_p = 7,
2cb5efef
PDS		 282 .ext_misc_reg[0] = 0x4f0,
283 .ext_misc_reg[1] = 0x4f4,
284 .ext_misc_reg[2] = 0x4f8,
ebe142b2
PDS		 285 .freq_table = pll_cx_freq_table,
286 .flags = TEGRA_PLL_USE_LOCK,
2cb5efef
PDS		 287};
288
289static struct tegra_clk_pll_params pll_c3_params = {
290 .input_min = 12000000,
291 .input_max = 48000000,
292 .cf_min = 12000000,
293 .cf_max = 19200000,
294 .vco_min = 600000000,
295 .vco_max = 1200000000,
296 .base_reg = PLLC3_BASE,
297 .misc_reg = PLLC3_MISC,
298 .lock_mask = PLL_BASE_LOCK,
299 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
300 .lock_delay = 300,
301 .pdiv_tohw = pllc_p,
fd428ad8
PDS		 302 .div_nmp = &pllcx_nmp,
303 .max_p = 7,
2cb5efef
PDS		 304 .ext_misc_reg[0] = 0x504,
305 .ext_misc_reg[1] = 0x508,
306 .ext_misc_reg[2] = 0x50c,
ebe142b2
PDS		 307 .freq_table = pll_cx_freq_table,
308 .flags = TEGRA_PLL_USE_LOCK,
2cb5efef
PDS		 309};
310
fd428ad8
PDS		 311static struct div_nmp pllm_nmp = {
312 .divm_shift = 0,
313 .divm_width = 8,
d53442e9 314 .override_divm_shift = 0,
fd428ad8
PDS		 315 .divn_shift = 8,
316 .divn_width = 8,
d53442e9 317 .override_divn_shift = 8,
fd428ad8
PDS		 318 .divp_shift = 20,
319 .divp_width = 1,
d53442e9 320 .override_divp_shift = 27,
fd428ad8
PDS		 321};
322
2cb5efef
PDS		 323static struct pdiv_map pllm_p[] = {
324 { .pdiv = 1, .hw_val = 0 },
325 { .pdiv = 2, .hw_val = 1 },
326 { .pdiv = 0, .hw_val = 0 },
327};
328
329static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
330 {12000000, 800000000, 66, 0, 1}, /* actual: 792.0 MHz */
331 {13000000, 800000000, 61, 0, 1}, /* actual: 793.0 MHz */
332 {16800000, 800000000, 47, 0, 1}, /* actual: 789.6 MHz */
333 {19200000, 800000000, 41, 0, 1}, /* actual: 787.2 MHz */
334 {26000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */
335 {0, 0, 0, 0, 0, 0},
336};
337
338static struct tegra_clk_pll_params pll_m_params = {
339 .input_min = 12000000,
340 .input_max = 500000000,
341 .cf_min = 12000000,
342 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
343 .vco_min = 400000000,
344 .vco_max = 1066000000,
345 .base_reg = PLLM_BASE,
346 .misc_reg = PLLM_MISC,
347 .lock_mask = PLL_BASE_LOCK,
348 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
349 .lock_delay = 300,
350 .max_p = 2,
351 .pdiv_tohw = pllm_p,
fd428ad8 352 .div_nmp = &pllm_nmp,
d53442e9
PDS		 353 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
354 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
ebe142b2
PDS		 355 .freq_table = pll_m_freq_table,
356 .flags = TEGRA_PLL_USE_LOCK,
fd428ad8
PDS		 357};
358
359static struct div_nmp pllp_nmp = {
360 .divm_shift = 0,
361 .divm_width = 5,
362 .divn_shift = 8,
363 .divn_width = 10,
364 .divp_shift = 20,
365 .divp_width = 3,
2cb5efef
PDS		 366};
367
368static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
369 {12000000, 216000000, 432, 12, 1, 8},
370 {13000000, 216000000, 432, 13, 1, 8},
371 {16800000, 216000000, 360, 14, 1, 8},
372 {19200000, 216000000, 360, 16, 1, 8},
373 {26000000, 216000000, 432, 26, 1, 8},
374 {0, 0, 0, 0, 0, 0},
375};
376
377static struct tegra_clk_pll_params pll_p_params = {
378 .input_min = 2000000,
379 .input_max = 31000000,
380 .cf_min = 1000000,
381 .cf_max = 6000000,
382 .vco_min = 200000000,
383 .vco_max = 700000000,
384 .base_reg = PLLP_BASE,
385 .misc_reg = PLLP_MISC,
386 .lock_mask = PLL_BASE_LOCK,
387 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
388 .lock_delay = 300,
fd428ad8 389 .div_nmp = &pllp_nmp,
ebe142b2
PDS		 390 .freq_table = pll_p_freq_table,
391 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
392 .fixed_rate = 408000000,
2cb5efef
PDS		 393};
394
395static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
396 {9600000, 282240000, 147, 5, 0, 4},
397 {9600000, 368640000, 192, 5, 0, 4},
398 {9600000, 240000000, 200, 8, 0, 8},
399
400 {28800000, 282240000, 245, 25, 0, 8},
401 {28800000, 368640000, 320, 25, 0, 8},
402 {28800000, 240000000, 200, 24, 0, 8},
403 {0, 0, 0, 0, 0, 0},
404};
405
406
407static struct tegra_clk_pll_params pll_a_params = {
408 .input_min = 2000000,
409 .input_max = 31000000,
410 .cf_min = 1000000,
411 .cf_max = 6000000,
412 .vco_min = 200000000,
413 .vco_max = 700000000,
414 .base_reg = PLLA_BASE,
415 .misc_reg = PLLA_MISC,
416 .lock_mask = PLL_BASE_LOCK,
417 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
418 .lock_delay = 300,
fd428ad8 419 .div_nmp = &pllp_nmp,
ebe142b2
PDS		 420 .freq_table = pll_a_freq_table,
421 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
2cb5efef
PDS		 422};
423
424static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
425 {12000000, 216000000, 864, 12, 2, 12},
426 {13000000, 216000000, 864, 13, 2, 12},
427 {16800000, 216000000, 720, 14, 2, 12},
428 {19200000, 216000000, 720, 16, 2, 12},
429 {26000000, 216000000, 864, 26, 2, 12},
430
431 {12000000, 594000000, 594, 12, 0, 12},
432 {13000000, 594000000, 594, 13, 0, 12},
433 {16800000, 594000000, 495, 14, 0, 12},
434 {19200000, 594000000, 495, 16, 0, 12},
435 {26000000, 594000000, 594, 26, 0, 12},
436
437 {12000000, 1000000000, 1000, 12, 0, 12},
438 {13000000, 1000000000, 1000, 13, 0, 12},
439 {19200000, 1000000000, 625, 12, 0, 12},
440 {26000000, 1000000000, 1000, 26, 0, 12},
441
442 {0, 0, 0, 0, 0, 0},
443};
444
445static struct tegra_clk_pll_params pll_d_params = {
446 .input_min = 2000000,
447 .input_max = 40000000,
448 .cf_min = 1000000,
449 .cf_max = 6000000,
450 .vco_min = 500000000,
451 .vco_max = 1000000000,
452 .base_reg = PLLD_BASE,
453 .misc_reg = PLLD_MISC,
454 .lock_mask = PLL_BASE_LOCK,
455 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
456 .lock_delay = 1000,
fd428ad8 457 .div_nmp = &pllp_nmp,
ebe142b2
PDS		 458 .freq_table = pll_d_freq_table,
459 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
460 TEGRA_PLL_USE_LOCK,
2cb5efef
PDS		 461};
462
463static struct tegra_clk_pll_params pll_d2_params = {
464 .input_min = 2000000,
465 .input_max = 40000000,
466 .cf_min = 1000000,
467 .cf_max = 6000000,
468 .vco_min = 500000000,
469 .vco_max = 1000000000,
470 .base_reg = PLLD2_BASE,
471 .misc_reg = PLLD2_MISC,
472 .lock_mask = PLL_BASE_LOCK,
473 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
474 .lock_delay = 1000,
fd428ad8 475 .div_nmp = &pllp_nmp,
ebe142b2
PDS		 476 .freq_table = pll_d_freq_table,
477 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
478 TEGRA_PLL_USE_LOCK,
2cb5efef
PDS		 479};
480
481static struct pdiv_map pllu_p[] = {
482 { .pdiv = 1, .hw_val = 1 },
483 { .pdiv = 2, .hw_val = 0 },
484 { .pdiv = 0, .hw_val = 0 },
485};
486
fd428ad8
PDS		 487static struct div_nmp pllu_nmp = {
488 .divm_shift = 0,
489 .divm_width = 5,
490 .divn_shift = 8,
491 .divn_width = 10,
492 .divp_shift = 20,
493 .divp_width = 1,
494};
495
2cb5efef
PDS		 496static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
497 {12000000, 480000000, 960, 12, 0, 12},
498 {13000000, 480000000, 960, 13, 0, 12},
499 {16800000, 480000000, 400, 7, 0, 5},
500 {19200000, 480000000, 200, 4, 0, 3},
501 {26000000, 480000000, 960, 26, 0, 12},
502 {0, 0, 0, 0, 0, 0},
503};
504
505static struct tegra_clk_pll_params pll_u_params = {
506 .input_min = 2000000,
507 .input_max = 40000000,
508 .cf_min = 1000000,
509 .cf_max = 6000000,
510 .vco_min = 480000000,
511 .vco_max = 960000000,
512 .base_reg = PLLU_BASE,
513 .misc_reg = PLLU_MISC,
514 .lock_mask = PLL_BASE_LOCK,
515 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
516 .lock_delay = 1000,
517 .pdiv_tohw = pllu_p,
fd428ad8 518 .div_nmp = &pllu_nmp,
ebe142b2
PDS		 519 .freq_table = pll_u_freq_table,
520 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
521 TEGRA_PLL_USE_LOCK,
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PDS		 522};
523
524static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
525 /* 1 GHz */
526 {12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */
527 {13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */
528 {16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */
529 {19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */
530 {26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */
531
532 {0, 0, 0, 0, 0, 0},
533};
534
535static struct tegra_clk_pll_params pll_x_params = {
536 .input_min = 12000000,
537 .input_max = 800000000,
538 .cf_min = 12000000,
539 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
540 .vco_min = 700000000,
541 .vco_max = 2400000000U,
542 .base_reg = PLLX_BASE,
543 .misc_reg = PLLX_MISC,
544 .lock_mask = PLL_BASE_LOCK,
545 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
546 .lock_delay = 300,
547 .iddq_reg = PLLX_MISC3,
548 .iddq_bit_idx = PLLX_IDDQ_BIT,
549 .max_p = PLLXC_SW_MAX_P,
550 .dyn_ramp_reg = PLLX_MISC2,
551 .stepa_shift = 16,
552 .stepb_shift = 24,
553 .pdiv_tohw = pllxc_p,
fd428ad8 554 .div_nmp = &pllxc_nmp,
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PDS		 555 .freq_table = pll_x_freq_table,
556 .flags = TEGRA_PLL_USE_LOCK,
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PDS		 557};
558
559static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
560 /* PLLE special case: use cpcon field to store cml divider value */
561 {336000000, 100000000, 100, 21, 16, 11},
562 {312000000, 100000000, 200, 26, 24, 13},
8e9cc80a 563 {12000000, 100000000, 200, 1, 24, 13},
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PDS		 564 {0, 0, 0, 0, 0, 0},
565};
566
fd428ad8
PDS		 567static struct div_nmp plle_nmp = {
568 .divm_shift = 0,
569 .divm_width = 8,
570 .divn_shift = 8,
571 .divn_width = 8,
572 .divp_shift = 24,
573 .divp_width = 4,
574};
575
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PDS		 576static struct tegra_clk_pll_params pll_e_params = {
577 .input_min = 12000000,
578 .input_max = 1000000000,
579 .cf_min = 12000000,
580 .cf_max = 75000000,
581 .vco_min = 1600000000,
582 .vco_max = 2400000000U,
583 .base_reg = PLLE_BASE,
584 .misc_reg = PLLE_MISC,
585 .aux_reg = PLLE_AUX,
586 .lock_mask = PLLE_MISC_LOCK,
587 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
588 .lock_delay = 300,
fd428ad8 589 .div_nmp = &plle_nmp,
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PDS		 590 .freq_table = pll_e_freq_table,
591 .flags = TEGRA_PLL_FIXED,
592 .fixed_rate = 100000000,
fd428ad8
PDS		 593};
594
595static struct div_nmp pllre_nmp = {
596 .divm_shift = 0,
597 .divm_width = 8,
598 .divn_shift = 8,
599 .divn_width = 8,
600 .divp_shift = 16,
601 .divp_width = 4,
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PDS		 602};
603
604static struct tegra_clk_pll_params pll_re_vco_params = {
605 .input_min = 12000000,
606 .input_max = 1000000000,
607 .cf_min = 12000000,
608 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
609 .vco_min = 300000000,
610 .vco_max = 600000000,
611 .base_reg = PLLRE_BASE,
612 .misc_reg = PLLRE_MISC,
613 .lock_mask = PLLRE_MISC_LOCK,
614 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
615 .lock_delay = 300,
616 .iddq_reg = PLLRE_MISC,
617 .iddq_bit_idx = PLLRE_IDDQ_BIT,
fd428ad8 618 .div_nmp = &pllre_nmp,
ebe142b2 619 .flags = TEGRA_PLL_USE_LOCK,
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PDS		 620};
621
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PDS		 622/* possible OSC frequencies in Hz */
623static unsigned long tegra114_input_freq[] = {
624 [0] = 13000000,
625 [1] = 16800000,
626 [4] = 19200000,
627 [5] = 38400000,
628 [8] = 12000000,
629 [9] = 48000000,
630 [12] = 260000000,
631};
632
633#define MASK(x) (BIT(x) - 1)
634
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PDS		 635struct utmi_clk_param {
636 /* Oscillator Frequency in KHz */
637 u32 osc_frequency;
638 /* UTMIP PLL Enable Delay Count */
639 u8 enable_delay_count;
640 /* UTMIP PLL Stable count */
641 u8 stable_count;
642 /* UTMIP PLL Active delay count */
643 u8 active_delay_count;
644 /* UTMIP PLL Xtal frequency count */
645 u8 xtal_freq_count;
646};
647
648static const struct utmi_clk_param utmi_parameters[] = {
649 {.osc_frequency = 13000000, .enable_delay_count = 0x02,
650 .stable_count = 0x33, .active_delay_count = 0x05,
651 .xtal_freq_count = 0x7F},
652 {.osc_frequency = 19200000, .enable_delay_count = 0x03,
653 .stable_count = 0x4B, .active_delay_count = 0x06,
654 .xtal_freq_count = 0xBB},
655 {.osc_frequency = 12000000, .enable_delay_count = 0x02,
656 .stable_count = 0x2F, .active_delay_count = 0x04,
657 .xtal_freq_count = 0x76},
658 {.osc_frequency = 26000000, .enable_delay_count = 0x04,
659 .stable_count = 0x66, .active_delay_count = 0x09,
660 .xtal_freq_count = 0xFE},
661 {.osc_frequency = 16800000, .enable_delay_count = 0x03,
662 .stable_count = 0x41, .active_delay_count = 0x0A,
663 .xtal_freq_count = 0xA4},
664};
665
666/* peripheral mux definitions */
667
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PDS		 668static const char *mux_plld_out0_plld2_out0[] = {
669 "pll_d_out0", "pll_d2_out0",
670};
671#define mux_plld_out0_plld2_out0_idx NULL
672
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PDS		 673static const char *mux_pllmcp_clkm[] = {
674 "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
675};
676
677static const struct clk_div_table pll_re_div_table[] = {
678 { .val = 0, .div = 1 },
679 { .val = 1, .div = 2 },
680 { .val = 2, .div = 3 },
681 { .val = 3, .div = 4 },
682 { .val = 4, .div = 5 },
683 { .val = 5, .div = 6 },
684 { .val = 0, .div = 0 },
685};
686
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PDS		 687static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
688 [tegra_clk_rtc] = { .dt_id = TEGRA114_CLK_RTC, .present = true },
689 [tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true },
690 [tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true },
691 [tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },
20e7c323 692 [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },
6609dbe4
PDS		 693 [tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true },
694 [tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true },
695 [tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },
20e7c323
AB		 696 [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },
697 [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },
6609dbe4
PDS		 698 [tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true },
699 [tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true },
700 [tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true },
701 [tegra_clk_epp_8] = { .dt_id = TEGRA114_CLK_EPP, .present = true },
702 [tegra_clk_gr2d_8] = { .dt_id = TEGRA114_CLK_GR2D, .present = true },
703 [tegra_clk_usbd] = { .dt_id = TEGRA114_CLK_USBD, .present = true },
704 [tegra_clk_isp] = { .dt_id = TEGRA114_CLK_ISP, .present = true },
705 [tegra_clk_gr3d_8] = { .dt_id = TEGRA114_CLK_GR3D, .present = true },
706 [tegra_clk_disp2] = { .dt_id = TEGRA114_CLK_DISP2, .present = true },
707 [tegra_clk_disp1] = { .dt_id = TEGRA114_CLK_DISP1, .present = true },
708 [tegra_clk_host1x_8] = { .dt_id = TEGRA114_CLK_HOST1X, .present = true },
709 [tegra_clk_vcp] = { .dt_id = TEGRA114_CLK_VCP, .present = true },
710 [tegra_clk_apbdma] = { .dt_id = TEGRA114_CLK_APBDMA, .present = true },
711 [tegra_clk_kbc] = { .dt_id = TEGRA114_CLK_KBC, .present = true },
712 [tegra_clk_kfuse] = { .dt_id = TEGRA114_CLK_KFUSE, .present = true },
713 [tegra_clk_sbc1_8] = { .dt_id = TEGRA114_CLK_SBC1, .present = true },
714 [tegra_clk_nor] = { .dt_id = TEGRA114_CLK_NOR, .present = true },
715 [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true },
716 [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true },
717 [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true },
6609dbe4
PDS		 718 [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true },
719 [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true },
720 [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
721 [tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },
722 [tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },
723 [tegra_clk_mipi_cal] = { .dt_id = TEGRA114_CLK_MIPI_CAL, .present = true },
724 [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },
725 [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },
726 [tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true },
727 [tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true },
728 [tegra_clk_bsea] = { .dt_id = TEGRA114_CLK_BSEA, .present = true },
729 [tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true },
730 [tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true },
731 [tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true },
20e7c323 732 [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },
6609dbe4
PDS		 733 [tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true },
734 [tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true },
735 [tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true },
736 [tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true },
737 [tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true },
738 [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true },
739 [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true },
740 [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true },
6609dbe4
PDS		 741 [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
742 [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
743 [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
744 [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true },
745 [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true },
746 [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true },
747 [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true },
748 [tegra_clk_i2s4] = { .dt_id = TEGRA114_CLK_I2S4, .present = true },
749 [tegra_clk_i2c4] = { .dt_id = TEGRA114_CLK_I2C4, .present = true },
750 [tegra_clk_sbc5_8] = { .dt_id = TEGRA114_CLK_SBC5, .present = true },
751 [tegra_clk_sbc6_8] = { .dt_id = TEGRA114_CLK_SBC6, .present = true },
752 [tegra_clk_d_audio] = { .dt_id = TEGRA114_CLK_D_AUDIO, .present = true },
753 [tegra_clk_apbif] = { .dt_id = TEGRA114_CLK_APBIF, .present = true },
754 [tegra_clk_dam0] = { .dt_id = TEGRA114_CLK_DAM0, .present = true },
755 [tegra_clk_dam1] = { .dt_id = TEGRA114_CLK_DAM1, .present = true },
756 [tegra_clk_dam2] = { .dt_id = TEGRA114_CLK_DAM2, .present = true },
757 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA114_CLK_HDA2CODEC_2X, .present = true },
758 [tegra_clk_audio0_2x] = { .dt_id = TEGRA114_CLK_AUDIO0_2X, .present = true },
759 [tegra_clk_audio1_2x] = { .dt_id = TEGRA114_CLK_AUDIO1_2X, .present = true },
760 [tegra_clk_audio2_2x] = { .dt_id = TEGRA114_CLK_AUDIO2_2X, .present = true },
761 [tegra_clk_audio3_2x] = { .dt_id = TEGRA114_CLK_AUDIO3_2X, .present = true },
762 [tegra_clk_audio4_2x] = { .dt_id = TEGRA114_CLK_AUDIO4_2X, .present = true },
763 [tegra_clk_spdif_2x] = { .dt_id = TEGRA114_CLK_SPDIF_2X, .present = true },
764 [tegra_clk_actmon] = { .dt_id = TEGRA114_CLK_ACTMON, .present = true },
765 [tegra_clk_extern1] = { .dt_id = TEGRA114_CLK_EXTERN1, .present = true },
766 [tegra_clk_extern2] = { .dt_id = TEGRA114_CLK_EXTERN2, .present = true },
767 [tegra_clk_extern3] = { .dt_id = TEGRA114_CLK_EXTERN3, .present = true },
768 [tegra_clk_hda] = { .dt_id = TEGRA114_CLK_HDA, .present = true },
769 [tegra_clk_se] = { .dt_id = TEGRA114_CLK_SE, .present = true },
770 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA114_CLK_HDA2HDMI, .present = true },
771 [tegra_clk_cilab] = { .dt_id = TEGRA114_CLK_CILAB, .present = true },
772 [tegra_clk_cilcd] = { .dt_id = TEGRA114_CLK_CILCD, .present = true },
773 [tegra_clk_cile] = { .dt_id = TEGRA114_CLK_CILE, .present = true },
774 [tegra_clk_dsialp] = { .dt_id = TEGRA114_CLK_DSIALP, .present = true },
775 [tegra_clk_dsiblp] = { .dt_id = TEGRA114_CLK_DSIBLP, .present = true },
776 [tegra_clk_dds] = { .dt_id = TEGRA114_CLK_DDS, .present = true },
777 [tegra_clk_dp2] = { .dt_id = TEGRA114_CLK_DP2, .present = true },
778 [tegra_clk_amx] = { .dt_id = TEGRA114_CLK_AMX, .present = true },
779 [tegra_clk_adx] = { .dt_id = TEGRA114_CLK_ADX, .present = true },
780 [tegra_clk_xusb_ss] = { .dt_id = TEGRA114_CLK_XUSB_SS, .present = true },
781 [tegra_clk_uartb] = { .dt_id = TEGRA114_CLK_UARTB, .present = true },
782 [tegra_clk_vfir] = { .dt_id = TEGRA114_CLK_VFIR, .present = true },
783 [tegra_clk_spdif_in] = { .dt_id = TEGRA114_CLK_SPDIF_IN, .present = true },
784 [tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true },
785 [tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true },
6609dbe4
PDS		 786 [tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true },
787 [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
788 [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
789 [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
790 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
791 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
792 [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
793 [tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
794 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
795 [tegra_clk_pll_c2] = { .dt_id = TEGRA114_CLK_PLL_C2, .present = true },
796 [tegra_clk_pll_c3] = { .dt_id = TEGRA114_CLK_PLL_C3, .present = true },
797 [tegra_clk_pll_m] = { .dt_id = TEGRA114_CLK_PLL_M, .present = true },
798 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA114_CLK_PLL_M_OUT1, .present = true },
799 [tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true },
800 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA114_CLK_PLL_P_OUT1, .present = true },
801 [tegra_clk_pll_p_out2_int] = { .dt_id = TEGRA114_CLK_PLL_P_OUT2, .present = true },
802 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA114_CLK_PLL_P_OUT3, .present = true },
803 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA114_CLK_PLL_P_OUT4, .present = true },
804 [tegra_clk_pll_a] = { .dt_id = TEGRA114_CLK_PLL_A, .present = true },
805 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA114_CLK_PLL_A_OUT0, .present = true },
806 [tegra_clk_pll_d] = { .dt_id = TEGRA114_CLK_PLL_D, .present = true },
807 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA114_CLK_PLL_D_OUT0, .present = true },
808 [tegra_clk_pll_d2] = { .dt_id = TEGRA114_CLK_PLL_D2, .present = true },
809 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA114_CLK_PLL_D2_OUT0, .present = true },
810 [tegra_clk_pll_u] = { .dt_id = TEGRA114_CLK_PLL_U, .present = true },
811 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA114_CLK_PLL_U_480M, .present = true },
812 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA114_CLK_PLL_U_60M, .present = true },
813 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA114_CLK_PLL_U_48M, .present = true },
814 [tegra_clk_pll_u_12m] = { .dt_id = TEGRA114_CLK_PLL_U_12M, .present = true },
815 [tegra_clk_pll_x] = { .dt_id = TEGRA114_CLK_PLL_X, .present = true },
816 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA114_CLK_PLL_X_OUT0, .present = true },
817 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA114_CLK_PLL_RE_VCO, .present = true },
818 [tegra_clk_pll_re_out] = { .dt_id = TEGRA114_CLK_PLL_RE_OUT, .present = true },
819 [tegra_clk_pll_e_out0] = { .dt_id = TEGRA114_CLK_PLL_E_OUT0, .present = true },
820 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC, .present = true },
821 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA114_CLK_I2S0_SYNC, .present = true },
822 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA114_CLK_I2S1_SYNC, .present = true },
823 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA114_CLK_I2S2_SYNC, .present = true },
824 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA114_CLK_I2S3_SYNC, .present = true },
825 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA114_CLK_I2S4_SYNC, .present = true },
826 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA114_CLK_VIMCLK_SYNC, .present = true },
827 [tegra_clk_audio0] = { .dt_id = TEGRA114_CLK_AUDIO0, .present = true },
828 [tegra_clk_audio1] = { .dt_id = TEGRA114_CLK_AUDIO1, .present = true },
829 [tegra_clk_audio2] = { .dt_id = TEGRA114_CLK_AUDIO2, .present = true },
830 [tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
831 [tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
832 [tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
833 [tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true },
834 [tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true },
835 [tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true },
836 [tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true },
837 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
838 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
839 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
840 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true },
5c992afc 841 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA114_CLK_XUSB_SS_DIV2, .present = true},
6609dbe4
PDS		 842 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true },
843 [tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true },
844 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true },
845 [tegra_clk_sclk] = { .dt_id = TEGRA114_CLK_SCLK, .present = true },
846 [tegra_clk_hclk] = { .dt_id = TEGRA114_CLK_HCLK, .present = true },
847 [tegra_clk_pclk] = { .dt_id = TEGRA114_CLK_PCLK, .present = true },
848 [tegra_clk_cclk_g] = { .dt_id = TEGRA114_CLK_CCLK_G, .present = true },
849 [tegra_clk_cclk_lp] = { .dt_id = TEGRA114_CLK_CCLK_LP, .present = true },
850 [tegra_clk_dfll_ref] = { .dt_id = TEGRA114_CLK_DFLL_REF, .present = true },
851 [tegra_clk_dfll_soc] = { .dt_id = TEGRA114_CLK_DFLL_SOC, .present = true },
852 [tegra_clk_audio0_mux] = { .dt_id = TEGRA114_CLK_AUDIO0_MUX, .present = true },
853 [tegra_clk_audio1_mux] = { .dt_id = TEGRA114_CLK_AUDIO1_MUX, .present = true },
854 [tegra_clk_audio2_mux] = { .dt_id = TEGRA114_CLK_AUDIO2_MUX, .present = true },
855 [tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
856 [tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
857 [tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
858 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_1_MUX, .present = true },
859 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_2_MUX, .present = true },
860 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
861 [tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
862 [tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
863};
864
73d37e4c
PDS		 865static struct tegra_devclk devclks[] __initdata = {
866 { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
867 { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
868 { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
869 { .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
870 { .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
871 { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
872 { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
873 { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
874 { .con_id = "pll_c3", .dt_id = TEGRA114_CLK_PLL_C3 },
875 { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P },
876 { .con_id = "pll_p_out1", .dt_id = TEGRA114_CLK_PLL_P_OUT1 },
877 { .con_id = "pll_p_out2", .dt_id = TEGRA114_CLK_PLL_P_OUT2 },
878 { .con_id = "pll_p_out3", .dt_id = TEGRA114_CLK_PLL_P_OUT3 },
879 { .con_id = "pll_p_out4", .dt_id = TEGRA114_CLK_PLL_P_OUT4 },
880 { .con_id = "pll_m", .dt_id = TEGRA114_CLK_PLL_M },
881 { .con_id = "pll_m_out1", .dt_id = TEGRA114_CLK_PLL_M_OUT1 },
882 { .con_id = "pll_x", .dt_id = TEGRA114_CLK_PLL_X },
883 { .con_id = "pll_x_out0", .dt_id = TEGRA114_CLK_PLL_X_OUT0 },
884 { .con_id = "pll_u", .dt_id = TEGRA114_CLK_PLL_U },
885 { .con_id = "pll_u_480M", .dt_id = TEGRA114_CLK_PLL_U_480M },
886 { .con_id = "pll_u_60M", .dt_id = TEGRA114_CLK_PLL_U_60M },
887 { .con_id = "pll_u_48M", .dt_id = TEGRA114_CLK_PLL_U_48M },
888 { .con_id = "pll_u_12M", .dt_id = TEGRA114_CLK_PLL_U_12M },
889 { .con_id = "pll_d", .dt_id = TEGRA114_CLK_PLL_D },
890 { .con_id = "pll_d_out0", .dt_id = TEGRA114_CLK_PLL_D_OUT0 },
891 { .con_id = "pll_d2", .dt_id = TEGRA114_CLK_PLL_D2 },
892 { .con_id = "pll_d2_out0", .dt_id = TEGRA114_CLK_PLL_D2_OUT0 },
893 { .con_id = "pll_a", .dt_id = TEGRA114_CLK_PLL_A },
894 { .con_id = "pll_a_out0", .dt_id = TEGRA114_CLK_PLL_A_OUT0 },
895 { .con_id = "pll_re_vco", .dt_id = TEGRA114_CLK_PLL_RE_VCO },
896 { .con_id = "pll_re_out", .dt_id = TEGRA114_CLK_PLL_RE_OUT },
897 { .con_id = "pll_e_out0", .dt_id = TEGRA114_CLK_PLL_E_OUT0 },
898 { .con_id = "spdif_in_sync", .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC },
899 { .con_id = "i2s0_sync", .dt_id = TEGRA114_CLK_I2S0_SYNC },
900 { .con_id = "i2s1_sync", .dt_id = TEGRA114_CLK_I2S1_SYNC },
901 { .con_id = "i2s2_sync", .dt_id = TEGRA114_CLK_I2S2_SYNC },
902 { .con_id = "i2s3_sync", .dt_id = TEGRA114_CLK_I2S3_SYNC },
903 { .con_id = "i2s4_sync", .dt_id = TEGRA114_CLK_I2S4_SYNC },
904 { .con_id = "vimclk_sync", .dt_id = TEGRA114_CLK_VIMCLK_SYNC },
905 { .con_id = "audio0", .dt_id = TEGRA114_CLK_AUDIO0 },
906 { .con_id = "audio1", .dt_id = TEGRA114_CLK_AUDIO1 },
907 { .con_id = "audio2", .dt_id = TEGRA114_CLK_AUDIO2 },
908 { .con_id = "audio3", .dt_id = TEGRA114_CLK_AUDIO3 },
909 { .con_id = "audio4", .dt_id = TEGRA114_CLK_AUDIO4 },
910 { .con_id = "spdif", .dt_id = TEGRA114_CLK_SPDIF },
911 { .con_id = "audio0_2x", .dt_id = TEGRA114_CLK_AUDIO0_2X },
912 { .con_id = "audio1_2x", .dt_id = TEGRA114_CLK_AUDIO1_2X },
913 { .con_id = "audio2_2x", .dt_id = TEGRA114_CLK_AUDIO2_2X },
914 { .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
915 { .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
916 { .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
917 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 },
918 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 },
919 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 },
920 { .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK },
921 { .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
922 { .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
923 { .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
924 { .con_id = "hclk", .dt_id = TEGRA114_CLK_HCLK },
925 { .con_id = "pclk", .dt_id = TEGRA114_CLK_PCLK },
5ab5d404 926 { .con_id = "fuse", .dt_id = TEGRA114_CLK_FUSE },
73d37e4c
PDS		 927 { .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC },
928 { .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER },
929};
930
167d5366
PDS		 931static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
932 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
933};
934static u32 mux_pllm_pllc2_c_c3_pllp_plla_idx[] = {
935 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
936};
937
343a607c 938static struct clk **clks;
2cb5efef
PDS		 939
940static unsigned long osc_freq;
941static unsigned long pll_ref_freq;
942
943static int __init tegra114_osc_clk_init(void __iomem *clk_base)
944{
945 struct clk *clk;
946 u32 val, pll_ref_div;
947
948 val = readl_relaxed(clk_base + OSC_CTRL);
949
950 osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT];
951 if (!osc_freq) {
952 WARN_ON(1);
953 return -EINVAL;
954 }
955
956 /* clk_m */
957 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
958 osc_freq);
c9e2d69a 959 clks[TEGRA114_CLK_CLK_M] = clk;
2cb5efef
PDS		 960
961 /* pll_ref */
962 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
963 pll_ref_div = 1 << val;
964 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
965 CLK_SET_RATE_PARENT, 1, pll_ref_div);
c9e2d69a 966 clks[TEGRA114_CLK_PLL_REF] = clk;
2cb5efef
PDS		 967
968 pll_ref_freq = osc_freq / pll_ref_div;
969
970 return 0;
971}
972
973static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
974{
975 struct clk *clk;
976
977 /* clk_32k */
978 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
979 32768);
c9e2d69a 980 clks[TEGRA114_CLK_CLK_32K] = clk;
2cb5efef
PDS		 981
982 /* clk_m_div2 */
983 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
984 CLK_SET_RATE_PARENT, 1, 2);
c9e2d69a 985 clks[TEGRA114_CLK_CLK_M_DIV2] = clk;
2cb5efef
PDS		 986
987 /* clk_m_div4 */
988 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
989 CLK_SET_RATE_PARENT, 1, 4);
c9e2d69a 990 clks[TEGRA114_CLK_CLK_M_DIV4] = clk;
2cb5efef
PDS		 991
992}
993
994static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
995{
996 u32 reg;
997 int i;
998
999 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1000 if (osc_freq == utmi_parameters[i].osc_frequency)
1001 break;
1002 }
1003
1004 if (i >= ARRAY_SIZE(utmi_parameters)) {
1005 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
1006 osc_freq);
1007 return;
1008 }
1009
1010 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
1011
1012 /* Program UTMIP PLL stable and active counts */
1013 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1014 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1015 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
1016
1017 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1018
1019 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
1020 active_delay_count);
1021
1022 /* Remove power downs from UTMIP PLL control bits */
1023 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1024 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1025 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1026
1027 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
1028
1029 /* Program UTMIP PLL delay and oscillator frequency counts */
1030 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1031 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1032
1033 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
1034 enable_delay_count);
1035
1036 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1037 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
1038 xtal_freq_count);
1039
1040 /* Remove power downs from UTMIP PLL control bits */
1041 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1042 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1043 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1044 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1045 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1046
1047 /* Setup HW control of UTMIPLL */
1048 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1049 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1050 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1051 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1052 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1053
1054 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1055 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1056 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1057 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1058
1059 udelay(1);
1060
1061 /* Setup SW override of UTMIPLL assuming USB2.0
1062 ports are assigned to USB2 */
1063 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1064 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1065 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1066 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1067
1068 udelay(1);
1069
1070 /* Enable HW control UTMIPLL */
1071 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1072 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1073 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1074}
1075
2cb5efef
PDS		 1076static void __init tegra114_pll_init(void __iomem *clk_base,
1077 void __iomem *pmc)
1078{
1079 u32 val;
1080 struct clk *clk;
1081
1082 /* PLLC */
04edb099 1083 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
ebe142b2 1084 pmc, 0, &pll_c_params, NULL);
04edb099
PDS		 1085 clks[TEGRA114_CLK_PLL_C] = clk;
1086
1087 /* PLLC_OUT1 */
1088 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1089 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1090 8, 8, 1, NULL);
1091 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1092 clk_base + PLLC_OUT, 1, 0,
1093 CLK_SET_RATE_PARENT, 0, NULL);
04edb099 1094 clks[TEGRA114_CLK_PLL_C_OUT1] = clk;
2cb5efef
PDS		 1095
1096 /* PLLC2 */
ebe142b2
PDS		 1097 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
1098 &pll_c2_params, NULL);
c9e2d69a 1099 clks[TEGRA114_CLK_PLL_C2] = clk;
2cb5efef
PDS		 1100
1101 /* PLLC3 */
ebe142b2
PDS		 1102 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
1103 &pll_c3_params, NULL);
c9e2d69a 1104 clks[TEGRA114_CLK_PLL_C3] = clk;
2cb5efef 1105
2cb5efef 1106 /* PLLM */
2cb5efef 1107 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
ebe142b2
PDS		 1108 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1109 &pll_m_params, NULL);
c9e2d69a 1110 clks[TEGRA114_CLK_PLL_M] = clk;
2cb5efef
PDS		 1111
1112 /* PLLM_OUT1 */
1113 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
1114 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1115 8, 8, 1, NULL);
1116 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1117 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
1118 CLK_SET_RATE_PARENT, 0, NULL);
c9e2d69a 1119 clks[TEGRA114_CLK_PLL_M_OUT1] = clk;
2cb5efef
PDS		 1120
1121 /* PLLM_UD */
1122 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1123 CLK_SET_RATE_PARENT, 1, 1);
1124
2cb5efef
PDS		 1125 /* PLLU */
1126 val = readl(clk_base + pll_u_params.base_reg);
1127 val &= ~BIT(24); /* disable PLLU_OVERRIDE */
1128 writel(val, clk_base + pll_u_params.base_reg);
1129
1130 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
ebe142b2 1131 &pll_u_params, &pll_u_lock);
c9e2d69a 1132 clks[TEGRA114_CLK_PLL_U] = clk;
2cb5efef
PDS		 1133
1134 tegra114_utmi_param_configure(clk_base);
1135
1136 /* PLLU_480M */
1137 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1138 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1139 22, 0, &pll_u_lock);
c9e2d69a 1140 clks[TEGRA114_CLK_PLL_U_480M] = clk;
2cb5efef
PDS		 1141
1142 /* PLLU_60M */
1143 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1144 CLK_SET_RATE_PARENT, 1, 8);
c9e2d69a 1145 clks[TEGRA114_CLK_PLL_U_60M] = clk;
2cb5efef
PDS		 1146
1147 /* PLLU_48M */
1148 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1149 CLK_SET_RATE_PARENT, 1, 10);
c9e2d69a 1150 clks[TEGRA114_CLK_PLL_U_48M] = clk;
2cb5efef
PDS		 1151
1152 /* PLLU_12M */
1153 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1154 CLK_SET_RATE_PARENT, 1, 40);
c9e2d69a 1155 clks[TEGRA114_CLK_PLL_U_12M] = clk;
2cb5efef
PDS		 1156
1157 /* PLLD */
1158 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
ebe142b2 1159 &pll_d_params, &pll_d_lock);
c9e2d69a 1160 clks[TEGRA114_CLK_PLL_D] = clk;
2cb5efef
PDS		 1161
1162 /* PLLD_OUT0 */
1163 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1164 CLK_SET_RATE_PARENT, 1, 2);
c9e2d69a 1165 clks[TEGRA114_CLK_PLL_D_OUT0] = clk;
2cb5efef
PDS		 1166
1167 /* PLLD2 */
1168 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,
ebe142b2 1169 &pll_d2_params, &pll_d2_lock);
c9e2d69a 1170 clks[TEGRA114_CLK_PLL_D2] = clk;
2cb5efef
PDS		 1171
1172 /* PLLD2_OUT0 */
1173 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1174 CLK_SET_RATE_PARENT, 1, 2);
c9e2d69a 1175 clks[TEGRA114_CLK_PLL_D2_OUT0] = clk;
2cb5efef 1176
2cb5efef 1177 /* PLLRE */
2cb5efef 1178 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
ebe142b2 1179 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
c9e2d69a 1180 clks[TEGRA114_CLK_PLL_RE_VCO] = clk;
2cb5efef
PDS		 1181
1182 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1183 clk_base + PLLRE_BASE, 16, 4, 0,
1184 pll_re_div_table, &pll_re_lock);
c9e2d69a 1185 clks[TEGRA114_CLK_PLL_RE_OUT] = clk;
2cb5efef
PDS		 1186
1187 /* PLLE */
8e9cc80a 1188 clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_ref",
ebe142b2 1189 clk_base, 0, &pll_e_params, NULL);
c9e2d69a 1190 clks[TEGRA114_CLK_PLL_E_OUT0] = clk;
2cb5efef
PDS		 1191}
1192
167d5366
PDS		 1193#define CLK_SOURCE_VI_SENSOR 0x1a8
1194
1195static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1196 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR),
1197};
1198
76ebc134
PDS		 1199static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1200 void __iomem *pmc_base)
2cb5efef 1201{
2cb5efef 1202 struct clk *clk;
167d5366
PDS		 1203 struct tegra_periph_init_data *data;
1204 int i;
76ebc134 1205
5c992afc
AB		 1206 /* xusb_ss_div2 */
1207 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
1208 1, 2);
1209 clks[TEGRA114_CLK_XUSB_SS_DIV2] = clk;
76ebc134
PDS		 1210
1211 /* dsia mux */
2cb5efef 1212 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
819c1de3
JH		 1213 ARRAY_SIZE(mux_plld_out0_plld2_out0),
1214 CLK_SET_RATE_NO_REPARENT,
2cb5efef 1215 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
c9e2d69a 1216 clks[TEGRA114_CLK_DSIA_MUX] = clk;
2cb5efef 1217
76ebc134 1218 /* dsib mux */
2cb5efef 1219 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
819c1de3
JH		 1220 ARRAY_SIZE(mux_plld_out0_plld2_out0),
1221 CLK_SET_RATE_NO_REPARENT,
2cb5efef 1222 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
c9e2d69a 1223 clks[TEGRA114_CLK_DSIB_MUX] = clk;
2cb5efef 1224
b270491e
MZ		 1225 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
1226 0, 48, periph_clk_enb_refcnt);
1227 clks[TEGRA114_CLK_DSIA] = clk;
1228
1229 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
1230 0, 82, periph_clk_enb_refcnt);
1231 clks[TEGRA114_CLK_DSIB] = clk;
1232
76ebc134 1233 /* emc mux */
2cb5efef 1234 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
819c1de3
JH		 1235 ARRAY_SIZE(mux_pllmcp_clkm),
1236 CLK_SET_RATE_NO_REPARENT,
2cb5efef 1237 clk_base + CLK_SOURCE_EMC,
4f4f85fa
TR		 1238 29, 3, 0, &emc_lock);
1239
1240 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
1241 &emc_lock);
1242 clks[TEGRA114_CLK_MC] = clk;
d5ff89a8 1243
167d5366
PDS		 1244 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1245 data = &tegra_periph_clk_list[i];
1246 clk = tegra_clk_register_periph(data->name,
1247 data->p.parent_names, data->num_parents,
1248 &data->periph, clk_base, data->offset, data->flags);
1249 clks[data->clk_id] = clk;
1250 }
1251
76ebc134
PDS		 1252 tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks,
1253 &pll_p_params);
2cb5efef
PDS		 1254}
1255
31972fd9
JL		 1256/* Tegra114 CPU clock and reset control functions */
1257static void tegra114_wait_cpu_in_reset(u32 cpu)
1258{
1259 unsigned int reg;
1260
1261 do {
1262 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1263 cpu_relax();
1264 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1265}
1266static void tegra114_disable_cpu_clock(u32 cpu)
1267{
1268 /* flow controller would take care in the power sequence. */
1269}
1270
ad7d1140
JL		 1271#ifdef CONFIG_PM_SLEEP
1272static void tegra114_cpu_clock_suspend(void)
1273{
1274 /* switch coresite to clk_m, save off original source */
1275 tegra114_cpu_clk_sctx.clk_csite_src =
1276 readl(clk_base + CLK_SOURCE_CSITE);
1277 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
0017f447
JL		 1278
1279 tegra114_cpu_clk_sctx.cclkg_burst =
1280 readl(clk_base + CCLKG_BURST_POLICY);
1281 tegra114_cpu_clk_sctx.cclkg_divider =
1282 readl(clk_base + CCLKG_BURST_POLICY + 4);
ad7d1140
JL		 1283}
1284
1285static void tegra114_cpu_clock_resume(void)
1286{
1287 writel(tegra114_cpu_clk_sctx.clk_csite_src,
1288 clk_base + CLK_SOURCE_CSITE);
0017f447
JL		 1289
1290 writel(tegra114_cpu_clk_sctx.cclkg_burst,
1291 clk_base + CCLKG_BURST_POLICY);
1292 writel(tegra114_cpu_clk_sctx.cclkg_divider,
1293 clk_base + CCLKG_BURST_POLICY + 4);
ad7d1140
JL		 1294}
1295#endif
1296
31972fd9
JL		 1297static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
1298 .wait_for_reset = tegra114_wait_cpu_in_reset,
1299 .disable_clock = tegra114_disable_cpu_clock,
ad7d1140
JL		 1300#ifdef CONFIG_PM_SLEEP
1301 .suspend = tegra114_cpu_clock_suspend,
1302 .resume = tegra114_cpu_clock_resume,
1303#endif
31972fd9 1304};
2cb5efef
PDS		 1305
1306static const struct of_device_id pmc_match[] __initconst = {
1307 { .compatible = "nvidia,tegra114-pmc" },
1308 {},
1309};
1310
9e60121f
PW		 1311/*
1312 * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5
1313 * breaks
1314 */
056dfcf6 1315static struct tegra_clk_init_table init_table[] __initdata = {
c9e2d69a
PDS		 1316 {TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0},
1317 {TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0},
1318 {TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0},
1319 {TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0},
1320 {TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1},
1321 {TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1},
1322 {TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1},
1323 {TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1},
1324 {TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1},
1325 {TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
1326 {TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
1327 {TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
1328 {TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
1329 {TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
897e1dde 1330 {TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0},
c9e2d69a
PDS		 1331 {TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1},
1332 {TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1},
77f71730
MP		 1333 {TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0},
1334 {TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0},
f67a8d21
TR		 1335 {TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0},
1336 {TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0},
39409aa4
TR		 1337 {TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0},
1338 {TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0},
4a7f10d6
AB		 1339 {TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0},
1340 {TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0},
1341 {TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0},
1342 {TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0},
1343 {TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0},
1344 {TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0},
c9e2d69a
PDS		 1345 /* This MUST be the last entry. */
1346 {TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0},
2cb5efef
PDS		 1347};
1348
1349static void __init tegra114_clock_apply_init_table(void)
1350{
c9e2d69a 1351 tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX);
2cb5efef
PDS		 1352}
1353
25c9ded6
PW		 1354
1355/**
1356 * tegra114_car_barrier - wait for pending writes to the CAR to complete
1357 *
1358 * Wait for any outstanding writes to the CAR MMIO space from this CPU
1359 * to complete before continuing execution. No return value.
1360 */
1361static void tegra114_car_barrier(void)
1362{
1363 wmb(); /* probably unnecessary */
1364 readl_relaxed(clk_base + CPU_FINETRIM_SELECT);
1365}
1366
1367/**
1368 * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays
1369 *
1370 * When the CPU rail voltage is in the high-voltage range, use the
1371 * built-in hardwired clock propagation delays in the CPU clock
1372 * shaper. No return value.
1373 */
1374void tegra114_clock_tune_cpu_trimmers_high(void)
1375{
1376 u32 select = 0;
1377
1378 /* Use hardwired rise->rise & fall->fall clock propagation delays */
1379 select |= ~(CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1380 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1381 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1382 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
1383
1384 tegra114_car_barrier();
1385}
1386EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_high);
1387
1388/**
1389 * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays
1390 *
1391 * When the CPU rail voltage is in the low-voltage range, use the
1392 * extended clock propagation delays set by
1393 * tegra114_clock_tune_cpu_trimmers_init(). The intention is to
1394 * maintain the input clock duty cycle that the FCPU subsystem
1395 * expects. No return value.
1396 */
1397void tegra114_clock_tune_cpu_trimmers_low(void)
1398{
1399 u32 select = 0;
1400
1401 /*
1402 * Use software-specified rise->rise & fall->fall clock
1403 * propagation delays (from
1404 * tegra114_clock_tune_cpu_trimmers_init()
1405 */
1406 select |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1407 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1408 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1409 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
1410
1411 tegra114_car_barrier();
1412}
1413EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_low);
1414
1415/**
1416 * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays
1417 *
1418 * Program extended clock propagation delays into the FCPU clock
1419 * shaper and enable them. XXX Define the purpose - peak current
1420 * reduction? No return value.
1421 */
1422/* XXX Initial voltage rail state assumption issues? */
1423void tegra114_clock_tune_cpu_trimmers_init(void)
1424{
1425 u32 dr = 0, r = 0;
1426
1427 /* Increment the rise->rise clock delay by four steps */
1428 r |= (CPU_FINETRIM_R_FCPU_1_MASK | CPU_FINETRIM_R_FCPU_2_MASK |
1429 CPU_FINETRIM_R_FCPU_3_MASK | CPU_FINETRIM_R_FCPU_4_MASK |
1430 CPU_FINETRIM_R_FCPU_5_MASK | CPU_FINETRIM_R_FCPU_6_MASK);
1431 writel_relaxed(r, clk_base + CPU_FINETRIM_R);
1432
1433 /*
1434 * Use the rise->rise clock propagation delay specified in the
1435 * r field
1436 */
1437 dr |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1438 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1439 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1440 writel_relaxed(dr, clk_base + CPU_FINETRIM_DR);
1441
1442 tegra114_clock_tune_cpu_trimmers_low();
1443}
1444EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init);
1445
1c472d8e
PW		 1446/**
1447 * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
1448 *
1449 * Assert the reset line of the DFLL's DVCO. No return value.
1450 */
1451void tegra114_clock_assert_dfll_dvco_reset(void)
1452{
1453 u32 v;
1454
1455 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1456 v |= (1 << DVFS_DFLL_RESET_SHIFT);
1457 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1458 tegra114_car_barrier();
1459}
1460EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
1461
1462/**
1463 * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
1464 *
1465 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
1466 * operate. No return value.
1467 */
1468void tegra114_clock_deassert_dfll_dvco_reset(void)
1469{
1470 u32 v;
1471
1472 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1473 v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
1474 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1475 tegra114_car_barrier();
1476}
1477EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset);
1478
061cec92 1479static void __init tegra114_clock_init(struct device_node *np)
2cb5efef
PDS		 1480{
1481 struct device_node *node;
2cb5efef
PDS		 1482
1483 clk_base = of_iomap(np, 0);
1484 if (!clk_base) {
1485 pr_err("ioremap tegra114 CAR failed\n");
1486 return;
1487 }
1488
1489 node = of_find_matching_node(NULL, pmc_match);
1490 if (!node) {
1491 pr_err("Failed to find pmc node\n");
1492 WARN_ON(1);
1493 return;
1494 }
1495
1496 pmc_base = of_iomap(node, 0);
1497 if (!pmc_base) {
1498 pr_err("Can't map pmc registers\n");
1499 WARN_ON(1);
1500 return;
1501 }
1502
6d5b988e
SW		 1503 clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX,
1504 TEGRA114_CLK_PERIPH_BANKS);
343a607c 1505 if (!clks)
2cb5efef
PDS		 1506 return;
1507
343a607c 1508 if (tegra114_osc_clk_init(clk_base) < 0)
d5ff89a8
PDS		 1509 return;
1510
2cb5efef
PDS		 1511 tegra114_fixed_clk_init(clk_base);
1512 tegra114_pll_init(clk_base, pmc_base);
76ebc134 1513 tegra114_periph_clk_init(clk_base, pmc_base);
6609dbe4 1514 tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, &pll_a_params);
de4f30fd 1515 tegra_pmc_clk_init(pmc_base, tegra114_clks);
a7c8485a
PDS		 1516 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
1517 &pll_x_params);
2cb5efef 1518
343a607c 1519 tegra_add_of_provider(np);
73d37e4c 1520 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
2cb5efef
PDS		 1521
1522 tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
1523
1524 tegra_cpu_car_ops = &tegra114_cpu_car_ops;
1525}
061cec92 1526CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init);
Linux 6.x block layer and io_uring tree(s)