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Merge tag 'for-linus-5.0-rc3-tag' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / clk / tegra / clk-tegra-periph.c
CommitLineData
76ebc134
PDS		 1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
76ebc134
PDS		 18#include <linux/clk-provider.h>
19#include <linux/clkdev.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/clk/tegra.h>
25
26#include "clk.h"
27#include "clk-id.h"
28
29#define CLK_SOURCE_I2S0 0x1d8
30#define CLK_SOURCE_I2S1 0x100
31#define CLK_SOURCE_I2S2 0x104
32#define CLK_SOURCE_NDFLASH 0x160
33#define CLK_SOURCE_I2S3 0x3bc
34#define CLK_SOURCE_I2S4 0x3c0
35#define CLK_SOURCE_SPDIF_OUT 0x108
36#define CLK_SOURCE_SPDIF_IN 0x10c
37#define CLK_SOURCE_PWM 0x110
38#define CLK_SOURCE_ADX 0x638
3b34d821 39#define CLK_SOURCE_ADX1 0x670
76ebc134 40#define CLK_SOURCE_AMX 0x63c
3b34d821 41#define CLK_SOURCE_AMX1 0x674
76ebc134
PDS		 42#define CLK_SOURCE_HDA 0x428
43#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
44#define CLK_SOURCE_SBC1 0x134
45#define CLK_SOURCE_SBC2 0x118
46#define CLK_SOURCE_SBC3 0x11c
47#define CLK_SOURCE_SBC4 0x1b4
48#define CLK_SOURCE_SBC5 0x3c8
49#define CLK_SOURCE_SBC6 0x3cc
50#define CLK_SOURCE_SATA_OOB 0x420
51#define CLK_SOURCE_SATA 0x424
52#define CLK_SOURCE_NDSPEED 0x3f8
53#define CLK_SOURCE_VFIR 0x168
54#define CLK_SOURCE_SDMMC1 0x150
55#define CLK_SOURCE_SDMMC2 0x154
56#define CLK_SOURCE_SDMMC3 0x1bc
57#define CLK_SOURCE_SDMMC4 0x164
58#define CLK_SOURCE_CVE 0x140
59#define CLK_SOURCE_TVO 0x188
60#define CLK_SOURCE_TVDAC 0x194
61#define CLK_SOURCE_VDE 0x1c8
62#define CLK_SOURCE_CSITE 0x1d4
63#define CLK_SOURCE_LA 0x1f8
64#define CLK_SOURCE_TRACE 0x634
65#define CLK_SOURCE_OWR 0x1cc
66#define CLK_SOURCE_NOR 0x1d0
67#define CLK_SOURCE_MIPI 0x174
68#define CLK_SOURCE_I2C1 0x124
69#define CLK_SOURCE_I2C2 0x198
70#define CLK_SOURCE_I2C3 0x1b8
71#define CLK_SOURCE_I2C4 0x3c4
72#define CLK_SOURCE_I2C5 0x128
3b34d821 73#define CLK_SOURCE_I2C6 0x65c
76ebc134
PDS		 74#define CLK_SOURCE_UARTA 0x178
75#define CLK_SOURCE_UARTB 0x17c
76#define CLK_SOURCE_UARTC 0x1a0
77#define CLK_SOURCE_UARTD 0x1c0
78#define CLK_SOURCE_UARTE 0x1c4
79#define CLK_SOURCE_3D 0x158
80#define CLK_SOURCE_2D 0x15c
81#define CLK_SOURCE_MPE 0x170
82#define CLK_SOURCE_VI_SENSOR 0x1a8
83#define CLK_SOURCE_VI 0x148
84#define CLK_SOURCE_EPP 0x16c
85#define CLK_SOURCE_MSENC 0x1f0
86#define CLK_SOURCE_TSEC 0x1f4
87#define CLK_SOURCE_HOST1X 0x180
88#define CLK_SOURCE_HDMI 0x18c
89#define CLK_SOURCE_DISP1 0x138
90#define CLK_SOURCE_DISP2 0x13c
91#define CLK_SOURCE_CILAB 0x614
92#define CLK_SOURCE_CILCD 0x618
93#define CLK_SOURCE_CILE 0x61c
94#define CLK_SOURCE_DSIALP 0x620
95#define CLK_SOURCE_DSIBLP 0x624
96#define CLK_SOURCE_TSENSOR 0x3b8
97#define CLK_SOURCE_D_AUDIO 0x3d0
98#define CLK_SOURCE_DAM0 0x3d8
99#define CLK_SOURCE_DAM1 0x3dc
100#define CLK_SOURCE_DAM2 0x3e0
101#define CLK_SOURCE_ACTMON 0x3e8
102#define CLK_SOURCE_EXTERN1 0x3ec
103#define CLK_SOURCE_EXTERN2 0x3f0
104#define CLK_SOURCE_EXTERN3 0x3f4
105#define CLK_SOURCE_I2CSLOW 0x3fc
106#define CLK_SOURCE_SE 0x42c
107#define CLK_SOURCE_MSELECT 0x3b4
108#define CLK_SOURCE_DFLL_REF 0x62c
109#define CLK_SOURCE_DFLL_SOC 0x630
110#define CLK_SOURCE_SOC_THERM 0x644
111#define CLK_SOURCE_XUSB_HOST_SRC 0x600
112#define CLK_SOURCE_XUSB_FALCON_SRC 0x604
113#define CLK_SOURCE_XUSB_FS_SRC 0x608
114#define CLK_SOURCE_XUSB_SS_SRC 0x610
115#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
3b34d821
PDS		 116#define CLK_SOURCE_ISP 0x144
117#define CLK_SOURCE_SOR0 0x414
118#define CLK_SOURCE_DPAUX 0x418
3b34d821
PDS		 119#define CLK_SOURCE_ENTROPY 0x628
120#define CLK_SOURCE_VI_SENSOR2 0x658
121#define CLK_SOURCE_HDMI_AUDIO 0x668
122#define CLK_SOURCE_VIC03 0x678
123#define CLK_SOURCE_CLK72MHZ 0x66c
dc37fec4
RK		 124#define CLK_SOURCE_DBGAPB 0x718
125#define CLK_SOURCE_NVENC 0x6a0
126#define CLK_SOURCE_NVDEC 0x698
127#define CLK_SOURCE_NVJPG 0x69c
128#define CLK_SOURCE_APE 0x6c0
dc37fec4
RK		 129#define CLK_SOURCE_SDMMC_LEGACY 0x694
130#define CLK_SOURCE_QSPI 0x6c4
131#define CLK_SOURCE_VI_I2C 0x6c8
132#define CLK_SOURCE_MIPIBIF 0x660
133#define CLK_SOURCE_UARTAPE 0x710
134#define CLK_SOURCE_TSECB 0x6d8
135#define CLK_SOURCE_MAUD 0x6d4
136#define CLK_SOURCE_USB2_HSIC_TRK 0x6cc
6cfc8bc9
PDS		 137#define CLK_SOURCE_DMIC1 0x64c
138#define CLK_SOURCE_DMIC2 0x650
139#define CLK_SOURCE_DMIC3 0x6bc
76ebc134
PDS		 140
141#define MASK(x) (BIT(x) - 1)
142
143#define MUX(_name, _parents, _offset, \
144 _clk_num, _gate_flags, _clk_id) \
145 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
146 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
bc44275b
PDS		 147 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
148 NULL)
76ebc134
PDS		 149
150#define MUX_FLAGS(_name, _parents, _offset,\
151 _clk_num, _gate_flags, _clk_id, flags)\
152 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
153 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
bc44275b
PDS		 154 _clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\
155 NULL)
76ebc134
PDS		 156
157#define MUX8(_name, _parents, _offset, \
158 _clk_num, _gate_flags, _clk_id) \
159 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
160 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
bc44275b
PDS		 161 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
162 NULL)
76ebc134 163
b29f9e92
PDS		 164#define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \
165 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
166 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
167 0, TEGRA_PERIPH_NO_GATE, _clk_id,\
168 _parents##_idx, 0, _lock)
169
34ac2c27
PDS		 170#define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \
171 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
172 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
173 0, TEGRA_PERIPH_NO_GATE, _clk_id,\
174 _parents##_idx, 0, NULL)
175
76ebc134
PDS		 176#define INT(_name, _parents, _offset, \
177 _clk_num, _gate_flags, _clk_id) \
178 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
179 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
180 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
bc44275b 181 _clk_id, _parents##_idx, 0, NULL)
76ebc134
PDS		 182
183#define INT_FLAGS(_name, _parents, _offset,\
184 _clk_num, _gate_flags, _clk_id, flags)\
185 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
186 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
187 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
bc44275b 188 _clk_id, _parents##_idx, flags, NULL)
76ebc134
PDS		 189
190#define INT8(_name, _parents, _offset,\
191 _clk_num, _gate_flags, _clk_id) \
192 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
193 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
194 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
bc44275b 195 _clk_id, _parents##_idx, 0, NULL)
76ebc134
PDS		 196
197#define UART(_name, _parents, _offset,\
198 _clk_num, _clk_id) \
199 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
200 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
201 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
bc44275b 202 _parents##_idx, 0, NULL)
76ebc134 203
dc37fec4
RK		 204#define UART8(_name, _parents, _offset,\
205 _clk_num, _clk_id) \
206 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
207 29, MASK(3), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
208 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
209 _parents##_idx, 0, NULL)
210
76ebc134
PDS		 211#define I2C(_name, _parents, _offset,\
212 _clk_num, _clk_id) \
213 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
214 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
82c875ca
AF		 215 _clk_num, TEGRA_PERIPH_ON_APB, _clk_id, \
216 _parents##_idx, 0, NULL)
76ebc134
PDS		 217
218#define XUSB(_name, _parents, _offset, \
219 _clk_num, _gate_flags, _clk_id) \
220 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
221 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
222 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
bc44275b 223 _clk_id, _parents##_idx, 0, NULL)
76ebc134
PDS		 224
225#define AUDIO(_name, _offset, _clk_num,\
226 _gate_flags, _clk_id) \
227 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, mux_d_audio_clk, \
228 _offset, 16, 0xE01F, 0, 0, 8, 1, \
229 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags, \
bc44275b 230 _clk_id, mux_d_audio_clk_idx, 0, NULL)
76ebc134
PDS		 231
232#define NODIV(_name, _parents, _offset, \
233 _mux_shift, _mux_mask, _clk_num, \
bc44275b 234 _gate_flags, _clk_id, _lock) \
76ebc134
PDS		 235 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
236 _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\
237 _clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\
bc44275b 238 _clk_id, _parents##_idx, 0, _lock)
76ebc134
PDS		 239
240#define GATE(_name, _parent_name, \
241 _clk_num, _gate_flags, _clk_id, _flags) \
242 { \
243 .name = _name, \
244 .clk_id = _clk_id, \
245 .p.parent_name = _parent_name, \
246 .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0, \
f081c896 247 _clk_num, _gate_flags, NULL, NULL), \
76ebc134
PDS		 248 .flags = _flags \
249 }
250
dc37fec4
RK		 251#define DIV8(_name, _parent_name, _offset, _clk_id, _flags) \
252 { \
253 .name = _name, \
254 .clk_id = _clk_id, \
255 .p.parent_name = _parent_name, \
256 .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 8, 1, \
257 TEGRA_DIVIDER_ROUND_UP, 0, 0, \
258 NULL, NULL), \
259 .offset = _offset, \
260 .flags = _flags, \
261 }
262
76ebc134
PDS		 263#define PLLP_BASE 0xa0
264#define PLLP_MISC 0xac
dc37fec4 265#define PLLP_MISC1 0x680
76ebc134
PDS		 266#define PLLP_OUTA 0xa4
267#define PLLP_OUTB 0xa8
3b34d821 268#define PLLP_OUTC 0x67c
76ebc134
PDS		 269
270#define PLL_BASE_LOCK BIT(27)
271#define PLL_MISC_LOCK_ENABLE 18
272
273static DEFINE_SPINLOCK(PLLP_OUTA_lock);
274static DEFINE_SPINLOCK(PLLP_OUTB_lock);
3b34d821
PDS		 275static DEFINE_SPINLOCK(PLLP_OUTC_lock);
276static DEFINE_SPINLOCK(sor0_lock);
76ebc134
PDS		 277
278#define MUX_I2S_SPDIF(_id) \
279static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
280 #_id, "pll_p",\
281 "clk_m"};
282MUX_I2S_SPDIF(audio0)
283MUX_I2S_SPDIF(audio1)
284MUX_I2S_SPDIF(audio2)
285MUX_I2S_SPDIF(audio3)
286MUX_I2S_SPDIF(audio4)
287MUX_I2S_SPDIF(audio)
288
289#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL
290#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL
291#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL
292#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL
293#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL
294#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL
295
296static const char *mux_pllp_pllc_pllm_clkm[] = {
297 "pll_p", "pll_c", "pll_m", "clk_m"
298};
299#define mux_pllp_pllc_pllm_clkm_idx NULL
300
301static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" };
302#define mux_pllp_pllc_pllm_idx NULL
303
304static const char *mux_pllp_pllc_clk32_clkm[] = {
305 "pll_p", "pll_c", "clk_32k", "clk_m"
306};
307#define mux_pllp_pllc_clk32_clkm_idx NULL
308
309static const char *mux_plla_pllc_pllp_clkm[] = {
310 "pll_a_out0", "pll_c", "pll_p", "clk_m"
311};
312#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx
313
314static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = {
315 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
316};
317static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = {
318 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
319};
320
321static const char *mux_pllp_clkm[] = {
322 "pll_p", "clk_m"
323};
324static u32 mux_pllp_clkm_idx[] = {
325 [0] = 0, [1] = 3,
326};
327
dc37fec4
RK		 328static const char *mux_pllp_clkm_2[] = {
329 "pll_p", "clk_m"
330};
331static u32 mux_pllp_clkm_2_idx[] = {
332 [0] = 2, [1] = 6,
333};
334
335static const char *mux_pllc2_c_c3_pllp_plla1_clkm[] = {
336 "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a1", "clk_m"
337};
338static u32 mux_pllc2_c_c3_pllp_plla1_clkm_idx[] = {
339 [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 6, [5] = 7,
340};
341
342static const char *
343mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0[] = {
344 "pll_c4_out1", "pll_c", "pll_c4_out2", "pll_p", "clk_m",
345 "pll_a_out0", "pll_c4_out0"
346};
347static u32 mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0_idx[] = {
348 [0] = 0, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
349};
350
351static const char *mux_pllc_pllp_plla[] = {
352 "pll_c", "pll_p", "pll_a_out0"
353};
354static u32 mux_pllc_pllp_plla_idx[] = {
355 [0] = 1, [1] = 2, [2] = 3,
356};
357
358static const char *mux_clkm_pllc_pllp_plla[] = {
359 "clk_m", "pll_c", "pll_p", "pll_a_out0"
360};
361#define mux_clkm_pllc_pllp_plla_idx NULL
362
363static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm[] = {
364 "pll_c", "pll_p", "pll_a1", "pll_c2", "pll_c3", "clk_m"
365};
366static u32 mux_pllc_pllp_plla1_pllc2_c3_clkm_idx[] = {
367 [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6,
368};
369
370static const char *mux_pllc2_c_c3_pllp_clkm_plla1_pllc4[] = {
371 "pll_c2", "pll_c", "pll_c3", "pll_p", "clk_m", "pll_a1", "pll_c4_out0",
372};
373static u32 mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx[] = {
374 [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
375};
376
377static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4[] = {
378 "pll_c", "pll_p", "pll_a1", "pll_c2", "pll_c3", "clk_m", "pll_c4_out0",
379};
380#define mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4_idx \
381 mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx
382
383static const char *
384mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm[] = {
385 "pll_a_out0", "pll_c4_out0", "pll_c", "pll_c4_out1", "pll_p",
386 "pll_c4_out2", "clk_m"
387};
388#define mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm_idx NULL
389
76ebc134
PDS		 390static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
391 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
392};
393#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx
394
395static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
396 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
397 "pll_d2_out0", "clk_m"
398};
399#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
400
401static const char *mux_pllm_pllc_pllp_plla[] = {
402 "pll_m", "pll_c", "pll_p", "pll_a_out0"
403};
404#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
405
406static const char *mux_pllp_pllc_clkm[] = {
dc37fec4 407 "pll_p", "pll_c", "clk_m"
76ebc134
PDS		 408};
409static u32 mux_pllp_pllc_clkm_idx[] = {
410 [0] = 0, [1] = 1, [2] = 3,
411};
412
dc37fec4
RK		 413static const char *mux_pllp_pllc_clkm_1[] = {
414 "pll_p", "pll_c", "clk_m"
415};
416static u32 mux_pllp_pllc_clkm_1_idx[] = {
417 [0] = 0, [1] = 2, [2] = 5,
418};
419
420static const char *mux_pllp_pllc_plla_clkm[] = {
421 "pll_p", "pll_c", "pll_a_out0", "clk_m"
422};
423static u32 mux_pllp_pllc_plla_clkm_idx[] = {
424 [0] = 0, [1] = 2, [2] = 4, [3] = 6,
425};
426
427static const char *mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2[] = {
428 "pll_p", "pll_c", "pll_c4_out0", "pll_c4_out1", "clk_m", "pll_c4_out2"
429};
430static u32 mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2_idx[] = {
431 [0] = 0, [1] = 2, [2] = 3, [3] = 5, [4] = 6, [5] = 7,
432};
433
434static const char *
435mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = {
436 "pll_p", "pll_c_out1", "pll_c", "pll_c4_out2", "pll_c4_out1",
437 "clk_m", "pll_c4_out0"
438};
439static u32
440mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
441 [0] = 0, [1] = 1, [2] = 2, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
442};
443
444static const char *mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = {
445 "pll_p", "pll_c4_out2", "pll_c4_out1", "clk_m", "pll_c4_out0"
446};
447static u32 mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
448 [0] = 0, [1] = 3, [2] = 4, [3] = 6, [4] = 7,
449};
450
dc37fec4
RK		 451static const char *mux_pllp_pllc2_c_c3_clkm[] = {
452 "pll_p", "pll_c2", "pll_c", "pll_c3", "clk_m"
453};
454static u32 mux_pllp_pllc2_c_c3_clkm_idx[] = {
455 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 6,
456};
457
458static const char *mux_pllp_clkm_clk32_plle[] = {
459 "pll_p", "clk_m", "clk_32k", "pll_e"
460};
461static u32 mux_pllp_clkm_clk32_plle_idx[] = {
462 [0] = 0, [1] = 2, [2] = 4, [3] = 6,
463};
464
465static const char *mux_pllp_pllp_out3_clkm_clk32k_plla[] = {
466 "pll_p", "pll_p_out3", "clk_m", "clk_32k", "pll_a_out0"
467};
468#define mux_pllp_pllp_out3_clkm_clk32k_plla_idx NULL
469
470static const char *mux_pllp_out3_clkm_pllp_pllc4[] = {
471 "pll_p_out3", "clk_m", "pll_p", "pll_c4_out0", "pll_c4_out1",
472 "pll_c4_out2"
473};
474static u32 mux_pllp_out3_clkm_pllp_pllc4_idx[] = {
475 [0] = 0, [1] = 3, [2] = 4, [3] = 5, [4] = 6, [5] = 7,
476};
477
478static const char *mux_clkm_pllp_pllre[] = {
479 "clk_m", "pll_p_out_xusb", "pll_re_out"
480};
481static u32 mux_clkm_pllp_pllre_idx[] = {
482 [0] = 0, [1] = 1, [2] = 5,
483};
484
76ebc134
PDS		 485static const char *mux_pllp_pllc_clkm_clk32[] = {
486 "pll_p", "pll_c", "clk_m", "clk_32k"
487};
488#define mux_pllp_pllc_clkm_clk32_idx NULL
489
490static const char *mux_plla_clk32_pllp_clkm_plle[] = {
491 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
492};
493#define mux_plla_clk32_pllp_clkm_plle_idx NULL
494
495static const char *mux_clkm_pllp_pllc_pllre[] = {
496 "clk_m", "pll_p", "pll_c", "pll_re_out"
497};
498static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
499 [0] = 0, [1] = 1, [2] = 3, [3] = 5,
500};
501
502static const char *mux_clkm_48M_pllp_480M[] = {
503 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
504};
9d61707b
JL		 505static u32 mux_clkm_48M_pllp_480M_idx[] = {
506 [0] = 0, [1] = 2, [2] = 4, [3] = 6,
507};
76ebc134 508
dc37fec4
RK		 509static const char *mux_clkm_pllre_clk32_480M[] = {
510 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M"
511};
512#define mux_clkm_pllre_clk32_480M_idx NULL
513
76ebc134
PDS		 514static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
515 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
516};
517static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
518 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
519};
520
dc37fec4
RK		 521static const char *mux_pllp_out3_pllp_pllc_clkm[] = {
522 "pll_p_out3", "pll_p", "pll_c", "clk_m"
523};
524static u32 mux_pllp_out3_pllp_pllc_clkm_idx[] = {
525 [0] = 0, [1] = 1, [2] = 2, [3] = 6,
526};
527
528static const char *mux_ss_div2_60M[] = {
5c992afc
AB		 529 "xusb_ss_div2", "pll_u_60M"
530};
dc37fec4
RK		 531#define mux_ss_div2_60M_idx NULL
532
533static const char *mux_ss_div2_60M_ss[] = {
534 "xusb_ss_div2", "pll_u_60M", "xusb_ss_src"
535};
536#define mux_ss_div2_60M_ss_idx NULL
537
538static const char *mux_ss_clkm[] = {
539 "xusb_ss_src", "clk_m"
540};
541#define mux_ss_clkm_idx NULL
5c992afc 542
76ebc134
PDS		 543static const char *mux_d_audio_clk[] = {
544 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
545 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
546};
547static u32 mux_d_audio_clk_idx[] = {
548 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001,
549 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007,
550};
551
552static const char *mux_pllp_plld_pllc_clkm[] = {
553 "pll_p", "pll_d_out0", "pll_c", "clk_m"
554};
555#define mux_pllp_plld_pllc_clkm_idx NULL
3b34d821
PDS		 556static const char *mux_pllm_pllc_pllp_plla_clkm_pllc4[] = {
557 "pll_m", "pll_c", "pll_p", "pll_a_out0", "clk_m", "pll_c4",
558};
559static u32 mux_pllm_pllc_pllp_plla_clkm_pllc4_idx[] = {
560 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 6, [5] = 7,
561};
562
563static const char *mux_pllp_clkm1[] = {
564 "pll_p", "clk_m",
565};
566#define mux_pllp_clkm1_idx NULL
567
568static const char *mux_pllp3_pllc_clkm[] = {
569 "pll_p_out3", "pll_c", "pll_c2", "clk_m",
570};
571#define mux_pllp3_pllc_clkm_idx NULL
572
573static const char *mux_pllm_pllc_pllp_plla_pllc2_c3_clkm[] = {
574 "pll_m", "pll_c", "pll_p", "pll_a", "pll_c2", "pll_c3", "clk_m"
575};
a9952a76 576#define mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx NULL
3b34d821
PDS		 577
578static const char *mux_pllm_pllc2_c_c3_pllp_plla_pllc4[] = {
579 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0", "pll_c4",
580};
581static u32 mux_pllm_pllc2_c_c3_pllp_plla_pllc4_idx[] = {
582 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, [6] = 7,
583};
584
dc37fec4
RK		 585/* SOR1 mux'es */
586static const char *mux_pllp_plld_plld2_clkm[] = {
587 "pll_p", "pll_d_out0", "pll_d2_out0", "clk_m"
588};
589static u32 mux_pllp_plld_plld2_clkm_idx[] = {
590 [0] = 0, [1] = 2, [2] = 5, [3] = 6
591};
592
dc37fec4
RK		 593static const char *mux_pllp_pllre_clkm[] = {
594 "pll_p", "pll_re_out1", "clk_m"
595};
596
597static u32 mux_pllp_pllre_clkm_idx[] = {
598 [0] = 0, [1] = 2, [2] = 3,
599};
600
3b34d821
PDS		 601static const char *mux_clkm_plldp_sor0lvds[] = {
602 "clk_m", "pll_dp", "sor0_lvds",
603};
604#define mux_clkm_plldp_sor0lvds_idx NULL
76ebc134 605
6cfc8bc9
PDS		 606static const char * const mux_dmic1[] = {
607 "pll_a_out0", "dmic1_sync_clk", "pll_p", "clk_m"
608};
609#define mux_dmic1_idx NULL
610
611static const char * const mux_dmic2[] = {
612 "pll_a_out0", "dmic2_sync_clk", "pll_p", "clk_m"
613};
614#define mux_dmic2_idx NULL
615
616static const char * const mux_dmic3[] = {
617 "pll_a_out0", "dmic3_sync_clk", "pll_p", "clk_m"
618};
619#define mux_dmic3_idx NULL
620
76ebc134
PDS		 621static struct tegra_periph_init_data periph_clks[] = {
622 AUDIO("d_audio", CLK_SOURCE_D_AUDIO, 106, TEGRA_PERIPH_ON_APB, tegra_clk_d_audio),
623 AUDIO("dam0", CLK_SOURCE_DAM0, 108, TEGRA_PERIPH_ON_APB, tegra_clk_dam0),
624 AUDIO("dam1", CLK_SOURCE_DAM1, 109, TEGRA_PERIPH_ON_APB, tegra_clk_dam1),
625 AUDIO("dam2", CLK_SOURCE_DAM2, 110, TEGRA_PERIPH_ON_APB, tegra_clk_dam2),
626 I2C("i2c1", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, tegra_clk_i2c1),
627 I2C("i2c2", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, tegra_clk_i2c2),
628 I2C("i2c3", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, tegra_clk_i2c3),
629 I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, tegra_clk_i2c4),
630 I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, tegra_clk_i2c5),
dc37fec4 631 I2C("i2c6", mux_pllp_clkm, CLK_SOURCE_I2C6, 166, tegra_clk_i2c6),
76ebc134
PDS		 632 INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde),
633 INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi),
634 INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp),
635 INT("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x),
636 INT("mpe", mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60, 0, tegra_clk_mpe),
637 INT("2d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d),
638 INT("3d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d),
639 INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde_8),
640 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8),
3b34d821 641 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_9),
dc37fec4 642 INT8("vi", mux_pllc2_c_c3_pllp_clkm_plla1_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_10),
76ebc134
PDS		 643 INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp_8),
644 INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, tegra_clk_msenc),
645 INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec),
dc37fec4 646 INT("tsec", mux_pllp_pllc_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec_8),
76ebc134 647 INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8),
dc37fec4 648 INT8("host1x", mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_9),
76ebc134 649 INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),
dc37fec4 650 INT8("se", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),
76ebc134
PDS		 651 INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8),
652 INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8),
3b34d821 653 INT8("vic03", mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03),
dc37fec4 654 INT8("vic03", mux_pllc_pllp_plla1_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03_8),
76ebc134
PDS		 655 INT_FLAGS("mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, tegra_clk_mselect, CLK_IGNORE_UNUSED),
656 MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_i2s0),
657 MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_i2s1),
658 MUX("i2s2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, tegra_clk_i2s2),
659 MUX("i2s3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, tegra_clk_i2s3),
660 MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk_i2s4),
661 MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out),
662 MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in),
dc37fec4 663 MUX8("spdif_in", mux_pllp_pllc_clkm_1, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in_8),
76ebc134
PDS		 664 MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm),
665 MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx),
666 MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, tegra_clk_amx),
667 MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda),
dc37fec4 668 MUX("hda", mux_pllp_pllc_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda_8),
76ebc134 669 MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x),
dc37fec4 670 MUX8("hda2codec_2x", mux_pllp_pllc_plla_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x_8),
76ebc134 671 MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir),
18abd163
AB		 672 MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1),
673 MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2),
674 MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3),
675 MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4),
dc37fec4 676 MUX8("sdmmc1", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_9),
dc37fec4 677 MUX8("sdmmc3", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_9),
76ebc134
PDS		 678 MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
679 MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
680 MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
dc37fec4 681 MUX("owr", mux_pllp_pllc_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr_8),
76ebc134
PDS		 682 MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor),
683 MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, tegra_clk_mipi),
684 MUX("vi_sensor", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor),
dc37fec4 685 MUX("vi_sensor", mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_9),
76ebc134
PDS		 686 MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, tegra_clk_cilab),
687 MUX("cilcd", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, tegra_clk_cilcd),
688 MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, tegra_clk_cile),
689 MUX("dsialp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, 0, tegra_clk_dsialp),
690 MUX("dsiblp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, 0, tegra_clk_dsiblp),
691 MUX("tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, TEGRA_PERIPH_ON_APB, tegra_clk_tsensor),
692 MUX("actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, 0, tegra_clk_actmon),
693 MUX("dfll_ref", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_ref),
694 MUX("dfll_soc", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_soc),
695 MUX("i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, tegra_clk_i2cslow),
696 MUX("sbc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1),
697 MUX("sbc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2),
698 MUX("sbc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3),
699 MUX("sbc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4),
700 MUX("sbc5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5),
701 MUX("sbc6", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6),
702 MUX("cve", mux_pllp_plld_pllc_clkm, CLK_SOURCE_CVE, 49, 0, tegra_clk_cve),
703 MUX("tvo", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVO, 49, 0, tegra_clk_tvo),
704 MUX("tvdac", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVDAC, 53, 0, tegra_clk_tvdac),
705 MUX("ndflash", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash),
706 MUX("ndspeed", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed),
707 MUX("sata_oob", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob),
dc37fec4 708 MUX("sata_oob", mux_pllp_pllc_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob_8),
76ebc134 709 MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata),
dc37fec4 710 MUX("sata", mux_pllp_pllc_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata_8),
3b34d821
PDS		 711 MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1),
712 MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1),
167d5366 713 MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2),
dc37fec4 714 MUX("vi_sensor2", mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2_8),
18abd163
AB		 715 MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_8),
716 MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_8),
717 MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_8),
718 MUX8("sdmmc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_8),
76ebc134
PDS		 719 MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8),
720 MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8),
721 MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8),
722 MUX8("sbc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_8),
723 MUX8("sbc5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5_8),
724 MUX8("sbc6", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6_8),
dc37fec4
RK		 725 MUX("sbc1", mux_pllp_pllc_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_9),
726 MUX("sbc2", mux_pllp_pllc_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_9),
727 MUX("sbc3", mux_pllp_pllc_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_9),
728 MUX("sbc4", mux_pllp_pllc_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_9),
76ebc134
PDS		 729 MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8),
730 MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8),
731 MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi),
732 MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, tegra_clk_extern1),
733 MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2),
734 MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3),
735 MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm),
dc37fec4 736 MUX8("soc_therm", mux_clkm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm_8),
167d5366 737 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
3b34d821 738 MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8),
34ac2c27 739 MUX8_NOGATE("isp", mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4, CLK_SOURCE_ISP, tegra_clk_isp_9),
3b34d821 740 MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy),
dc37fec4 741 MUX8("entropy", mux_pllp_clkm_clk32_plle, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy_8),
3b34d821
PDS		 742 MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio),
743 MUX8("clk72mhz", mux_pllp3_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz),
dc37fec4 744 MUX8("clk72mhz", mux_pllp_out3_pllp_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz_8),
3b34d821 745 MUX8_NOGATE_LOCK("sor0_lvds", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_lvds, &sor0_lock),
76ebc134 746 MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED),
dc37fec4 747 MUX_FLAGS("csite", mux_pllp_pllre_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite_8, CLK_IGNORE_UNUSED),
bc44275b 748 NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL),
dc37fec4 749 NODIV("disp1", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1_8, NULL),
bc44275b 750 NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL),
dc37fec4 751 NODIV("disp2", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2_8, NULL),
3b34d821 752 NODIV("sor0", mux_clkm_plldp_sor0lvds, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),
76ebc134
PDS		 753 UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta),
754 UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb),
755 UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc),
756 UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd),
2edf3e03 757 UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte),
dc37fec4
RK		 758 UART8("uarta", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTA, 6, tegra_clk_uarta_8),
759 UART8("uartb", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTB, 7, tegra_clk_uartb_8),
760 UART8("uartc", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTC, 55, tegra_clk_uartc_8),
761 UART8("uartd", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTD, 65, tegra_clk_uartd_8),
76ebc134 762 XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src),
dc37fec4 763 XUSB("xusb_host_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src_8),
76ebc134 764 XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src),
dc37fec4 765 XUSB("xusb_falcon_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src_8),
76ebc134
PDS		 766 XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src),
767 XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src),
dc37fec4
RK		 768 XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src_8),
769 NODIV("xusb_hs_src", mux_ss_div2_60M, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src, NULL),
770 NODIV("xusb_hs_src", mux_ss_div2_60M_ss, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(2), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src_4, NULL),
771 NODIV("xusb_ssp_src", mux_ss_clkm, CLK_SOURCE_XUSB_SS_SRC, 24, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ssp_src, NULL),
76ebc134 772 XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),
dc37fec4
RK		 773 XUSB("xusb_dev_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src_8),
774 MUX8("dbgapb", mux_pllp_clkm_2, CLK_SOURCE_DBGAPB, 185, TEGRA_PERIPH_NO_RESET, tegra_clk_dbgapb),
736971be 775 MUX8("nvenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc),
dc37fec4
RK		 776 MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec),
777 MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg),
778 MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape),
dc37fec4
RK		 779 MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy),
780 MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi),
21e49032 781 I2C("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c),
dc37fec4
RK		 782 MUX("mipibif", mux_pllp_clkm, CLK_SOURCE_MIPIBIF, 173, TEGRA_PERIPH_ON_APB, tegra_clk_mipibif),
783 MUX("uartape", mux_pllp_pllc_clkm, CLK_SOURCE_UARTAPE, 212, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_uartape),
784 MUX8("tsecb", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_TSECB, 206, 0, tegra_clk_tsecb),
785 MUX8("maud", mux_pllp_pllp_out3_clkm_clk32k_plla, CLK_SOURCE_MAUD, 202, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_maud),
6cfc8bc9
PDS		 786 MUX8("dmic1", mux_dmic1, CLK_SOURCE_DMIC1, 161, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic1),
787 MUX8("dmic2", mux_dmic2, CLK_SOURCE_DMIC2, 162, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic2),
788 MUX8("dmic3", mux_dmic3, CLK_SOURCE_DMIC3, 197, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic3),
76ebc134
PDS		 789};
790
791static struct tegra_periph_init_data gate_clks[] = {
792 GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
28580386 793 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
76ebc134
PDS		 794 GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
795 GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
899f8095 796 GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0),
3ff46fd0 797 GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0),
76ebc134
PDS		 798 GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
799 GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
800 GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
801 GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
802 GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
803 GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0),
804 GATE("bsea", "clk_m", 62, 0, tegra_clk_bsea, 0),
805 GATE("bsev", "clk_m", 63, 0, tegra_clk_bsev, 0),
07314fc1 806 GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
76ebc134
PDS		 807 GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd, 0),
808 GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0),
809 GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0),
810 GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0),
e7a49675 811 GATE("afi", "mselect", 72, 0, tegra_clk_afi, 0),
76ebc134
PDS		 812 GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0),
813 GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0),
814 GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0),
815 GATE("dtv", "clk_m", 79, TEGRA_PERIPH_ON_APB, tegra_clk_dtv, 0),
816 GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),
817 GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),
818 GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
2dcabf05 819 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IS_CRITICAL),
76ebc134 820 GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
34ac2c27
PDS		 821 GATE("ispa", "isp", 23, 0, tegra_clk_ispa, 0),
822 GATE("ispb", "isp", 3, 0, tegra_clk_ispb, 0),
3b34d821
PDS		 823 GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0),
824 GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
3b34d821 825 GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
dc37fec4
RK		 826 GATE("pllg_ref", "pll_ref", 189, 0, tegra_clk_pll_g_ref, 0),
827 GATE("hsic_trk", "usb2_hsic_trk", 209, TEGRA_PERIPH_NO_RESET, tegra_clk_hsic_trk, 0),
828 GATE("usb2_trk", "usb2_hsic_trk", 210, TEGRA_PERIPH_NO_RESET, tegra_clk_usb2_trk, 0),
829 GATE("xusb_gate", "osc", 143, 0, tegra_clk_xusb_gate, 0),
830 GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0),
831 GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0),
29569941 832 GATE("apb2ape", "clk_m", 107, 0, tegra_clk_apb2ape, 0),
bfa34832 833 GATE("cec", "pclk", 136, 0, tegra_clk_cec, 0),
88da44c5
PDS		 834 GATE("iqc1", "clk_m", 221, 0, tegra_clk_iqc1, 0),
835 GATE("iqc2", "clk_m", 220, 0, tegra_clk_iqc1, 0),
836 GATE("pll_a_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out_adsp, 0),
837 GATE("pll_a_out0_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out0_out_adsp, 0),
838 GATE("adsp", "aclk", 199, 0, tegra_clk_adsp, 0),
839 GATE("adsp_neon", "aclk", 218, 0, tegra_clk_adsp_neon, 0),
dc37fec4
RK		 840};
841
842static struct tegra_periph_init_data div_clks[] = {
843 DIV8("usb2_hsic_trk", "osc", CLK_SOURCE_USB2_HSIC_TRK, tegra_clk_usb2_hsic_trk, 0),
76ebc134
PDS		 844};
845
846struct pll_out_data {
847 char *div_name;
848 char *pll_out_name;
849 u32 offset;
850 int clk_id;
851 u8 div_shift;
852 u8 div_flags;
853 u8 rst_shift;
854 spinlock_t *lock;
855};
856
857#define PLL_OUT(_num, _offset, _div_shift, _div_flags, _rst_shift, _id) \
858 {\
859 .div_name = "pll_p_out" #_num "_div",\
860 .pll_out_name = "pll_p_out" #_num,\
861 .offset = _offset,\
862 .div_shift = _div_shift,\
863 .div_flags = _div_flags | TEGRA_DIVIDER_FIXED |\
864 TEGRA_DIVIDER_ROUND_UP,\
865 .rst_shift = _rst_shift,\
866 .clk_id = tegra_clk_ ## _id,\
867 .lock = &_offset ##_lock,\
868 }
869
870static struct pll_out_data pllp_out_clks[] = {
871 PLL_OUT(1, PLLP_OUTA, 8, 0, 0, pll_p_out1),
872 PLL_OUT(2, PLLP_OUTA, 24, 0, 16, pll_p_out2),
873 PLL_OUT(2, PLLP_OUTA, 24, TEGRA_DIVIDER_INT, 16, pll_p_out2_int),
874 PLL_OUT(3, PLLP_OUTB, 8, 0, 0, pll_p_out3),
875 PLL_OUT(4, PLLP_OUTB, 24, 0, 16, pll_p_out4),
3b34d821 876 PLL_OUT(5, PLLP_OUTC, 24, 0, 16, pll_p_out5),
76ebc134
PDS		 877};
878
879static void __init periph_clk_init(void __iomem *clk_base,
880 struct tegra_clk *tegra_clks)
881{
882 int i;
883 struct clk *clk;
884 struct clk **dt_clk;
885
886 for (i = 0; i < ARRAY_SIZE(periph_clks); i++) {
7e14f223 887 const struct tegra_clk_periph_regs *bank;
76ebc134
PDS		 888 struct tegra_periph_init_data *data;
889
890 data = periph_clks + i;
891
892 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
893 if (!dt_clk)
894 continue;
895
896 bank = get_reg_bank(data->periph.gate.clk_num);
897 if (!bank)
898 continue;
899
900 data->periph.gate.regs = bank;
1d7e2c8e 901 clk = tegra_clk_register_periph_data(clk_base, data);
76ebc134
PDS		 902 *dt_clk = clk;
903 }
904}
905
906static void __init gate_clk_init(void __iomem *clk_base,
907 struct tegra_clk *tegra_clks)
908{
909 int i;
910 struct clk *clk;
911 struct clk **dt_clk;
912
913 for (i = 0; i < ARRAY_SIZE(gate_clks); i++) {
914 struct tegra_periph_init_data *data;
915
916 data = gate_clks + i;
917
918 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
919 if (!dt_clk)
920 continue;
921
922 clk = tegra_clk_register_periph_gate(data->name,
923 data->p.parent_name, data->periph.gate.flags,
924 clk_base, data->flags,
925 data->periph.gate.clk_num,
926 periph_clk_enb_refcnt);
927 *dt_clk = clk;
928 }
929}
930
dc37fec4
RK		 931static void __init div_clk_init(void __iomem *clk_base,
932 struct tegra_clk *tegra_clks)
933{
934 int i;
935 struct clk *clk;
936 struct clk **dt_clk;
937
938 for (i = 0; i < ARRAY_SIZE(div_clks); i++) {
939 struct tegra_periph_init_data *data;
940
941 data = div_clks + i;
942
943 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
944 if (!dt_clk)
945 continue;
946
947 clk = tegra_clk_register_divider(data->name,
948 data->p.parent_name, clk_base + data->offset,
949 data->flags, data->periph.divider.flags,
950 data->periph.divider.shift,
951 data->periph.divider.width,
952 data->periph.divider.frac_width,
953 data->periph.divider.lock);
954 *dt_clk = clk;
955 }
956}
957
76ebc134
PDS		 958static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base,
959 struct tegra_clk *tegra_clks,
960 struct tegra_clk_pll_params *pll_params)
961{
962 struct clk *clk;
963 struct clk **dt_clk;
964 int i;
965
966 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p, tegra_clks);
967 if (dt_clk) {
968 /* PLLP */
969 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base,
970 pmc_base, 0, pll_params, NULL);
971 clk_register_clkdev(clk, "pll_p", NULL);
972 *dt_clk = clk;
973 }
974
975 for (i = 0; i < ARRAY_SIZE(pllp_out_clks); i++) {
976 struct pll_out_data *data;
977
978 data = pllp_out_clks + i;
979
980 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
981 if (!dt_clk)
982 continue;
983
984 clk = tegra_clk_register_divider(data->div_name, "pll_p",
985 clk_base + data->offset, 0, data->div_flags,
986 data->div_shift, 8, 1, data->lock);
987 clk = tegra_clk_register_pll_out(data->pll_out_name,
988 data->div_name, clk_base + data->offset,
989 data->rst_shift + 1, data->rst_shift,
990 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
991 data->lock);
992 *dt_clk = clk;
993 }
dc37fec4
RK		 994
995 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_cpu,
996 tegra_clks);
997 if (dt_clk) {
998 /*
999 * Tegra210 has control on enabling/disabling PLLP branches to
1000 * CPU, register a gate clock "pll_p_out_cpu" for this gating
1001 * function and parent "pll_p_out4" to it, so when we are
1002 * re-parenting CPU off from "pll_p_out4" the PLLP branching to
1003 * CPU can be disabled automatically.
1004 */
1005 clk = tegra_clk_register_divider("pll_p_out4_div",
1006 "pll_p_out_cpu", clk_base + PLLP_OUTB, 0, 0, 24,
1007 8, 1, &PLLP_OUTB_lock);
1008
1009 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out4_cpu, tegra_clks);
1010 if (dt_clk) {
1011 clk = tegra_clk_register_pll_out("pll_p_out4",
1012 "pll_p_out4_div", clk_base + PLLP_OUTB,
1013 17, 16, CLK_IGNORE_UNUSED |
1014 CLK_SET_RATE_PARENT, 0,
1015 &PLLP_OUTB_lock);
1016 *dt_clk = clk;
1017 }
1018 }
1019
1020 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_hsio, tegra_clks);
1021 if (dt_clk) {
1022 /* PLLP_OUT_HSIO */
1023 clk = clk_register_gate(NULL, "pll_p_out_hsio", "pll_p",
1024 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1025 clk_base + PLLP_MISC1, 29, 0, NULL);
1026 *dt_clk = clk;
1027 }
1028
1029 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_xusb, tegra_clks);
1030 if (dt_clk) {
1031 /* PLLP_OUT_XUSB */
1032 clk = clk_register_gate(NULL, "pll_p_out_xusb",
1033 "pll_p_out_hsio", CLK_SET_RATE_PARENT |
1034 CLK_IGNORE_UNUSED, clk_base + PLLP_MISC1, 28, 0,
1035 NULL);
1036 clk_register_clkdev(clk, "pll_p_out_xusb", NULL);
1037 *dt_clk = clk;
1038 }
76ebc134
PDS		 1039}
1040
1041void __init tegra_periph_clk_init(void __iomem *clk_base,
1042 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
1043 struct tegra_clk_pll_params *pll_params)
1044{
1045 init_pllp(clk_base, pmc_base, tegra_clks, pll_params);
1046 periph_clk_init(clk_base, tegra_clks);
1047 gate_clk_init(clk_base, tegra_clks);
dc37fec4 1048 div_clk_init(clk_base, tegra_clks);
76ebc134 1049}
Linux 6.x block layer and io_uring tree(s)