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9952f691 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
8f8f484b PG |
2 | /* |
3 | * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. | |
8f8f484b PG |
4 | */ |
5 | ||
6 | #include <linux/kernel.h> | |
7 | #include <linux/io.h> | |
8 | #include <linux/delay.h> | |
9 | #include <linux/err.h> | |
10 | #include <linux/slab.h> | |
11 | #include <linux/clk-provider.h> | |
8f8f484b PG |
12 | |
13 | #include "clk.h" | |
14 | ||
15 | #define SUPER_STATE_IDLE 0 | |
16 | #define SUPER_STATE_RUN 1 | |
17 | #define SUPER_STATE_IRQ 2 | |
18 | #define SUPER_STATE_FIQ 3 | |
19 | ||
20 | #define SUPER_STATE_SHIFT 28 | |
21 | #define SUPER_STATE_MASK ((BIT(SUPER_STATE_IDLE) | BIT(SUPER_STATE_RUN) | \ | |
22 | BIT(SUPER_STATE_IRQ) | BIT(SUPER_STATE_FIQ)) \ | |
23 | << SUPER_STATE_SHIFT) | |
24 | ||
25 | #define SUPER_LP_DIV2_BYPASS (1 << 16) | |
26 | ||
27 | #define super_state(s) (BIT(s) << SUPER_STATE_SHIFT) | |
28 | #define super_state_to_src_shift(m, s) ((m->width * s)) | |
29 | #define super_state_to_src_mask(m) (((1 << m->width) - 1)) | |
30 | ||
68a14a56 SK |
31 | #define CCLK_SRC_PLLP_OUT0 4 |
32 | #define CCLK_SRC_PLLP_OUT4 5 | |
33 | ||
8f8f484b PG |
34 | static u8 clk_super_get_parent(struct clk_hw *hw) |
35 | { | |
36 | struct tegra_clk_super_mux *mux = to_clk_super_mux(hw); | |
37 | u32 val, state; | |
38 | u8 source, shift; | |
39 | ||
40 | val = readl_relaxed(mux->reg); | |
41 | ||
42 | state = val & SUPER_STATE_MASK; | |
43 | ||
44 | BUG_ON((state != super_state(SUPER_STATE_RUN)) && | |
45 | (state != super_state(SUPER_STATE_IDLE))); | |
46 | shift = (state == super_state(SUPER_STATE_IDLE)) ? | |
47 | super_state_to_src_shift(mux, SUPER_STATE_IDLE) : | |
48 | super_state_to_src_shift(mux, SUPER_STATE_RUN); | |
49 | ||
50 | source = (val >> shift) & super_state_to_src_mask(mux); | |
51 | ||
52 | /* | |
53 | * If LP_DIV2_BYPASS is not set and PLLX is current parent then | |
54 | * PLLX/2 is the input source to CCLKLP. | |
55 | */ | |
56 | if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) && | |
57 | (source == mux->pllx_index)) | |
58 | source = mux->div2_index; | |
59 | ||
60 | return source; | |
61 | } | |
62 | ||
63 | static int clk_super_set_parent(struct clk_hw *hw, u8 index) | |
64 | { | |
65 | struct tegra_clk_super_mux *mux = to_clk_super_mux(hw); | |
66 | u32 val, state; | |
c64c65d4 | 67 | int err = 0; |
8f8f484b | 68 | u8 parent_index, shift; |
c64c65d4 PDS |
69 | unsigned long flags = 0; |
70 | ||
71 | if (mux->lock) | |
72 | spin_lock_irqsave(mux->lock, flags); | |
8f8f484b PG |
73 | |
74 | val = readl_relaxed(mux->reg); | |
75 | state = val & SUPER_STATE_MASK; | |
76 | BUG_ON((state != super_state(SUPER_STATE_RUN)) && | |
77 | (state != super_state(SUPER_STATE_IDLE))); | |
78 | shift = (state == super_state(SUPER_STATE_IDLE)) ? | |
79 | super_state_to_src_shift(mux, SUPER_STATE_IDLE) : | |
80 | super_state_to_src_shift(mux, SUPER_STATE_RUN); | |
81 | ||
82 | /* | |
83 | * For LP mode super-clock switch between PLLX direct | |
84 | * and divided-by-2 outputs is allowed only when other | |
85 | * than PLLX clock source is current parent. | |
86 | */ | |
87 | if ((mux->flags & TEGRA_DIVIDER_2) && ((index == mux->div2_index) || | |
88 | (index == mux->pllx_index))) { | |
89 | parent_index = clk_super_get_parent(hw); | |
90 | if ((parent_index == mux->div2_index) || | |
c64c65d4 PDS |
91 | (parent_index == mux->pllx_index)) { |
92 | err = -EINVAL; | |
93 | goto out; | |
94 | } | |
8f8f484b PG |
95 | |
96 | val ^= SUPER_LP_DIV2_BYPASS; | |
97 | writel_relaxed(val, mux->reg); | |
98 | udelay(2); | |
99 | ||
100 | if (index == mux->div2_index) | |
101 | index = mux->pllx_index; | |
102 | } | |
68a14a56 SK |
103 | |
104 | /* enable PLLP branches to CPU before selecting PLLP source */ | |
105 | if ((mux->flags & TEGRA210_CPU_CLK) && | |
106 | (index == CCLK_SRC_PLLP_OUT0 || index == CCLK_SRC_PLLP_OUT4)) | |
107 | tegra_clk_set_pllp_out_cpu(true); | |
108 | ||
8f8f484b PG |
109 | val &= ~((super_state_to_src_mask(mux)) << shift); |
110 | val |= (index & (super_state_to_src_mask(mux))) << shift; | |
111 | ||
112 | writel_relaxed(val, mux->reg); | |
113 | udelay(2); | |
c64c65d4 | 114 | |
68a14a56 SK |
115 | /* disable PLLP branches to CPU if not used */ |
116 | if ((mux->flags & TEGRA210_CPU_CLK) && | |
117 | index != CCLK_SRC_PLLP_OUT0 && index != CCLK_SRC_PLLP_OUT4) | |
118 | tegra_clk_set_pllp_out_cpu(false); | |
119 | ||
c64c65d4 PDS |
120 | out: |
121 | if (mux->lock) | |
122 | spin_unlock_irqrestore(mux->lock, flags); | |
123 | ||
124 | return err; | |
8f8f484b PG |
125 | } |
126 | ||
b331db55 | 127 | static const struct clk_ops tegra_clk_super_mux_ops = { |
e827ba18 PDS |
128 | .get_parent = clk_super_get_parent, |
129 | .set_parent = clk_super_set_parent, | |
130 | }; | |
131 | ||
132 | static long clk_super_round_rate(struct clk_hw *hw, unsigned long rate, | |
133 | unsigned long *parent_rate) | |
134 | { | |
135 | struct tegra_clk_super_mux *super = to_clk_super_mux(hw); | |
136 | struct clk_hw *div_hw = &super->frac_div.hw; | |
137 | ||
138 | __clk_hw_set_clk(div_hw, hw); | |
139 | ||
140 | return super->div_ops->round_rate(div_hw, rate, parent_rate); | |
141 | } | |
142 | ||
143 | static unsigned long clk_super_recalc_rate(struct clk_hw *hw, | |
144 | unsigned long parent_rate) | |
145 | { | |
146 | struct tegra_clk_super_mux *super = to_clk_super_mux(hw); | |
147 | struct clk_hw *div_hw = &super->frac_div.hw; | |
148 | ||
149 | __clk_hw_set_clk(div_hw, hw); | |
150 | ||
151 | return super->div_ops->recalc_rate(div_hw, parent_rate); | |
152 | } | |
153 | ||
154 | static int clk_super_set_rate(struct clk_hw *hw, unsigned long rate, | |
155 | unsigned long parent_rate) | |
156 | { | |
157 | struct tegra_clk_super_mux *super = to_clk_super_mux(hw); | |
158 | struct clk_hw *div_hw = &super->frac_div.hw; | |
159 | ||
160 | __clk_hw_set_clk(div_hw, hw); | |
161 | ||
162 | return super->div_ops->set_rate(div_hw, rate, parent_rate); | |
163 | } | |
164 | ||
8f8f484b PG |
165 | const struct clk_ops tegra_clk_super_ops = { |
166 | .get_parent = clk_super_get_parent, | |
167 | .set_parent = clk_super_set_parent, | |
e827ba18 PDS |
168 | .set_rate = clk_super_set_rate, |
169 | .round_rate = clk_super_round_rate, | |
170 | .recalc_rate = clk_super_recalc_rate, | |
8f8f484b PG |
171 | }; |
172 | ||
173 | struct clk *tegra_clk_register_super_mux(const char *name, | |
174 | const char **parent_names, u8 num_parents, | |
175 | unsigned long flags, void __iomem *reg, u8 clk_super_flags, | |
176 | u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock) | |
177 | { | |
178 | struct tegra_clk_super_mux *super; | |
179 | struct clk *clk; | |
180 | struct clk_init_data init; | |
181 | ||
182 | super = kzalloc(sizeof(*super), GFP_KERNEL); | |
e827ba18 | 183 | if (!super) |
8f8f484b | 184 | return ERR_PTR(-ENOMEM); |
8f8f484b PG |
185 | |
186 | init.name = name; | |
e827ba18 | 187 | init.ops = &tegra_clk_super_mux_ops; |
8f8f484b PG |
188 | init.flags = flags; |
189 | init.parent_names = parent_names; | |
190 | init.num_parents = num_parents; | |
191 | ||
192 | super->reg = reg; | |
193 | super->pllx_index = pllx_index; | |
194 | super->div2_index = div2_index; | |
195 | super->lock = lock; | |
196 | super->width = width; | |
197 | super->flags = clk_super_flags; | |
198 | ||
199 | /* Data in .init is copied by clk_register(), so stack variable OK */ | |
200 | super->hw.init = &init; | |
201 | ||
202 | clk = clk_register(NULL, &super->hw); | |
203 | if (IS_ERR(clk)) | |
204 | kfree(super); | |
205 | ||
206 | return clk; | |
207 | } | |
e827ba18 PDS |
208 | |
209 | struct clk *tegra_clk_register_super_clk(const char *name, | |
210 | const char * const *parent_names, u8 num_parents, | |
211 | unsigned long flags, void __iomem *reg, u8 clk_super_flags, | |
212 | spinlock_t *lock) | |
213 | { | |
214 | struct tegra_clk_super_mux *super; | |
215 | struct clk *clk; | |
216 | struct clk_init_data init; | |
217 | ||
218 | super = kzalloc(sizeof(*super), GFP_KERNEL); | |
219 | if (!super) | |
220 | return ERR_PTR(-ENOMEM); | |
221 | ||
222 | init.name = name; | |
223 | init.ops = &tegra_clk_super_ops; | |
224 | init.flags = flags; | |
225 | init.parent_names = parent_names; | |
226 | init.num_parents = num_parents; | |
227 | ||
228 | super->reg = reg; | |
229 | super->lock = lock; | |
230 | super->width = 4; | |
231 | super->flags = clk_super_flags; | |
232 | super->frac_div.reg = reg + 4; | |
233 | super->frac_div.shift = 16; | |
234 | super->frac_div.width = 8; | |
235 | super->frac_div.frac_width = 1; | |
236 | super->frac_div.lock = lock; | |
237 | super->div_ops = &tegra_clk_frac_div_ops; | |
238 | ||
239 | /* Data in .init is copied by clk_register(), so stack variable OK */ | |
240 | super->hw.init = &init; | |
241 | ||
242 | clk = clk_register(NULL, &super->hw); | |
243 | if (IS_ERR(clk)) | |
244 | kfree(super); | |
245 | ||
246 | return clk; | |
247 | } |