[linux-block.git] / drivers / clk / tegra / clk-super.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
 */

#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/clk-provider.h>

#include "clk.h"

#define SUPER_STATE_IDLE 0
#define SUPER_STATE_RUN 1
#define SUPER_STATE_IRQ 2
#define SUPER_STATE_FIQ 3

#define SUPER_STATE_SHIFT 28
#define SUPER_STATE_MASK ((BIT(SUPER_STATE_IDLE) | BIT(SUPER_STATE_RUN) | \
			   BIT(SUPER_STATE_IRQ) | BIT(SUPER_STATE_FIQ))	\
			  << SUPER_STATE_SHIFT)

#define SUPER_LP_DIV2_BYPASS (1 << 16)

#define super_state(s) (BIT(s) << SUPER_STATE_SHIFT)
#define super_state_to_src_shift(m, s) ((m->width * s))
#define super_state_to_src_mask(m) (((1 << m->width) - 1))

#define CCLK_SRC_PLLP_OUT0 4
#define CCLK_SRC_PLLP_OUT4 5

static u8 clk_super_get_parent(struct clk_hw *hw)
{
	struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
	u32 val, state;
	u8 source, shift;

	val = readl_relaxed(mux->reg);

	state = val & SUPER_STATE_MASK;

	BUG_ON((state != super_state(SUPER_STATE_RUN)) &&
	       (state != super_state(SUPER_STATE_IDLE)));
	shift = (state == super_state(SUPER_STATE_IDLE)) ?
		super_state_to_src_shift(mux, SUPER_STATE_IDLE) :
		super_state_to_src_shift(mux, SUPER_STATE_RUN);

	source = (val >> shift) & super_state_to_src_mask(mux);

	/*
	 * If LP_DIV2_BYPASS is not set and PLLX is current parent then
	 * PLLX/2 is the input source to CCLKLP.
	 */
	if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) &&
	    (source == mux->pllx_index))
		source = mux->div2_index;

	return source;
}

static int clk_super_set_parent(struct clk_hw *hw, u8 index)
{
	struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
	u32 val, state;
	int err = 0;
	u8 parent_index, shift;
	unsigned long flags = 0;

	if (mux->lock)
		spin_lock_irqsave(mux->lock, flags);

	val = readl_relaxed(mux->reg);
	state = val & SUPER_STATE_MASK;
	BUG_ON((state != super_state(SUPER_STATE_RUN)) &&
	       (state != super_state(SUPER_STATE_IDLE)));
	shift = (state == super_state(SUPER_STATE_IDLE)) ?
		super_state_to_src_shift(mux, SUPER_STATE_IDLE) :
		super_state_to_src_shift(mux, SUPER_STATE_RUN);

	/*
	 * For LP mode super-clock switch between PLLX direct
	 * and divided-by-2 outputs is allowed only when other
	 * than PLLX clock source is current parent.
	 */
	if ((mux->flags & TEGRA_DIVIDER_2) && ((index == mux->div2_index) ||
					       (index == mux->pllx_index))) {
		parent_index = clk_super_get_parent(hw);
		if ((parent_index == mux->div2_index) ||
		    (parent_index == mux->pllx_index)) {
			err = -EINVAL;
			goto out;
		}

		val ^= SUPER_LP_DIV2_BYPASS;
		writel_relaxed(val, mux->reg);
		udelay(2);

		if (index == mux->div2_index)
			index = mux->pllx_index;
	}

	/* enable PLLP branches to CPU before selecting PLLP source */
	if ((mux->flags & TEGRA210_CPU_CLK) &&
	    (index == CCLK_SRC_PLLP_OUT0 || index == CCLK_SRC_PLLP_OUT4))
		tegra_clk_set_pllp_out_cpu(true);

	val &= ~((super_state_to_src_mask(mux)) << shift);
	val |= (index & (super_state_to_src_mask(mux))) << shift;

	writel_relaxed(val, mux->reg);
	udelay(2);

	/* disable PLLP branches to CPU if not used */
	if ((mux->flags & TEGRA210_CPU_CLK) &&
	    index != CCLK_SRC_PLLP_OUT0 && index != CCLK_SRC_PLLP_OUT4)
		tegra_clk_set_pllp_out_cpu(false);

out:
	if (mux->lock)
		spin_unlock_irqrestore(mux->lock, flags);

	return err;
}

static void clk_super_mux_restore_context(struct clk_hw *hw)
{
	int parent_id;

	parent_id = clk_hw_get_parent_index(hw);
	if (WARN_ON(parent_id < 0))
		return;

	clk_super_set_parent(hw, parent_id);
}

static const struct clk_ops tegra_clk_super_mux_ops = {
	.determine_rate = clk_hw_determine_rate_no_reparent,
	.get_parent = clk_super_get_parent,
	.set_parent = clk_super_set_parent,
	.restore_context = clk_super_mux_restore_context,
};

static long clk_super_round_rate(struct clk_hw *hw, unsigned long rate,
				 unsigned long *parent_rate)
{
	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
	struct clk_hw *div_hw = &super->frac_div.hw;

	__clk_hw_set_clk(div_hw, hw);

	return super->div_ops->round_rate(div_hw, rate, parent_rate);
}

static unsigned long clk_super_recalc_rate(struct clk_hw *hw,
					   unsigned long parent_rate)
{
	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
	struct clk_hw *div_hw = &super->frac_div.hw;

	__clk_hw_set_clk(div_hw, hw);

	return super->div_ops->recalc_rate(div_hw, parent_rate);
}

static int clk_super_set_rate(struct clk_hw *hw, unsigned long rate,
			      unsigned long parent_rate)
{
	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
	struct clk_hw *div_hw = &super->frac_div.hw;

	__clk_hw_set_clk(div_hw, hw);

	return super->div_ops->set_rate(div_hw, rate, parent_rate);
}

static void clk_super_restore_context(struct clk_hw *hw)
{
	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
	struct clk_hw *div_hw = &super->frac_div.hw;
	int parent_id;

	parent_id = clk_hw_get_parent_index(hw);
	if (WARN_ON(parent_id < 0))
		return;

	super->div_ops->restore_context(div_hw);
	clk_super_set_parent(hw, parent_id);
}

const struct clk_ops tegra_clk_super_ops = {
	.get_parent = clk_super_get_parent,
	.set_parent = clk_super_set_parent,
	.set_rate = clk_super_set_rate,
	.round_rate = clk_super_round_rate,
	.recalc_rate = clk_super_recalc_rate,
	.restore_context = clk_super_restore_context,
};

struct clk *tegra_clk_register_super_mux(const char *name,
		const char **parent_names, u8 num_parents,
		unsigned long flags, void __iomem *reg, u8 clk_super_flags,
		u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock)
{
	struct tegra_clk_super_mux *super;
	struct clk *clk;
	struct clk_init_data init;

	super = kzalloc(sizeof(*super), GFP_KERNEL);
	if (!super)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &tegra_clk_super_mux_ops;
	init.flags = flags;
	init.parent_names = parent_names;
	init.num_parents = num_parents;

	super->reg = reg;
	super->pllx_index = pllx_index;
	super->div2_index = div2_index;
	super->lock = lock;
	super->width = width;
	super->flags = clk_super_flags;

	/* Data in .init is copied by clk_register(), so stack variable OK */
	super->hw.init = &init;

	clk = tegra_clk_dev_register(&super->hw);
	if (IS_ERR(clk))
		kfree(super);

	return clk;
}

struct clk *tegra_clk_register_super_clk(const char *name,
		const char * const *parent_names, u8 num_parents,
		unsigned long flags, void __iomem *reg, u8 clk_super_flags,
		spinlock_t *lock)
{
	struct tegra_clk_super_mux *super;
	struct clk *clk;
	struct clk_init_data init;

	super = kzalloc(sizeof(*super), GFP_KERNEL);
	if (!super)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &tegra_clk_super_ops;
	init.flags = flags;
	init.parent_names = parent_names;
	init.num_parents = num_parents;

	super->reg = reg;
	super->lock = lock;
	super->width = 4;
	super->flags = clk_super_flags;
	super->frac_div.reg = reg + 4;
	super->frac_div.shift = 16;
	super->frac_div.width = 8;
	super->frac_div.frac_width = 1;
	super->frac_div.lock = lock;
	super->div_ops = &tegra_clk_frac_div_ops;

	/* Data in .init is copied by clk_register(), so stack variable OK */
	super->hw.init = &init;

	clk = clk_register(NULL, &super->hw);
	if (IS_ERR(clk))
		kfree(super);

	return clk;
}
Commit	Line	Data
9952f691	1	// SPDX-License-Identifier: GPL-2.0-only
8f8f484b PG	2	/*
8f8f484b PG	3	* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
8f8f484b PG	4	*/
	5
	6	#include <linux/kernel.h>
	7	#include <linux/io.h>
	8	#include <linux/delay.h>
	9	#include <linux/err.h>
	10	#include <linux/slab.h>
	11	#include <linux/clk-provider.h>
8f8f484b PG	12
	13	#include "clk.h"
	14
	15	#define SUPER_STATE_IDLE 0
	16	#define SUPER_STATE_RUN 1
	17	#define SUPER_STATE_IRQ 2
	18	#define SUPER_STATE_FIQ 3
	19
	20	#define SUPER_STATE_SHIFT 28
	21	#define SUPER_STATE_MASK ((BIT(SUPER_STATE_IDLE) \| BIT(SUPER_STATE_RUN) \| \
	22	BIT(SUPER_STATE_IRQ) \| BIT(SUPER_STATE_FIQ)) \
	23	<< SUPER_STATE_SHIFT)
	24
	25	#define SUPER_LP_DIV2_BYPASS (1 << 16)
	26
	27	#define super_state(s) (BIT(s) << SUPER_STATE_SHIFT)
	28	#define super_state_to_src_shift(m, s) ((m->width * s))
	29	#define super_state_to_src_mask(m) (((1 << m->width) - 1))
	30
68a14a56 SK	31	#define CCLK_SRC_PLLP_OUT0 4
	32	#define CCLK_SRC_PLLP_OUT4 5
	33
8f8f484b PG	34	static u8 clk_super_get_parent(struct clk_hw *hw)
	35	{
	36	struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
	37	u32 val, state;
	38	u8 source, shift;
	39
	40	val = readl_relaxed(mux->reg);
	41
	42	state = val & SUPER_STATE_MASK;
	43
	44	BUG_ON((state != super_state(SUPER_STATE_RUN)) &&
	45	(state != super_state(SUPER_STATE_IDLE)));
	46	shift = (state == super_state(SUPER_STATE_IDLE)) ?
	47	super_state_to_src_shift(mux, SUPER_STATE_IDLE) :
	48	super_state_to_src_shift(mux, SUPER_STATE_RUN);
	49
	50	source = (val >> shift) & super_state_to_src_mask(mux);
	51
	52	/*
	53	* If LP_DIV2_BYPASS is not set and PLLX is current parent then
	54	* PLLX/2 is the input source to CCLKLP.
	55	*/
	56	if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) &&
	57	(source == mux->pllx_index))
	58	source = mux->div2_index;
	59
	60	return source;
	61	}
	62
	63	static int clk_super_set_parent(struct clk_hw *hw, u8 index)
	64	{
	65	struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
	66	u32 val, state;
c64c65d4	67	int err = 0;
8f8f484b	68	u8 parent_index, shift;
c64c65d4 PDS	69	unsigned long flags = 0;
	70
	71	if (mux->lock)
	72	spin_lock_irqsave(mux->lock, flags);
8f8f484b PG	73
	74	val = readl_relaxed(mux->reg);
	75	state = val & SUPER_STATE_MASK;
	76	BUG_ON((state != super_state(SUPER_STATE_RUN)) &&
	77	(state != super_state(SUPER_STATE_IDLE)));
	78	shift = (state == super_state(SUPER_STATE_IDLE)) ?
	79	super_state_to_src_shift(mux, SUPER_STATE_IDLE) :
	80	super_state_to_src_shift(mux, SUPER_STATE_RUN);
	81
	82	/*
	83	* For LP mode super-clock switch between PLLX direct
	84	* and divided-by-2 outputs is allowed only when other
	85	* than PLLX clock source is current parent.
	86	*/
	87	if ((mux->flags & TEGRA_DIVIDER_2) && ((index == mux->div2_index) \|\|
	88	(index == mux->pllx_index))) {
	89	parent_index = clk_super_get_parent(hw);
	90	if ((parent_index == mux->div2_index) \|\|
c64c65d4 PDS	91	(parent_index == mux->pllx_index)) {
	92	err = -EINVAL;
	93	goto out;
	94	}
8f8f484b PG	95
	96	val ^= SUPER_LP_DIV2_BYPASS;
	97	writel_relaxed(val, mux->reg);
	98	udelay(2);
	99
	100	if (index == mux->div2_index)
	101	index = mux->pllx_index;
	102	}
68a14a56 SK	103
	104	/* enable PLLP branches to CPU before selecting PLLP source */
	105	if ((mux->flags & TEGRA210_CPU_CLK) &&
	106	(index == CCLK_SRC_PLLP_OUT0 \|\| index == CCLK_SRC_PLLP_OUT4))
	107	tegra_clk_set_pllp_out_cpu(true);
	108
8f8f484b PG	109	val &= ~((super_state_to_src_mask(mux)) << shift);
	110	val \|= (index & (super_state_to_src_mask(mux))) << shift;
	111
	112	writel_relaxed(val, mux->reg);
	113	udelay(2);
c64c65d4	114
68a14a56 SK	115	/* disable PLLP branches to CPU if not used */
	116	if ((mux->flags & TEGRA210_CPU_CLK) &&
	117	index != CCLK_SRC_PLLP_OUT0 && index != CCLK_SRC_PLLP_OUT4)
	118	tegra_clk_set_pllp_out_cpu(false);
	119
c64c65d4 PDS	120	out:
	121	if (mux->lock)
	122	spin_unlock_irqrestore(mux->lock, flags);
	123
	124	return err;
8f8f484b PG	125	}
8f8f484b PG	126
f8fd9752 SK	127	static void clk_super_mux_restore_context(struct clk_hw *hw)
	128	{
	129	int parent_id;
	130
	131	parent_id = clk_hw_get_parent_index(hw);
	132	if (WARN_ON(parent_id < 0))
	133	return;
	134
	135	clk_super_set_parent(hw, parent_id);
	136	}
	137
b331db55	138	static const struct clk_ops tegra_clk_super_mux_ops = {
78b435c8	139	.determine_rate = clk_hw_determine_rate_no_reparent,
e827ba18 PDS	140	.get_parent = clk_super_get_parent,
e827ba18 PDS	141	.set_parent = clk_super_set_parent,
f8fd9752	142	.restore_context = clk_super_mux_restore_context,
e827ba18 PDS	143	};
	144
	145	static long clk_super_round_rate(struct clk_hw *hw, unsigned long rate,
	146	unsigned long *parent_rate)
	147	{
	148	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
	149	struct clk_hw *div_hw = &super->frac_div.hw;
	150
	151	__clk_hw_set_clk(div_hw, hw);
	152
	153	return super->div_ops->round_rate(div_hw, rate, parent_rate);
	154	}
	155
	156	static unsigned long clk_super_recalc_rate(struct clk_hw *hw,
	157	unsigned long parent_rate)
	158	{
	159	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
	160	struct clk_hw *div_hw = &super->frac_div.hw;
	161
	162	__clk_hw_set_clk(div_hw, hw);
	163
	164	return super->div_ops->recalc_rate(div_hw, parent_rate);
	165	}
	166
	167	static int clk_super_set_rate(struct clk_hw *hw, unsigned long rate,
	168	unsigned long parent_rate)
	169	{
	170	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
	171	struct clk_hw *div_hw = &super->frac_div.hw;
	172
	173	__clk_hw_set_clk(div_hw, hw);
	174
	175	return super->div_ops->set_rate(div_hw, rate, parent_rate);
	176	}
	177
f8fd9752 SK	178	static void clk_super_restore_context(struct clk_hw *hw)
	179	{
	180	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
	181	struct clk_hw *div_hw = &super->frac_div.hw;
	182	int parent_id;
	183
	184	parent_id = clk_hw_get_parent_index(hw);
	185	if (WARN_ON(parent_id < 0))
	186	return;
	187
	188	super->div_ops->restore_context(div_hw);
	189	clk_super_set_parent(hw, parent_id);
	190	}
	191
8f8f484b PG	192	const struct clk_ops tegra_clk_super_ops = {
	193	.get_parent = clk_super_get_parent,
	194	.set_parent = clk_super_set_parent,
e827ba18 PDS	195	.set_rate = clk_super_set_rate,
	196	.round_rate = clk_super_round_rate,
	197	.recalc_rate = clk_super_recalc_rate,
f8fd9752	198	.restore_context = clk_super_restore_context,
8f8f484b PG	199	};
	200
	201	struct clk tegra_clk_register_super_mux(const char name,
	202	const char **parent_names, u8 num_parents,
	203	unsigned long flags, void __iomem *reg, u8 clk_super_flags,
	204	u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock)
	205	{
	206	struct tegra_clk_super_mux *super;
	207	struct clk *clk;
	208	struct clk_init_data init;
	209
	210	super = kzalloc(sizeof(*super), GFP_KERNEL);
e827ba18	211	if (!super)
8f8f484b	212	return ERR_PTR(-ENOMEM);
8f8f484b PG	213
8f8f484b PG	214	init.name = name;
e827ba18	215	init.ops = &tegra_clk_super_mux_ops;
8f8f484b PG	216	init.flags = flags;
	217	init.parent_names = parent_names;
	218	init.num_parents = num_parents;
	219
	220	super->reg = reg;
	221	super->pllx_index = pllx_index;
	222	super->div2_index = div2_index;
	223	super->lock = lock;
	224	super->width = width;
	225	super->flags = clk_super_flags;
	226
	227	/* Data in .init is copied by clk_register(), so stack variable OK */
	228	super->hw.init = &init;
	229
b1bc04a2	230	clk = tegra_clk_dev_register(&super->hw);
8f8f484b PG	231	if (IS_ERR(clk))
	232	kfree(super);
	233
	234	return clk;
	235	}
e827ba18 PDS	236
	237	struct clk tegra_clk_register_super_clk(const char name,
	238	const char * const *parent_names, u8 num_parents,
	239	unsigned long flags, void __iomem *reg, u8 clk_super_flags,
	240	spinlock_t *lock)
	241	{
	242	struct tegra_clk_super_mux *super;
	243	struct clk *clk;
	244	struct clk_init_data init;
	245
	246	super = kzalloc(sizeof(*super), GFP_KERNEL);
	247	if (!super)
	248	return ERR_PTR(-ENOMEM);
	249
	250	init.name = name;
	251	init.ops = &tegra_clk_super_ops;
	252	init.flags = flags;
	253	init.parent_names = parent_names;
	254	init.num_parents = num_parents;
	255
	256	super->reg = reg;
	257	super->lock = lock;
	258	super->width = 4;
	259	super->flags = clk_super_flags;
	260	super->frac_div.reg = reg + 4;
	261	super->frac_div.shift = 16;
	262	super->frac_div.width = 8;
	263	super->frac_div.frac_width = 1;
	264	super->frac_div.lock = lock;
	265	super->div_ops = &tegra_clk_frac_div_ops;
	266
	267	/* Data in .init is copied by clk_register(), so stack variable OK */
	268	super->hw.init = &init;
	269
	270	clk = clk_register(NULL, &super->hw);
	271	if (IS_ERR(clk))
	272	kfree(super);
	273
	274	return clk;
	275	}