[linux-2.6-block.git] / drivers / clk / tegra / clk-dfll.h

/*
 * clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver
 * Copyright (C) 2013 NVIDIA Corporation.  All rights reserved.
 *
 * Aleksandr Frid <afrid@nvidia.com>
 * Paul Walmsley <pwalmsley@nvidia.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef __DRIVERS_CLK_TEGRA_CLK_DFLL_H
#define __DRIVERS_CLK_TEGRA_CLK_DFLL_H

#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/types.h>

/**
 * struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver
 * @dev: struct device * that holds the OPP table for the DFLL
 * @max_freq: maximum frequency supported on this SoC
 * @cvb: CPU frequency table for this SoC
 * @init_clock_trimmers: callback to initialize clock trimmers
 * @set_clock_trimmers_high: callback to tune clock trimmers for high voltage
 * @set_clock_trimmers_low: callback to tune clock trimmers for low voltage
 */
struct tegra_dfll_soc_data {
	struct device *dev;
	unsigned long max_freq;
	const struct cvb_table *cvb;

	void (*init_clock_trimmers)(void);
	void (*set_clock_trimmers_high)(void);
	void (*set_clock_trimmers_low)(void);
};

int tegra_dfll_register(struct platform_device *pdev,
			struct tegra_dfll_soc_data *soc);
int tegra_dfll_unregister(struct platform_device *pdev);
int tegra_dfll_runtime_suspend(struct device *dev);
int tegra_dfll_runtime_resume(struct device *dev);

#endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */
Commit	Line	Data
d8d7a08f TT	1	/*
	2	* clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver
	3	* Copyright (C) 2013 NVIDIA Corporation. All rights reserved.
	4	*
	5	* Aleksandr Frid <afrid@nvidia.com>
	6	* Paul Walmsley <pwalmsley@nvidia.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*/
	17
	18	#ifndef __DRIVERS_CLK_TEGRA_CLK_DFLL_H
	19	#define __DRIVERS_CLK_TEGRA_CLK_DFLL_H
	20
	21	#include <linux/platform_device.h>
	22	#include <linux/reset.h>
	23	#include <linux/types.h>
	24
	25	/**
	26	* struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver
8eaaae99	27	* @dev: struct device * that holds the OPP table for the DFLL
f7c42d98	28	* @max_freq: maximum frequency supported on this SoC
27ed2f7e	29	* @cvb: CPU frequency table for this SoC
8eaaae99 TR	30	* @init_clock_trimmers: callback to initialize clock trimmers
	31	* @set_clock_trimmers_high: callback to tune clock trimmers for high voltage
	32	* @set_clock_trimmers_low: callback to tune clock trimmers for low voltage
d8d7a08f TT	33	*/
d8d7a08f TT	34	struct tegra_dfll_soc_data {
62a8a094	35	struct device *dev;
f7c42d98	36	unsigned long max_freq;
27ed2f7e	37	const struct cvb_table *cvb;
8eaaae99	38
d8d7a08f TT	39	void (*init_clock_trimmers)(void);
	40	void (*set_clock_trimmers_high)(void);
	41	void (*set_clock_trimmers_low)(void);
	42	};
	43
	44	int tegra_dfll_register(struct platform_device *pdev,
	45	struct tegra_dfll_soc_data *soc);
	46	int tegra_dfll_unregister(struct platform_device *pdev);
	47	int tegra_dfll_runtime_suspend(struct device *dev);
	48	int tegra_dfll_runtime_resume(struct device *dev);
	49
	50	#endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */