[linux-block.git] / drivers / clk / sunxi-ng / ccu_common.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
 */

#ifndef _COMMON_H_
#define _COMMON_H_

#include <linux/compiler.h>
#include <linux/clk-provider.h>

#define CCU_FEATURE_FRACTIONAL		BIT(0)
#define CCU_FEATURE_VARIABLE_PREDIV	BIT(1)
#define CCU_FEATURE_FIXED_PREDIV	BIT(2)
#define CCU_FEATURE_FIXED_POSTDIV	BIT(3)
#define CCU_FEATURE_ALL_PREDIV		BIT(4)
#define CCU_FEATURE_LOCK_REG		BIT(5)
#define CCU_FEATURE_MMC_TIMING_SWITCH	BIT(6)
#define CCU_FEATURE_SIGMA_DELTA_MOD	BIT(7)
#define CCU_FEATURE_KEY_FIELD		BIT(8)

/* MMC timing mode switch bit */
#define CCU_MMC_NEW_TIMING_MODE		BIT(30)

struct device_node;

struct ccu_common {
	void __iomem	*base;
	u16		reg;
	u16		lock_reg;
	u32		prediv;

	unsigned long	features;
	spinlock_t	*lock;
	struct clk_hw	hw;
};

static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw)
{
	return container_of(hw, struct ccu_common, hw);
}

struct sunxi_ccu_desc {
	struct ccu_common		**ccu_clks;
	unsigned long			num_ccu_clks;

	struct clk_hw_onecell_data	*hw_clks;

	struct ccu_reset_map		*resets;
	unsigned long			num_resets;
};

void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock);

struct ccu_pll_nb {
	struct notifier_block	clk_nb;
	struct ccu_common	*common;

	u32	enable;
	u32	lock;
};

#define to_ccu_pll_nb(_nb) container_of(_nb, struct ccu_pll_nb, clk_nb)

int ccu_pll_notifier_register(struct ccu_pll_nb *pll_nb);

int devm_sunxi_ccu_probe(struct device *dev, void __iomem *reg,
			 const struct sunxi_ccu_desc *desc);
void of_sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
			const struct sunxi_ccu_desc *desc);

#endif /* _COMMON_H_ */
Commit	Line	Data
9c92ab61	1	/* SPDX-License-Identifier: GPL-2.0-only */
1d80c142 MR	2	/*
1d80c142 MR	3	* Copyright (c) 2016 Maxime Ripard. All rights reserved.
1d80c142 MR	4	*/
	5
	6	#ifndef _COMMON_H_
	7	#define _COMMON_H_
	8
	9	#include <linux/compiler.h>
	10	#include <linux/clk-provider.h>
	11
	12	#define CCU_FEATURE_FRACTIONAL BIT(0)
	13	#define CCU_FEATURE_VARIABLE_PREDIV BIT(1)
	14	#define CCU_FEATURE_FIXED_PREDIV BIT(2)
	15	#define CCU_FEATURE_FIXED_POSTDIV BIT(3)
7c09b858	16	#define CCU_FEATURE_ALL_PREDIV BIT(4)
3de64bf1	17	#define CCU_FEATURE_LOCK_REG BIT(5)
f6f64ed8	18	#define CCU_FEATURE_MMC_TIMING_SWITCH BIT(6)
05d2eaac	19	#define CCU_FEATURE_SIGMA_DELTA_MOD BIT(7)
7fc46339	20	#define CCU_FEATURE_KEY_FIELD BIT(8)
f6f64ed8 CYT	21
	22	/* MMC timing mode switch bit */
	23	#define CCU_MMC_NEW_TIMING_MODE BIT(30)
1d80c142 MR	24
	25	struct device_node;
	26
1d80c142 MR	27	struct ccu_common {
	28	void __iomem *base;
	29	u16 reg;
3de64bf1	30	u16 lock_reg;
7c09b858	31	u32 prediv;
1d80c142 MR	32
	33	unsigned long features;
	34	spinlock_t *lock;
	35	struct clk_hw hw;
	36	};
	37
	38	static inline struct ccu_common hw_to_ccu_common(struct clk_hw hw)
	39	{
	40	return container_of(hw, struct ccu_common, hw);
	41	}
	42
	43	struct sunxi_ccu_desc {
	44	struct ccu_common **ccu_clks;
	45	unsigned long num_ccu_clks;
	46
	47	struct clk_hw_onecell_data *hw_clks;
	48
	49	struct ccu_reset_map *resets;
	50	unsigned long num_resets;
	51	};
	52
	53	void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock);
	54
02ae2bc6 CYT	55	struct ccu_pll_nb {
	56	struct notifier_block clk_nb;
	57	struct ccu_common *common;
	58
	59	u32 enable;
	60	u32 lock;
	61	};
	62
	63	#define to_ccu_pll_nb(_nb) container_of(_nb, struct ccu_pll_nb, clk_nb)
	64
	65	int ccu_pll_notifier_register(struct ccu_pll_nb *pll_nb);
	66
9bec2b9c SH	67	int devm_sunxi_ccu_probe(struct device dev, void __iomem reg,
	68	const struct sunxi_ccu_desc *desc);
	69	void of_sunxi_ccu_probe(struct device_node node, void __iomem reg,
	70	const struct sunxi_ccu_desc *desc);
1d80c142 MR	71
1d80c142 MR	72	#endif /* _COMMON_H_ */