projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| c6a06374 MR |
1 | /* |
| 2 | * Copyright 2016 Maxime Ripard | |
| 3 | * | |
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License as published by | |
| 8 | * the Free Software Foundation; either version 2 of the License, or | |
| 9 | * (at your option) any later version. | |
| 10 | * | |
| 11 | * This program is distributed in the hope that it will be useful, | |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 | * GNU General Public License for more details. | |
| 15 | */ | |
| 16 | ||
| 17 | #ifndef _CCU_SUN50I_A64_H_ | |
| 18 | #define _CCU_SUN50I_A64_H_ | |
| 19 | ||
| 20 | #include <dt-bindings/clock/sun50i-a64-ccu.h> | |
| 21 | #include <dt-bindings/reset/sun50i-a64-ccu.h> | |
| 22 | ||
| 23 | #define CLK_OSC_12M 0 | |
| 24 | #define CLK_PLL_CPUX 1 | |
| 25 | #define CLK_PLL_AUDIO_BASE 2 | |
| 26 | #define CLK_PLL_AUDIO 3 | |
| 27 | #define CLK_PLL_AUDIO_2X 4 | |
| 28 | #define CLK_PLL_AUDIO_4X 5 | |
| 29 | #define CLK_PLL_AUDIO_8X 6 | |
| 30 | #define CLK_PLL_VIDEO0 7 | |
| 31 | #define CLK_PLL_VIDEO0_2X 8 | |
| 32 | #define CLK_PLL_VE 9 | |
| 33 | #define CLK_PLL_DDR0 10 | |
| 34 | #define CLK_PLL_PERIPH0 11 | |
| 35 | #define CLK_PLL_PERIPH0_2X 12 | |
| 36 | #define CLK_PLL_PERIPH1 13 | |
| 37 | #define CLK_PLL_PERIPH1_2X 14 | |
| 38 | #define CLK_PLL_VIDEO1 15 | |
| 39 | #define CLK_PLL_GPU 16 | |
| 40 | #define CLK_PLL_MIPI 17 | |
| 41 | #define CLK_PLL_HSIC 18 | |
| 42 | #define CLK_PLL_DE 19 | |
| 43 | #define CLK_PLL_DDR1 20 | |
| 44 | #define CLK_CPUX 21 | |
| 45 | #define CLK_AXI 22 | |
| 46 | #define CLK_APB 23 | |
| 47 | #define CLK_AHB1 24 | |
| 48 | #define CLK_APB1 25 | |
| 49 | #define CLK_APB2 26 | |
| 50 | #define CLK_AHB2 27 | |
| 51 | ||
| 52 | /* All the bus gates are exported */ | |
| 53 | ||
| 54 | /* The first bunch of module clocks are exported */ | |
| 55 | ||
| 56 | #define CLK_USB_OHCI0_12M 90 | |
| 57 | ||
| 58 | #define CLK_USB_OHCI1_12M 92 | |
| 59 | ||
| 60 | #define CLK_DRAM 94 | |
| 61 | ||
| 62 | /* All the DRAM gates are exported */ | |
| 63 | ||
| 64 | /* Some more module clocks are exported */ | |
| 65 | ||
| 66 | #define CLK_MBUS 112 | |
| 67 | ||
| 68 | /* And the DSI and GPU module clock is exported */ | |
| 69 | ||
| 70 | #define CLK_NUMBER (CLK_GPU + 1) | |
| 71 | ||
| 72 | #endif /* _CCU_SUN50I_A64_H_ */ |