[linux-block.git] / drivers / clk / sunxi / clk-sun9i-core.c

/*
 * Copyright 2014 Chen-Yu Tsai
 *
 * Chen-Yu Tsai <wens@csie.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/log2.h>

#include "clk-factors.h"


/**
 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
 * PLL4 rate is calculated as follows
 * rate = (parent_rate * n >> p) / (m + 1);
 * parent_rate is always 24MHz
 *
 * p and m are named div1 and div2 in Allwinner's SDK
 */

static void sun9i_a80_get_pll4_factors(struct factors_request *req)
{
	int n;
	int m = 1;
	int p = 1;

	/* Normalize value to a 6 MHz multiple (24 MHz / 4) */
	n = DIV_ROUND_UP(req->rate, 6000000);

	/* If n is too large switch to steps of 12 MHz */
	if (n > 255) {
		m = 0;
		n = (n + 1) / 2;
	}

	/* If n is still too large switch to steps of 24 MHz */
	if (n > 255) {
		p = 0;
		n = (n + 1) / 2;
	}

	/* n must be between 12 and 255 */
	if (n > 255)
		n = 255;
	else if (n < 12)
		n = 12;

	req->rate = ((24000000 * n) >> p) / (m + 1);
	req->n = n;
	req->m = m;
	req->p = p;
}

static const struct clk_factors_config sun9i_a80_pll4_config = {
	.mshift = 18,
	.mwidth = 1,
	.nshift = 8,
	.nwidth = 8,
	.pshift = 16,
	.pwidth = 1,
};

static const struct factors_data sun9i_a80_pll4_data __initconst = {
	.enable = 31,
	.table = &sun9i_a80_pll4_config,
	.getter = sun9i_a80_get_pll4_factors,
};

static DEFINE_SPINLOCK(sun9i_a80_pll4_lock);

static void __init sun9i_a80_pll4_setup(struct device_node *node)
{
	void __iomem *reg;

	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
	if (IS_ERR(reg)) {
		pr_err("Could not get registers for a80-pll4-clk: %pOFn\n",
		       node);
		return;
	}

	sunxi_factors_register(node, &sun9i_a80_pll4_data,
			       &sun9i_a80_pll4_lock, reg);
}
CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);


/**
 * sun9i_a80_get_gt_factors() - calculates m factor for GT
 * GT rate is calculated as follows
 * rate = parent_rate / (m + 1);
 */

static void sun9i_a80_get_gt_factors(struct factors_request *req)
{
	u32 div;

	if (req->parent_rate < req->rate)
		req->rate = req->parent_rate;

	div = DIV_ROUND_UP(req->parent_rate, req->rate);

	/* maximum divider is 4 */
	if (div > 4)
		div = 4;

	req->rate = req->parent_rate / div;
	req->m = div;
}

static const struct clk_factors_config sun9i_a80_gt_config = {
	.mshift = 0,
	.mwidth = 2,
};

static const struct factors_data sun9i_a80_gt_data __initconst = {
	.mux = 24,
	.muxmask = BIT(1) | BIT(0),
	.table = &sun9i_a80_gt_config,
	.getter = sun9i_a80_get_gt_factors,
};

static DEFINE_SPINLOCK(sun9i_a80_gt_lock);

static void __init sun9i_a80_gt_setup(struct device_node *node)
{
	void __iomem *reg;

	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
	if (IS_ERR(reg)) {
		pr_err("Could not get registers for a80-gt-clk: %pOFn\n",
		       node);
		return;
	}

	/* The GT bus clock needs to be always enabled */
	sunxi_factors_register_critical(node, &sun9i_a80_gt_data,
					&sun9i_a80_gt_lock, reg);
}
CLK_OF_DECLARE(sun9i_a80_gt, "allwinner,sun9i-a80-gt-clk", sun9i_a80_gt_setup);


/**
 * sun9i_a80_get_ahb_factors() - calculates p factor for AHB0/1/2
 * AHB rate is calculated as follows
 * rate = parent_rate >> p;
 */

static void sun9i_a80_get_ahb_factors(struct factors_request *req)
{
	u32 _p;

	if (req->parent_rate < req->rate)
		req->rate = req->parent_rate;

	_p = order_base_2(DIV_ROUND_UP(req->parent_rate, req->rate));

	/* maximum p is 3 */
	if (_p > 3)
		_p = 3;

	req->rate = req->parent_rate >> _p;
	req->p = _p;
}

static const struct clk_factors_config sun9i_a80_ahb_config = {
	.pshift = 0,
	.pwidth = 2,
};

static const struct factors_data sun9i_a80_ahb_data __initconst = {
	.mux = 24,
	.muxmask = BIT(1) | BIT(0),
	.table = &sun9i_a80_ahb_config,
	.getter = sun9i_a80_get_ahb_factors,
};

static DEFINE_SPINLOCK(sun9i_a80_ahb_lock);

static void __init sun9i_a80_ahb_setup(struct device_node *node)
{
	void __iomem *reg;

	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
	if (IS_ERR(reg)) {
		pr_err("Could not get registers for a80-ahb-clk: %pOFn\n",
		       node);
		return;
	}

	sunxi_factors_register(node, &sun9i_a80_ahb_data,
			       &sun9i_a80_ahb_lock, reg);
}
CLK_OF_DECLARE(sun9i_a80_ahb, "allwinner,sun9i-a80-ahb-clk", sun9i_a80_ahb_setup);


static const struct factors_data sun9i_a80_apb0_data __initconst = {
	.mux = 24,
	.muxmask = BIT(0),
	.table = &sun9i_a80_ahb_config,
	.getter = sun9i_a80_get_ahb_factors,
};

static DEFINE_SPINLOCK(sun9i_a80_apb0_lock);

static void __init sun9i_a80_apb0_setup(struct device_node *node)
{
	void __iomem *reg;

	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
	if (IS_ERR(reg)) {
		pr_err("Could not get registers for a80-apb0-clk: %pOFn\n",
		       node);
		return;
	}

	sunxi_factors_register(node, &sun9i_a80_apb0_data,
			       &sun9i_a80_apb0_lock, reg);
}
CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_setup);


/**
 * sun9i_a80_get_apb1_factors() - calculates m, p factors for APB1
 * APB1 rate is calculated as follows
 * rate = (parent_rate >> p) / (m + 1);
 */

static void sun9i_a80_get_apb1_factors(struct factors_request *req)
{
	u32 div;

	if (req->parent_rate < req->rate)
		req->rate = req->parent_rate;

	div = DIV_ROUND_UP(req->parent_rate, req->rate);

	/* Highest possible divider is 256 (p = 3, m = 31) */
	if (div > 256)
		div = 256;

	req->p = order_base_2(div);
	req->m = (req->parent_rate >> req->p) - 1;
	req->rate = (req->parent_rate >> req->p) / (req->m + 1);
}

static const struct clk_factors_config sun9i_a80_apb1_config = {
	.mshift = 0,
	.mwidth = 5,
	.pshift = 16,
	.pwidth = 2,
};

static const struct factors_data sun9i_a80_apb1_data __initconst = {
	.mux = 24,
	.muxmask = BIT(0),
	.table = &sun9i_a80_apb1_config,
	.getter = sun9i_a80_get_apb1_factors,
};

static DEFINE_SPINLOCK(sun9i_a80_apb1_lock);

static void __init sun9i_a80_apb1_setup(struct device_node *node)
{
	void __iomem *reg;

	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
	if (IS_ERR(reg)) {
		pr_err("Could not get registers for a80-apb1-clk: %pOFn\n",
		       node);
		return;
	}

	sunxi_factors_register(node, &sun9i_a80_apb1_data,
			       &sun9i_a80_apb1_lock, reg);
}
CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-clk", sun9i_a80_apb1_setup);
Commit	Line	Data
3b2bd70f CYT	1	/*
	2	* Copyright 2014 Chen-Yu Tsai
	3	*
	4	* Chen-Yu Tsai <wens@csie.org>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16
9dfefe8c	17	#include <linux/clk.h>
3b2bd70f	18	#include <linux/clk-provider.h>
3b2bd70f CYT	19	#include <linux/of.h>
	20	#include <linux/of_address.h>
	21	#include <linux/log2.h>
	22
	23	#include "clk-factors.h"
	24
	25
	26	/**
6424e0ae	27	* sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
3b2bd70f CYT	28	* PLL4 rate is calculated as follows
3b2bd70f CYT	29	* rate = (parent_rate * n >> p) / (m + 1);
6424e0ae	30	* parent_rate is always 24MHz
3b2bd70f CYT	31	*
	32	* p and m are named div1 and div2 in Allwinner's SDK
	33	*/
	34
cfa63688	35	static void sun9i_a80_get_pll4_factors(struct factors_request *req)
3b2bd70f	36	{
6424e0ae HG	37	int n;
	38	int m = 1;
	39	int p = 1;
3b2bd70f	40
6424e0ae	41	/* Normalize value to a 6 MHz multiple (24 MHz / 4) */
cfa63688	42	n = DIV_ROUND_UP(req->rate, 6000000);
3b2bd70f	43
6424e0ae HG	44	/* If n is too large switch to steps of 12 MHz */
	45	if (n > 255) {
	46	m = 0;
	47	n = (n + 1) / 2;
	48	}
3b2bd70f	49
6424e0ae HG	50	/* If n is still too large switch to steps of 24 MHz */
	51	if (n > 255) {
	52	p = 0;
	53	n = (n + 1) / 2;
	54	}
3b2bd70f	55
6424e0ae HG	56	/* n must be between 12 and 255 */
	57	if (n > 255)
	58	n = 255;
	59	else if (n < 12)
	60	n = 12;
	61
cfa63688 CYT	62	req->rate = ((24000000 * n) >> p) / (m + 1);
	63	req->n = n;
	64	req->m = m;
	65	req->p = p;
3b2bd70f CYT	66	}
3b2bd70f CYT	67
b3e919e0	68	static const struct clk_factors_config sun9i_a80_pll4_config = {
3b2bd70f CYT	69	.mshift = 18,
	70	.mwidth = 1,
	71	.nshift = 8,
	72	.nwidth = 8,
	73	.pshift = 16,
	74	.pwidth = 1,
	75	};
	76
	77	static const struct factors_data sun9i_a80_pll4_data __initconst = {
	78	.enable = 31,
	79	.table = &sun9i_a80_pll4_config,
	80	.getter = sun9i_a80_get_pll4_factors,
	81	};
	82
	83	static DEFINE_SPINLOCK(sun9i_a80_pll4_lock);
	84
	85	static void __init sun9i_a80_pll4_setup(struct device_node *node)
	86	{
66e79cf1 CYT	87	void __iomem *reg;
	88
	89	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
5ac382c3	90	if (IS_ERR(reg)) {
e665f029 RH	91	pr_err("Could not get registers for a80-pll4-clk: %pOFn\n",
e665f029 RH	92	node);
66e79cf1 CYT	93	return;
	94	}
	95
	96	sunxi_factors_register(node, &sun9i_a80_pll4_data,
	97	&sun9i_a80_pll4_lock, reg);
3b2bd70f CYT	98	}
	99	CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);
	100
	101
	102	/**
	103	* sun9i_a80_get_gt_factors() - calculates m factor for GT
	104	* GT rate is calculated as follows
	105	* rate = parent_rate / (m + 1);
	106	*/
	107
cfa63688	108	static void sun9i_a80_get_gt_factors(struct factors_request *req)
3b2bd70f CYT	109	{
	110	u32 div;
	111
cfa63688 CYT	112	if (req->parent_rate < req->rate)
cfa63688 CYT	113	req->rate = req->parent_rate;
3b2bd70f	114
cfa63688	115	div = DIV_ROUND_UP(req->parent_rate, req->rate);
3b2bd70f CYT	116
	117	/* maximum divider is 4 */
	118	if (div > 4)
	119	div = 4;
	120
cfa63688 CYT	121	req->rate = req->parent_rate / div;
cfa63688 CYT	122	req->m = div;
3b2bd70f CYT	123	}
3b2bd70f CYT	124
b3e919e0	125	static const struct clk_factors_config sun9i_a80_gt_config = {
3b2bd70f CYT	126	.mshift = 0,
	127	.mwidth = 2,
	128	};
	129
	130	static const struct factors_data sun9i_a80_gt_data __initconst = {
	131	.mux = 24,
	132	.muxmask = BIT(1) \| BIT(0),
	133	.table = &sun9i_a80_gt_config,
	134	.getter = sun9i_a80_get_gt_factors,
	135	};
	136
	137	static DEFINE_SPINLOCK(sun9i_a80_gt_lock);
	138
	139	static void __init sun9i_a80_gt_setup(struct device_node *node)
	140	{
66e79cf1	141	void __iomem *reg;
66e79cf1 CYT	142
66e79cf1 CYT	143	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
5ac382c3	144	if (IS_ERR(reg)) {
e665f029 RH	145	pr_err("Could not get registers for a80-gt-clk: %pOFn\n",
e665f029 RH	146	node);
66e79cf1 CYT	147	return;
	148	}
	149
3b2bd70f	150	/* The GT bus clock needs to be always enabled */
9919d44f SB	151	sunxi_factors_register_critical(node, &sun9i_a80_gt_data,
9919d44f SB	152	&sun9i_a80_gt_lock, reg);
3b2bd70f CYT	153	}
	154	CLK_OF_DECLARE(sun9i_a80_gt, "allwinner,sun9i-a80-gt-clk", sun9i_a80_gt_setup);
	155
	156
	157	/**
	158	* sun9i_a80_get_ahb_factors() - calculates p factor for AHB0/1/2
	159	* AHB rate is calculated as follows
	160	* rate = parent_rate >> p;
	161	*/
	162
cfa63688	163	static void sun9i_a80_get_ahb_factors(struct factors_request *req)
3b2bd70f CYT	164	{
	165	u32 _p;
	166
cfa63688 CYT	167	if (req->parent_rate < req->rate)
cfa63688 CYT	168	req->rate = req->parent_rate;
3b2bd70f	169
cfa63688	170	_p = order_base_2(DIV_ROUND_UP(req->parent_rate, req->rate));
3b2bd70f CYT	171
	172	/* maximum p is 3 */
	173	if (_p > 3)
	174	_p = 3;
	175
cfa63688 CYT	176	req->rate = req->parent_rate >> _p;
cfa63688 CYT	177	req->p = _p;
3b2bd70f CYT	178	}
3b2bd70f CYT	179
b3e919e0	180	static const struct clk_factors_config sun9i_a80_ahb_config = {
3b2bd70f CYT	181	.pshift = 0,
	182	.pwidth = 2,
	183	};
	184
	185	static const struct factors_data sun9i_a80_ahb_data __initconst = {
	186	.mux = 24,
	187	.muxmask = BIT(1) \| BIT(0),
	188	.table = &sun9i_a80_ahb_config,
	189	.getter = sun9i_a80_get_ahb_factors,
	190	};
	191
	192	static DEFINE_SPINLOCK(sun9i_a80_ahb_lock);
	193
	194	static void __init sun9i_a80_ahb_setup(struct device_node *node)
	195	{
66e79cf1 CYT	196	void __iomem *reg;
	197
	198	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
5ac382c3	199	if (IS_ERR(reg)) {
e665f029 RH	200	pr_err("Could not get registers for a80-ahb-clk: %pOFn\n",
e665f029 RH	201	node);
66e79cf1 CYT	202	return;
	203	}
	204
	205	sunxi_factors_register(node, &sun9i_a80_ahb_data,
	206	&sun9i_a80_ahb_lock, reg);
3b2bd70f CYT	207	}
	208	CLK_OF_DECLARE(sun9i_a80_ahb, "allwinner,sun9i-a80-ahb-clk", sun9i_a80_ahb_setup);
	209
	210
	211	static const struct factors_data sun9i_a80_apb0_data __initconst = {
	212	.mux = 24,
	213	.muxmask = BIT(0),
	214	.table = &sun9i_a80_ahb_config,
	215	.getter = sun9i_a80_get_ahb_factors,
	216	};
	217
	218	static DEFINE_SPINLOCK(sun9i_a80_apb0_lock);
	219
	220	static void __init sun9i_a80_apb0_setup(struct device_node *node)
	221	{
66e79cf1 CYT	222	void __iomem *reg;
	223
	224	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
5ac382c3	225	if (IS_ERR(reg)) {
e665f029 RH	226	pr_err("Could not get registers for a80-apb0-clk: %pOFn\n",
e665f029 RH	227	node);
66e79cf1 CYT	228	return;
	229	}
	230
	231	sunxi_factors_register(node, &sun9i_a80_apb0_data,
	232	&sun9i_a80_apb0_lock, reg);
3b2bd70f CYT	233	}
	234	CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_setup);
	235
	236
	237	/**
	238	* sun9i_a80_get_apb1_factors() - calculates m, p factors for APB1
	239	* APB1 rate is calculated as follows
	240	* rate = (parent_rate >> p) / (m + 1);
	241	*/
	242
cfa63688	243	static void sun9i_a80_get_apb1_factors(struct factors_request *req)
3b2bd70f CYT	244	{
3b2bd70f CYT	245	u32 div;
3b2bd70f	246
cfa63688 CYT	247	if (req->parent_rate < req->rate)
cfa63688 CYT	248	req->rate = req->parent_rate;
3b2bd70f	249
cfa63688	250	div = DIV_ROUND_UP(req->parent_rate, req->rate);
3b2bd70f CYT	251
	252	/* Highest possible divider is 256 (p = 3, m = 31) */
	253	if (div > 256)
	254	div = 256;
	255
cfa63688 CYT	256	req->p = order_base_2(div);
	257	req->m = (req->parent_rate >> req->p) - 1;
	258	req->rate = (req->parent_rate >> req->p) / (req->m + 1);
3b2bd70f CYT	259	}
3b2bd70f CYT	260
b3e919e0	261	static const struct clk_factors_config sun9i_a80_apb1_config = {
3b2bd70f CYT	262	.mshift = 0,
	263	.mwidth = 5,
	264	.pshift = 16,
	265	.pwidth = 2,
	266	};
	267
	268	static const struct factors_data sun9i_a80_apb1_data __initconst = {
	269	.mux = 24,
	270	.muxmask = BIT(0),
	271	.table = &sun9i_a80_apb1_config,
	272	.getter = sun9i_a80_get_apb1_factors,
	273	};
	274
	275	static DEFINE_SPINLOCK(sun9i_a80_apb1_lock);
	276
	277	static void __init sun9i_a80_apb1_setup(struct device_node *node)
	278	{
66e79cf1 CYT	279	void __iomem *reg;
	280
	281	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
5ac382c3	282	if (IS_ERR(reg)) {
e665f029 RH	283	pr_err("Could not get registers for a80-apb1-clk: %pOFn\n",
e665f029 RH	284	node);
66e79cf1 CYT	285	return;
	286	}
	287
	288	sunxi_factors_register(node, &sun9i_a80_apb1_data,
	289	&sun9i_a80_apb1_lock, reg);
3b2bd70f CYT	290	}
3b2bd70f CYT	291	CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-clk", sun9i_a80_apb1_setup);