[linux-2.6-block.git] / drivers / clk / sunxi / clk-sun6i-ar100.c

/*
 * Copyright (C) 2014 Free Electrons
 *
 * License Terms: GNU General Public License v2
 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
 *
 * Allwinner A31 AR100 clock driver
 *
 */

#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>

#include "clk-factors.h"

/**
 * sun6i_get_ar100_factors - Calculates factors p, m for AR100
 *
 * AR100 rate is calculated as follows
 * rate = (parent_rate >> p) / (m + 1);
 */
static void sun6i_get_ar100_factors(struct factors_request *req)
{
	unsigned long div;
	int shift;

	/* clock only divides */
	if (req->rate > req->parent_rate)
		req->rate = req->parent_rate;

	div = DIV_ROUND_UP(req->parent_rate, req->rate);

	if (div < 32)
		shift = 0;
	else if (div >> 1 < 32)
		shift = 1;
	else if (div >> 2 < 32)
		shift = 2;
	else
		shift = 3;

	div >>= shift;

	if (div > 32)
		div = 32;

	req->rate = (req->parent_rate >> shift) / div;
	req->m = div - 1;
	req->p = shift;
}

static const struct clk_factors_config sun6i_ar100_config = {
	.mwidth = 5,
	.mshift = 8,
	.pwidth = 2,
	.pshift = 4,
};

static const struct factors_data sun6i_ar100_data = {
	.mux = 16,
	.muxmask = GENMASK(1, 0),
	.table = &sun6i_ar100_config,
	.getter = sun6i_get_ar100_factors,
};

static DEFINE_SPINLOCK(sun6i_ar100_lock);

static int sun6i_a31_ar100_clk_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct resource *r;
	void __iomem *reg;
	struct clk *clk;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	reg = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(reg))
		return PTR_ERR(reg);

	clk = sunxi_factors_register(np, &sun6i_ar100_data, &sun6i_ar100_lock,
				     reg);
	if (!clk)
		return -ENOMEM;

	platform_set_drvdata(pdev, clk);

	return 0;
}

static int sun6i_a31_ar100_clk_remove(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct clk *clk = platform_get_drvdata(pdev);

	sunxi_factors_unregister(np, clk);

	return 0;
}

static const struct of_device_id sun6i_a31_ar100_clk_dt_ids[] = {
	{ .compatible = "allwinner,sun6i-a31-ar100-clk" },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sun6i_a31_ar100_clk_dt_ids);

static struct platform_driver sun6i_a31_ar100_clk_driver = {
	.driver = {
		.name = "sun6i-a31-ar100-clk",
		.of_match_table = sun6i_a31_ar100_clk_dt_ids,
	},
	.probe = sun6i_a31_ar100_clk_probe,
	.remove = sun6i_a31_ar100_clk_remove,
};
module_platform_driver(sun6i_a31_ar100_clk_driver);

MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>");
MODULE_DESCRIPTION("Allwinner A31 AR100 clock Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
c8a76cac BB	1	/*
	2	* Copyright (C) 2014 Free Electrons
	3	*
	4	* License Terms: GNU General Public License v2
	5	* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
	6	*
	7	* Allwinner A31 AR100 clock driver
	8	*
	9	*/
	10
3ca2377b	11	#include <linux/bitops.h>
c8a76cac BB	12	#include <linux/clk-provider.h>
	13	#include <linux/module.h>
	14	#include <linux/of.h>
	15	#include <linux/platform_device.h>
3ca2377b	16	#include <linux/spinlock.h>
c8a76cac	17
3ca2377b	18	#include "clk-factors.h"
c8a76cac	19
3ca2377b CYT	20	/**
	21	* sun6i_get_ar100_factors - Calculates factors p, m for AR100
	22	*
	23	* AR100 rate is calculated as follows
	24	* rate = (parent_rate >> p) / (m + 1);
	25	*/
	26	static void sun6i_get_ar100_factors(struct factors_request *req)
c8a76cac	27	{
3ca2377b	28	unsigned long div;
c8a76cac BB	29	int shift;
c8a76cac BB	30
3ca2377b CYT	31	/* clock only divides */
	32	if (req->rate > req->parent_rate)
	33	req->rate = req->parent_rate;
c8a76cac	34
3ca2377b	35	div = DIV_ROUND_UP(req->parent_rate, req->rate);
c8a76cac	36
3ca2377b CYT	37	if (div < 32)
	38	shift = 0;
	39	else if (div >> 1 < 32)
	40	shift = 1;
	41	else if (div >> 2 < 32)
	42	shift = 2;
	43	else
	44	shift = 3;
c8a76cac	45
3ca2377b	46	div >>= shift;
c8a76cac	47
3ca2377b CYT	48	if (div > 32)
3ca2377b CYT	49	div = 32;
c8a76cac	50
3ca2377b CYT	51	req->rate = (req->parent_rate >> shift) / div;
	52	req->m = div - 1;
	53	req->p = shift;
c8a76cac BB	54	}
c8a76cac BB	55
3ca2377b CYT	56	static const struct clk_factors_config sun6i_ar100_config = {
	57	.mwidth = 5,
	58	.mshift = 8,
	59	.pwidth = 2,
	60	.pshift = 4,
c8a76cac BB	61	};
c8a76cac BB	62
14b5a4bf	63	static const struct factors_data sun6i_ar100_data = {
3ca2377b CYT	64	.mux = 16,
	65	.muxmask = GENMASK(1, 0),
	66	.table = &sun6i_ar100_config,
	67	.getter = sun6i_get_ar100_factors,
	68	};
	69
	70	static DEFINE_SPINLOCK(sun6i_ar100_lock);
	71
c8a76cac BB	72	static int sun6i_a31_ar100_clk_probe(struct platform_device *pdev)
c8a76cac BB	73	{
c8a76cac	74	struct device_node *np = pdev->dev.of_node;
c8a76cac	75	struct resource *r;
3ca2377b	76	void __iomem *reg;
c8a76cac	77	struct clk *clk;
c8a76cac BB	78
c8a76cac BB	79	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3ca2377b CYT	80	reg = devm_ioremap_resource(&pdev->dev, r);
	81	if (IS_ERR(reg))
	82	return PTR_ERR(reg);
c8a76cac	83
3ca2377b CYT	84	clk = sunxi_factors_register(np, &sun6i_ar100_data, &sun6i_ar100_lock,
	85	reg);
	86	if (!clk)
	87	return -ENOMEM;
c8a76cac	88
3ca2377b	89	platform_set_drvdata(pdev, clk);
c8a76cac	90
3ca2377b CYT	91	return 0;
3ca2377b CYT	92	}
c8a76cac	93
3ca2377b CYT	94	static int sun6i_a31_ar100_clk_remove(struct platform_device *pdev)
	95	{
	96	struct device_node *np = pdev->dev.of_node;
	97	struct clk *clk = platform_get_drvdata(pdev);
c8a76cac	98
3ca2377b	99	sunxi_factors_unregister(np, clk);
c8a76cac	100
3ca2377b	101	return 0;
c8a76cac BB	102	}
c8a76cac BB	103
381c1ccd	104	static const struct of_device_id sun6i_a31_ar100_clk_dt_ids[] = {
c8a76cac BB	105	{ .compatible = "allwinner,sun6i-a31-ar100-clk" },
	106	{ /* sentinel */ }
	107	};
ad915483	108	MODULE_DEVICE_TABLE(of, sun6i_a31_ar100_clk_dt_ids);
c8a76cac BB	109
	110	static struct platform_driver sun6i_a31_ar100_clk_driver = {
	111	.driver = {
	112	.name = "sun6i-a31-ar100-clk",
c8a76cac BB	113	.of_match_table = sun6i_a31_ar100_clk_dt_ids,
	114	},
	115	.probe = sun6i_a31_ar100_clk_probe,
3ca2377b	116	.remove = sun6i_a31_ar100_clk_remove,
c8a76cac BB	117	};
	118	module_platform_driver(sun6i_a31_ar100_clk_driver);
	119
	120	MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>");
	121	MODULE_DESCRIPTION("Allwinner A31 AR100 clock Driver");
	122	MODULE_LICENSE("GPL v2");