[linux-2.6-block.git] / drivers / clk / sunxi / clk-mod0.c

/*
 * Copyright 2013 Emilio López
 *
 * Emilio López <emilio@elopez.com.ar>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/of_address.h>

#include "clk-factors.h"

/**
 * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
 * MOD0 rate is calculated as follows
 * rate = (parent_rate >> p) / (m + 1);
 */

static void sun4i_a10_get_mod0_factors(u32 *freq, u32 parent_rate,
				       u8 *n, u8 *k, u8 *m, u8 *p)
{
	u8 div, calcm, calcp;

	/* These clocks can only divide, so we will never be able to achieve
	 * frequencies higher than the parent frequency */
	if (*freq > parent_rate)
		*freq = parent_rate;

	div = DIV_ROUND_UP(parent_rate, *freq);

	if (div < 16)
		calcp = 0;
	else if (div / 2 < 16)
		calcp = 1;
	else if (div / 4 < 16)
		calcp = 2;
	else
		calcp = 3;

	calcm = DIV_ROUND_UP(div, 1 << calcp);

	*freq = (parent_rate >> calcp) / calcm;

	/* we were called to round the frequency, we can now return */
	if (n == NULL)
		return;

	*m = calcm - 1;
	*p = calcp;
}

/* user manual says "n" but it's really "p" */
static struct clk_factors_config sun4i_a10_mod0_config = {
	.mshift = 0,
	.mwidth = 4,
	.pshift = 16,
	.pwidth = 2,
};

static const struct factors_data sun4i_a10_mod0_data __initconst = {
	.enable = 31,
	.mux = 24,
	.table = &sun4i_a10_mod0_config,
	.getter = sun4i_a10_get_mod0_factors,
};

static DEFINE_SPINLOCK(sun4i_a10_mod0_lock);

static void __init sun4i_a10_mod0_setup(struct device_node *node)
{
	sunxi_factors_register(node, &sun4i_a10_mod0_data, &sun4i_a10_mod0_lock);
}
CLK_OF_DECLARE(sun4i_a10_mod0, "allwinner,sun4i-a10-mod0-clk", sun4i_a10_mod0_setup);

static DEFINE_SPINLOCK(sun5i_a13_mbus_lock);

static void __init sun5i_a13_mbus_setup(struct device_node *node)
{
	struct clk *mbus = sunxi_factors_register(node, &sun4i_a10_mod0_data, &sun5i_a13_mbus_lock);

	/* The MBUS clocks needs to be always enabled */
	__clk_get(mbus);
	clk_prepare_enable(mbus);
}
CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup);

struct mmc_phase_data {
	u8	offset;
};

struct mmc_phase {
	struct clk_hw		hw;
	void __iomem		*reg;
	struct mmc_phase_data	*data;
	spinlock_t		*lock;
};

#define to_mmc_phase(_hw) container_of(_hw, struct mmc_phase, hw)

static int mmc_get_phase(struct clk_hw *hw)
{
	struct clk *mmc, *mmc_parent, *clk = hw->clk;
	struct mmc_phase *phase = to_mmc_phase(hw);
	unsigned int mmc_rate, mmc_parent_rate;
	u16 step, mmc_div;
	u32 value;
	u8 delay;

	value = readl(phase->reg);
	delay = (value >> phase->data->offset) & 0x3;

	if (!delay)
		return 180;

	/* Get the main MMC clock */
	mmc = clk_get_parent(clk);
	if (!mmc)
		return -EINVAL;

	/* And its rate */
	mmc_rate = clk_get_rate(mmc);
	if (!mmc_rate)
		return -EINVAL;

	/* Now, get the MMC parent (most likely some PLL) */
	mmc_parent = clk_get_parent(mmc);
	if (!mmc_parent)
		return -EINVAL;

	/* And its rate */
	mmc_parent_rate = clk_get_rate(mmc_parent);
	if (!mmc_parent_rate)
		return -EINVAL;

	/* Get MMC clock divider */
	mmc_div = mmc_parent_rate / mmc_rate;

	step = DIV_ROUND_CLOSEST(360, mmc_div);
	return delay * step;
}

static int mmc_set_phase(struct clk_hw *hw, int degrees)
{
	struct clk *mmc, *mmc_parent, *clk = hw->clk;
	struct mmc_phase *phase = to_mmc_phase(hw);
	unsigned int mmc_rate, mmc_parent_rate;
	unsigned long flags;
	u32 value;
	u8 delay;

	/* Get the main MMC clock */
	mmc = clk_get_parent(clk);
	if (!mmc)
		return -EINVAL;

	/* And its rate */
	mmc_rate = clk_get_rate(mmc);
	if (!mmc_rate)
		return -EINVAL;

	/* Now, get the MMC parent (most likely some PLL) */
	mmc_parent = clk_get_parent(mmc);
	if (!mmc_parent)
		return -EINVAL;

	/* And its rate */
	mmc_parent_rate = clk_get_rate(mmc_parent);
	if (!mmc_parent_rate)
		return -EINVAL;

	if (degrees != 180) {
		u16 step, mmc_div;

		/* Get MMC clock divider */
		mmc_div = mmc_parent_rate / mmc_rate;

		/*
		 * We can only outphase the clocks by multiple of the
		 * PLL's period.
		 *
		 * Since the MMC clock in only a divider, and the
		 * formula to get the outphasing in degrees is deg =
		 * 360 * delta / period
		 *
		 * If we simplify this formula, we can see that the
		 * only thing that we're concerned about is the number
		 * of period we want to outphase our clock from, and
		 * the divider set by the MMC clock.
		 */
		step = DIV_ROUND_CLOSEST(360, mmc_div);
		delay = DIV_ROUND_CLOSEST(degrees, step);
	} else {
		delay = 0;
	}

	spin_lock_irqsave(phase->lock, flags);
	value = readl(phase->reg);
	value &= ~GENMASK(phase->data->offset + 3, phase->data->offset);
	value |= delay << phase->data->offset;
	writel(value, phase->reg);
	spin_unlock_irqrestore(phase->lock, flags);

	return 0;
}

static const struct clk_ops mmc_clk_ops = {
	.get_phase	= mmc_get_phase,
	.set_phase	= mmc_set_phase,
};

static void __init sun4i_a10_mmc_phase_setup(struct device_node *node,
					     struct mmc_phase_data *data)
{
	const char *parent_names[1] = { of_clk_get_parent_name(node, 0) };
	struct clk_init_data init = {
		.num_parents	= 1,
		.parent_names	= parent_names,
		.ops		= &mmc_clk_ops,
	};

	struct mmc_phase *phase;
	struct clk *clk;

	phase = kmalloc(sizeof(*phase), GFP_KERNEL);
	if (!phase)
		return;

	phase->hw.init = &init;

	phase->reg = of_iomap(node, 0);
	if (!phase->reg)
		goto err_free;

	phase->data = data;
	phase->lock = &sun4i_a10_mod0_lock;

	if (of_property_read_string(node, "clock-output-names", &init.name))
		init.name = node->name;

	clk = clk_register(NULL, &phase->hw);
	if (IS_ERR(clk))
		goto err_unmap;

	of_clk_add_provider(node, of_clk_src_simple_get, clk);

	return;

err_unmap:
	iounmap(phase->reg);
err_free:
	kfree(phase);
}


static struct mmc_phase_data mmc_output_clk = {
	.offset	= 8,
};

static struct mmc_phase_data mmc_sample_clk = {
	.offset	= 20,
};

static void __init sun4i_a10_mmc_output_setup(struct device_node *node)
{
	sun4i_a10_mmc_phase_setup(node, &mmc_output_clk);
}
CLK_OF_DECLARE(sun4i_a10_mmc_output, "allwinner,sun4i-a10-mmc-output-clk", sun4i_a10_mmc_output_setup);

static void __init sun4i_a10_mmc_sample_setup(struct device_node *node)
{
	sun4i_a10_mmc_phase_setup(node, &mmc_sample_clk);
}
CLK_OF_DECLARE(sun4i_a10_mmc_sample, "allwinner,sun4i-a10-mmc-sample-clk", sun4i_a10_mmc_sample_setup);
Commit	Line	Data
992a56e4 MR	1	/*
	2	* Copyright 2013 Emilio López
	3	*
	4	* Emilio López <emilio@elopez.com.ar>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16
	17	#include <linux/clk-provider.h>
	18	#include <linux/clkdev.h>
37e1041f	19	#include <linux/of_address.h>
992a56e4 MR	20
	21	#include "clk-factors.h"
	22
	23	/**
	24	* sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
	25	* MOD0 rate is calculated as follows
	26	* rate = (parent_rate >> p) / (m + 1);
	27	*/
	28
	29	static void sun4i_a10_get_mod0_factors(u32 *freq, u32 parent_rate,
	30	u8 n, u8 k, u8 m, u8 p)
	31	{
	32	u8 div, calcm, calcp;
	33
	34	/* These clocks can only divide, so we will never be able to achieve
	35	* frequencies higher than the parent frequency */
	36	if (*freq > parent_rate)
	37	*freq = parent_rate;
	38
	39	div = DIV_ROUND_UP(parent_rate, *freq);
	40
	41	if (div < 16)
	42	calcp = 0;
	43	else if (div / 2 < 16)
	44	calcp = 1;
	45	else if (div / 4 < 16)
	46	calcp = 2;
	47	else
	48	calcp = 3;
	49
	50	calcm = DIV_ROUND_UP(div, 1 << calcp);
	51
	52	*freq = (parent_rate >> calcp) / calcm;
	53
	54	/* we were called to round the frequency, we can now return */
	55	if (n == NULL)
	56	return;
	57
	58	*m = calcm - 1;
	59	*p = calcp;
	60	}
	61
	62	/* user manual says "n" but it's really "p" */
	63	static struct clk_factors_config sun4i_a10_mod0_config = {
	64	.mshift = 0,
	65	.mwidth = 4,
	66	.pshift = 16,
	67	.pwidth = 2,
	68	};
	69
	70	static const struct factors_data sun4i_a10_mod0_data __initconst = {
	71	.enable = 31,
	72	.mux = 24,
	73	.table = &sun4i_a10_mod0_config,
	74	.getter = sun4i_a10_get_mod0_factors,
	75	};
	76
	77	static DEFINE_SPINLOCK(sun4i_a10_mod0_lock);
	78
	79	static void __init sun4i_a10_mod0_setup(struct device_node *node)
	80	{
	81	sunxi_factors_register(node, &sun4i_a10_mod0_data, &sun4i_a10_mod0_lock);
	82	}
	83	CLK_OF_DECLARE(sun4i_a10_mod0, "allwinner,sun4i-a10-mod0-clk", sun4i_a10_mod0_setup);
eaa18f5d MR	84
	85	static DEFINE_SPINLOCK(sun5i_a13_mbus_lock);
	86
	87	static void __init sun5i_a13_mbus_setup(struct device_node *node)
	88	{
	89	struct clk *mbus = sunxi_factors_register(node, &sun4i_a10_mod0_data, &sun5i_a13_mbus_lock);
	90
	91	/* The MBUS clocks needs to be always enabled */
	92	__clk_get(mbus);
	93	clk_prepare_enable(mbus);
	94	}
	95	CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup);
37e1041f MR	96
	97	struct mmc_phase_data {
	98	u8 offset;
	99	};
	100
	101	struct mmc_phase {
	102	struct clk_hw hw;
	103	void __iomem *reg;
	104	struct mmc_phase_data *data;
	105	spinlock_t *lock;
	106	};
	107
	108	#define to_mmc_phase(_hw) container_of(_hw, struct mmc_phase, hw)
	109
	110	static int mmc_get_phase(struct clk_hw *hw)
	111	{
	112	struct clk mmc, mmc_parent, *clk = hw->clk;
	113	struct mmc_phase *phase = to_mmc_phase(hw);
	114	unsigned int mmc_rate, mmc_parent_rate;
	115	u16 step, mmc_div;
	116	u32 value;
	117	u8 delay;
	118
	119	value = readl(phase->reg);
	120	delay = (value >> phase->data->offset) & 0x3;
	121
	122	if (!delay)
	123	return 180;
	124
	125	/* Get the main MMC clock */
	126	mmc = clk_get_parent(clk);
	127	if (!mmc)
	128	return -EINVAL;
	129
	130	/* And its rate */
	131	mmc_rate = clk_get_rate(mmc);
	132	if (!mmc_rate)
	133	return -EINVAL;
	134
	135	/* Now, get the MMC parent (most likely some PLL) */
	136	mmc_parent = clk_get_parent(mmc);
	137	if (!mmc_parent)
	138	return -EINVAL;
	139
	140	/* And its rate */
	141	mmc_parent_rate = clk_get_rate(mmc_parent);
	142	if (!mmc_parent_rate)
	143	return -EINVAL;
	144
	145	/* Get MMC clock divider */
	146	mmc_div = mmc_parent_rate / mmc_rate;
	147
	148	step = DIV_ROUND_CLOSEST(360, mmc_div);
	149	return delay * step;
	150	}
	151
	152	static int mmc_set_phase(struct clk_hw *hw, int degrees)
	153	{
	154	struct clk mmc, mmc_parent, *clk = hw->clk;
	155	struct mmc_phase *phase = to_mmc_phase(hw);
	156	unsigned int mmc_rate, mmc_parent_rate;
	157	unsigned long flags;
	158	u32 value;
	159	u8 delay;
160
161	/* Get the main MMC clock */
162	mmc = clk_get_parent(clk);
163	if (!mmc)
164	return -EINVAL;
165
166	/* And its rate */
167	mmc_rate = clk_get_rate(mmc);
168	if (!mmc_rate)
169	return -EINVAL;
170
171	/* Now, get the MMC parent (most likely some PLL) */
172	mmc_parent = clk_get_parent(mmc);
173	if (!mmc_parent)
174	return -EINVAL;
175
176	/* And its rate */
177	mmc_parent_rate = clk_get_rate(mmc_parent);
178	if (!mmc_parent_rate)
179	return -EINVAL;
180
181	if (degrees != 180) {
182	u16 step, mmc_div;
183
184	/* Get MMC clock divider */
185	mmc_div = mmc_parent_rate / mmc_rate;
186
187	/*
188	* We can only outphase the clocks by multiple of the
189	* PLL's period.
190	*
191	* Since the MMC clock in only a divider, and the
192	* formula to get the outphasing in degrees is deg =
193	* 360 * delta / period
194	*
195	* If we simplify this formula, we can see that the
196	* only thing that we're concerned about is the number
197	* of period we want to outphase our clock from, and
198	* the divider set by the MMC clock.
199	*/
200	step = DIV_ROUND_CLOSEST(360, mmc_div);
201	delay = DIV_ROUND_CLOSEST(degrees, step);
202	} else {
203	delay = 0;
204	}
205
206	spin_lock_irqsave(phase->lock, flags);
207	value = readl(phase->reg);
208	value &= ~GENMASK(phase->data->offset + 3, phase->data->offset);
209	value \|= delay << phase->data->offset;
210	writel(value, phase->reg);
211	spin_unlock_irqrestore(phase->lock, flags);
212
213	return 0;
214	}
215
216	static const struct clk_ops mmc_clk_ops = {
217	.get_phase = mmc_get_phase,
218	.set_phase = mmc_set_phase,
219	};
220
221	static void __init sun4i_a10_mmc_phase_setup(struct device_node *node,
222	struct mmc_phase_data *data)
223	{
224	const char *parent_names[1] = { of_clk_get_parent_name(node, 0) };
225	struct clk_init_data init = {
226	.num_parents = 1,
227	.parent_names = parent_names,
228	.ops = &mmc_clk_ops,
229	};
230
231	struct mmc_phase *phase;
232	struct clk *clk;
233
234	phase = kmalloc(sizeof(*phase), GFP_KERNEL);
235	if (!phase)
236	return;
237
238	phase->hw.init = &init;
239
240	phase->reg = of_iomap(node, 0);
241	if (!phase->reg)
242	goto err_free;
243
244	phase->data = data;
245	phase->lock = &sun4i_a10_mod0_lock;
246
247	if (of_property_read_string(node, "clock-output-names", &init.name))
248	init.name = node->name;
249
250	clk = clk_register(NULL, &phase->hw);
251	if (IS_ERR(clk))
252	goto err_unmap;
253
254	of_clk_add_provider(node, of_clk_src_simple_get, clk);
255
256	return;
257
258	err_unmap:
259	iounmap(phase->reg);
260	err_free:
261	kfree(phase);
262	}
263
264
265	static struct mmc_phase_data mmc_output_clk = {
266	.offset = 8,
267	};
268
269	static struct mmc_phase_data mmc_sample_clk = {
270	.offset = 20,
271	};
272
273	static void __init sun4i_a10_mmc_output_setup(struct device_node *node)
274	{
275	sun4i_a10_mmc_phase_setup(node, &mmc_output_clk);
276	}
277	CLK_OF_DECLARE(sun4i_a10_mmc_output, "allwinner,sun4i-a10-mmc-output-clk", sun4i_a10_mmc_output_setup);
278
279	static void __init sun4i_a10_mmc_sample_setup(struct device_node *node)
280	{
281	sun4i_a10_mmc_phase_setup(node, &mmc_sample_clk);
282	}
283	CLK_OF_DECLARE(sun4i_a10_mmc_sample, "allwinner,sun4i-a10-mmc-sample-clk", sun4i_a10_mmc_sample_setup);