Commit | Line | Data |
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992a56e4 MR |
1 | /* |
2 | * Copyright 2013 Emilio López | |
3 | * | |
4 | * Emilio López <emilio@elopez.com.ar> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
9dfefe8c | 17 | #include <linux/clk.h> |
992a56e4 | 18 | #include <linux/clk-provider.h> |
37e1041f | 19 | #include <linux/of_address.h> |
6ea3953d | 20 | #include <linux/platform_device.h> |
9dfefe8c | 21 | #include <linux/slab.h> |
992a56e4 MR |
22 | |
23 | #include "clk-factors.h" | |
24 | ||
25 | /** | |
35b1fc2c | 26 | * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks |
992a56e4 MR |
27 | * MOD0 rate is calculated as follows |
28 | * rate = (parent_rate >> p) / (m + 1); | |
29 | */ | |
30 | ||
cfa63688 | 31 | static void sun4i_a10_get_mod0_factors(struct factors_request *req) |
992a56e4 MR |
32 | { |
33 | u8 div, calcm, calcp; | |
34 | ||
35 | /* These clocks can only divide, so we will never be able to achieve | |
36 | * frequencies higher than the parent frequency */ | |
cfa63688 CYT |
37 | if (req->rate > req->parent_rate) |
38 | req->rate = req->parent_rate; | |
992a56e4 | 39 | |
cfa63688 | 40 | div = DIV_ROUND_UP(req->parent_rate, req->rate); |
992a56e4 MR |
41 | |
42 | if (div < 16) | |
43 | calcp = 0; | |
44 | else if (div / 2 < 16) | |
45 | calcp = 1; | |
46 | else if (div / 4 < 16) | |
47 | calcp = 2; | |
48 | else | |
49 | calcp = 3; | |
50 | ||
51 | calcm = DIV_ROUND_UP(div, 1 << calcp); | |
52 | ||
cfa63688 CYT |
53 | req->rate = (req->parent_rate >> calcp) / calcm; |
54 | req->m = calcm - 1; | |
55 | req->p = calcp; | |
992a56e4 MR |
56 | } |
57 | ||
58 | /* user manual says "n" but it's really "p" */ | |
b3e919e0 | 59 | static const struct clk_factors_config sun4i_a10_mod0_config = { |
992a56e4 MR |
60 | .mshift = 0, |
61 | .mwidth = 4, | |
62 | .pshift = 16, | |
63 | .pwidth = 2, | |
64 | }; | |
65 | ||
6ea3953d | 66 | static const struct factors_data sun4i_a10_mod0_data = { |
992a56e4 MR |
67 | .enable = 31, |
68 | .mux = 24, | |
e94f8cb3 | 69 | .muxmask = BIT(1) | BIT(0), |
992a56e4 MR |
70 | .table = &sun4i_a10_mod0_config, |
71 | .getter = sun4i_a10_get_mod0_factors, | |
72 | }; | |
73 | ||
74 | static DEFINE_SPINLOCK(sun4i_a10_mod0_lock); | |
75 | ||
76 | static void __init sun4i_a10_mod0_setup(struct device_node *node) | |
77 | { | |
7c74c220 HG |
78 | void __iomem *reg; |
79 | ||
80 | reg = of_iomap(node, 0); | |
81 | if (!reg) { | |
6ea3953d HG |
82 | /* |
83 | * This happens with mod0 clk nodes instantiated through | |
84 | * mfd, as those do not have their resources assigned at | |
85 | * CLK_OF_DECLARE time yet, so do not print an error. | |
86 | */ | |
7c74c220 HG |
87 | return; |
88 | } | |
89 | ||
90 | sunxi_factors_register(node, &sun4i_a10_mod0_data, | |
91 | &sun4i_a10_mod0_lock, reg); | |
992a56e4 | 92 | } |
cb1291c3 RRD |
93 | CLK_OF_DECLARE_DRIVER(sun4i_a10_mod0, "allwinner,sun4i-a10-mod0-clk", |
94 | sun4i_a10_mod0_setup); | |
eaa18f5d | 95 | |
6ea3953d HG |
96 | static int sun4i_a10_mod0_clk_probe(struct platform_device *pdev) |
97 | { | |
98 | struct device_node *np = pdev->dev.of_node; | |
99 | struct resource *r; | |
100 | void __iomem *reg; | |
101 | ||
102 | if (!np) | |
103 | return -ENODEV; | |
104 | ||
105 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
106 | reg = devm_ioremap_resource(&pdev->dev, r); | |
107 | if (IS_ERR(reg)) | |
108 | return PTR_ERR(reg); | |
109 | ||
110 | sunxi_factors_register(np, &sun4i_a10_mod0_data, | |
111 | &sun4i_a10_mod0_lock, reg); | |
112 | return 0; | |
113 | } | |
114 | ||
115 | static const struct of_device_id sun4i_a10_mod0_clk_dt_ids[] = { | |
116 | { .compatible = "allwinner,sun4i-a10-mod0-clk" }, | |
117 | { /* sentinel */ } | |
118 | }; | |
119 | ||
120 | static struct platform_driver sun4i_a10_mod0_clk_driver = { | |
121 | .driver = { | |
122 | .name = "sun4i-a10-mod0-clk", | |
123 | .of_match_table = sun4i_a10_mod0_clk_dt_ids, | |
124 | }, | |
125 | .probe = sun4i_a10_mod0_clk_probe, | |
126 | }; | |
77459a0f | 127 | builtin_platform_driver(sun4i_a10_mod0_clk_driver); |
6ea3953d | 128 | |
61af4d8d CYT |
129 | static const struct factors_data sun9i_a80_mod0_data __initconst = { |
130 | .enable = 31, | |
131 | .mux = 24, | |
132 | .muxmask = BIT(3) | BIT(2) | BIT(1) | BIT(0), | |
133 | .table = &sun4i_a10_mod0_config, | |
134 | .getter = sun4i_a10_get_mod0_factors, | |
135 | }; | |
136 | ||
137 | static void __init sun9i_a80_mod0_setup(struct device_node *node) | |
138 | { | |
139 | void __iomem *reg; | |
140 | ||
141 | reg = of_io_request_and_map(node, 0, of_node_full_name(node)); | |
142 | if (IS_ERR(reg)) { | |
e665f029 RH |
143 | pr_err("Could not get registers for mod0-clk: %pOFn\n", |
144 | node); | |
61af4d8d CYT |
145 | return; |
146 | } | |
147 | ||
148 | sunxi_factors_register(node, &sun9i_a80_mod0_data, | |
149 | &sun4i_a10_mod0_lock, reg); | |
150 | } | |
151 | CLK_OF_DECLARE(sun9i_a80_mod0, "allwinner,sun9i-a80-mod0-clk", sun9i_a80_mod0_setup); | |
152 | ||
eaa18f5d MR |
153 | static DEFINE_SPINLOCK(sun5i_a13_mbus_lock); |
154 | ||
155 | static void __init sun5i_a13_mbus_setup(struct device_node *node) | |
156 | { | |
7c74c220 HG |
157 | void __iomem *reg; |
158 | ||
159 | reg = of_iomap(node, 0); | |
160 | if (!reg) { | |
161 | pr_err("Could not get registers for a13-mbus-clk\n"); | |
162 | return; | |
163 | } | |
164 | ||
eaa18f5d | 165 | /* The MBUS clocks needs to be always enabled */ |
9919d44f SB |
166 | sunxi_factors_register_critical(node, &sun4i_a10_mod0_data, |
167 | &sun5i_a13_mbus_lock, reg); | |
eaa18f5d MR |
168 | } |
169 | CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup); | |
37e1041f | 170 | |
37e1041f MR |
171 | struct mmc_phase { |
172 | struct clk_hw hw; | |
6b0b8ccf | 173 | u8 offset; |
37e1041f | 174 | void __iomem *reg; |
37e1041f MR |
175 | spinlock_t *lock; |
176 | }; | |
177 | ||
178 | #define to_mmc_phase(_hw) container_of(_hw, struct mmc_phase, hw) | |
179 | ||
180 | static int mmc_get_phase(struct clk_hw *hw) | |
181 | { | |
182 | struct clk *mmc, *mmc_parent, *clk = hw->clk; | |
183 | struct mmc_phase *phase = to_mmc_phase(hw); | |
184 | unsigned int mmc_rate, mmc_parent_rate; | |
185 | u16 step, mmc_div; | |
186 | u32 value; | |
187 | u8 delay; | |
188 | ||
189 | value = readl(phase->reg); | |
6b0b8ccf | 190 | delay = (value >> phase->offset) & 0x3; |
37e1041f MR |
191 | |
192 | if (!delay) | |
193 | return 180; | |
194 | ||
195 | /* Get the main MMC clock */ | |
196 | mmc = clk_get_parent(clk); | |
197 | if (!mmc) | |
198 | return -EINVAL; | |
199 | ||
200 | /* And its rate */ | |
201 | mmc_rate = clk_get_rate(mmc); | |
202 | if (!mmc_rate) | |
203 | return -EINVAL; | |
204 | ||
205 | /* Now, get the MMC parent (most likely some PLL) */ | |
206 | mmc_parent = clk_get_parent(mmc); | |
207 | if (!mmc_parent) | |
208 | return -EINVAL; | |
209 | ||
210 | /* And its rate */ | |
211 | mmc_parent_rate = clk_get_rate(mmc_parent); | |
212 | if (!mmc_parent_rate) | |
213 | return -EINVAL; | |
214 | ||
215 | /* Get MMC clock divider */ | |
216 | mmc_div = mmc_parent_rate / mmc_rate; | |
217 | ||
218 | step = DIV_ROUND_CLOSEST(360, mmc_div); | |
219 | return delay * step; | |
220 | } | |
221 | ||
222 | static int mmc_set_phase(struct clk_hw *hw, int degrees) | |
223 | { | |
224 | struct clk *mmc, *mmc_parent, *clk = hw->clk; | |
225 | struct mmc_phase *phase = to_mmc_phase(hw); | |
226 | unsigned int mmc_rate, mmc_parent_rate; | |
227 | unsigned long flags; | |
228 | u32 value; | |
229 | u8 delay; | |
230 | ||
231 | /* Get the main MMC clock */ | |
232 | mmc = clk_get_parent(clk); | |
233 | if (!mmc) | |
234 | return -EINVAL; | |
235 | ||
236 | /* And its rate */ | |
237 | mmc_rate = clk_get_rate(mmc); | |
238 | if (!mmc_rate) | |
239 | return -EINVAL; | |
240 | ||
241 | /* Now, get the MMC parent (most likely some PLL) */ | |
242 | mmc_parent = clk_get_parent(mmc); | |
243 | if (!mmc_parent) | |
244 | return -EINVAL; | |
245 | ||
246 | /* And its rate */ | |
247 | mmc_parent_rate = clk_get_rate(mmc_parent); | |
248 | if (!mmc_parent_rate) | |
249 | return -EINVAL; | |
250 | ||
251 | if (degrees != 180) { | |
252 | u16 step, mmc_div; | |
253 | ||
254 | /* Get MMC clock divider */ | |
255 | mmc_div = mmc_parent_rate / mmc_rate; | |
256 | ||
257 | /* | |
258 | * We can only outphase the clocks by multiple of the | |
259 | * PLL's period. | |
260 | * | |
261 | * Since the MMC clock in only a divider, and the | |
262 | * formula to get the outphasing in degrees is deg = | |
263 | * 360 * delta / period | |
264 | * | |
265 | * If we simplify this formula, we can see that the | |
266 | * only thing that we're concerned about is the number | |
267 | * of period we want to outphase our clock from, and | |
268 | * the divider set by the MMC clock. | |
269 | */ | |
270 | step = DIV_ROUND_CLOSEST(360, mmc_div); | |
271 | delay = DIV_ROUND_CLOSEST(degrees, step); | |
272 | } else { | |
273 | delay = 0; | |
274 | } | |
275 | ||
276 | spin_lock_irqsave(phase->lock, flags); | |
277 | value = readl(phase->reg); | |
6b0b8ccf MR |
278 | value &= ~GENMASK(phase->offset + 3, phase->offset); |
279 | value |= delay << phase->offset; | |
37e1041f MR |
280 | writel(value, phase->reg); |
281 | spin_unlock_irqrestore(phase->lock, flags); | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
286 | static const struct clk_ops mmc_clk_ops = { | |
287 | .get_phase = mmc_get_phase, | |
288 | .set_phase = mmc_set_phase, | |
289 | }; | |
290 | ||
eb378df7 CYT |
291 | /* |
292 | * sunxi_mmc_setup - Common setup function for mmc module clocks | |
293 | * | |
294 | * The only difference between module clocks on different platforms is the | |
295 | * width of the mux register bits and the valid values, which are passed in | |
296 | * through struct factors_data. The phase clocks parts are identical. | |
297 | */ | |
298 | static void __init sunxi_mmc_setup(struct device_node *node, | |
299 | const struct factors_data *data, | |
300 | spinlock_t *lock) | |
6b0b8ccf MR |
301 | { |
302 | struct clk_onecell_data *clk_data; | |
303 | const char *parent; | |
304 | void __iomem *reg; | |
305 | int i; | |
37e1041f | 306 | |
6b0b8ccf MR |
307 | reg = of_io_request_and_map(node, 0, of_node_full_name(node)); |
308 | if (IS_ERR(reg)) { | |
e665f029 | 309 | pr_err("Couldn't map the %pOFn clock registers\n", node); |
6b0b8ccf MR |
310 | return; |
311 | } | |
37e1041f | 312 | |
6b0b8ccf MR |
313 | clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL); |
314 | if (!clk_data) | |
315 | return; | |
37e1041f | 316 | |
6b0b8ccf MR |
317 | clk_data->clks = kcalloc(3, sizeof(*clk_data->clks), GFP_KERNEL); |
318 | if (!clk_data->clks) | |
319 | goto err_free_data; | |
320 | ||
321 | clk_data->clk_num = 3; | |
eb378df7 | 322 | clk_data->clks[0] = sunxi_factors_register(node, data, lock, reg); |
6b0b8ccf MR |
323 | if (!clk_data->clks[0]) |
324 | goto err_free_clks; | |
325 | ||
326 | parent = __clk_get_name(clk_data->clks[0]); | |
327 | ||
328 | for (i = 1; i < 3; i++) { | |
329 | struct clk_init_data init = { | |
330 | .num_parents = 1, | |
331 | .parent_names = &parent, | |
332 | .ops = &mmc_clk_ops, | |
333 | }; | |
334 | struct mmc_phase *phase; | |
335 | ||
336 | phase = kmalloc(sizeof(*phase), GFP_KERNEL); | |
337 | if (!phase) | |
338 | continue; | |
339 | ||
340 | phase->hw.init = &init; | |
341 | phase->reg = reg; | |
eb378df7 | 342 | phase->lock = lock; |
6b0b8ccf MR |
343 | |
344 | if (i == 1) | |
345 | phase->offset = 8; | |
346 | else | |
347 | phase->offset = 20; | |
348 | ||
349 | if (of_property_read_string_index(node, "clock-output-names", | |
350 | i, &init.name)) | |
351 | init.name = node->name; | |
352 | ||
353 | clk_data->clks[i] = clk_register(NULL, &phase->hw); | |
354 | if (IS_ERR(clk_data->clks[i])) { | |
355 | kfree(phase); | |
356 | continue; | |
357 | } | |
358 | } | |
37e1041f | 359 | |
6b0b8ccf | 360 | of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
37e1041f MR |
361 | |
362 | return; | |
363 | ||
6b0b8ccf MR |
364 | err_free_clks: |
365 | kfree(clk_data->clks); | |
366 | err_free_data: | |
367 | kfree(clk_data); | |
37e1041f | 368 | } |
eb378df7 CYT |
369 | |
370 | static DEFINE_SPINLOCK(sun4i_a10_mmc_lock); | |
371 | ||
372 | static void __init sun4i_a10_mmc_setup(struct device_node *node) | |
373 | { | |
374 | sunxi_mmc_setup(node, &sun4i_a10_mod0_data, &sun4i_a10_mmc_lock); | |
375 | } | |
6b0b8ccf | 376 | CLK_OF_DECLARE(sun4i_a10_mmc, "allwinner,sun4i-a10-mmc-clk", sun4i_a10_mmc_setup); |
61af4d8d CYT |
377 | |
378 | static DEFINE_SPINLOCK(sun9i_a80_mmc_lock); | |
379 | ||
380 | static void __init sun9i_a80_mmc_setup(struct device_node *node) | |
381 | { | |
382 | sunxi_mmc_setup(node, &sun9i_a80_mod0_data, &sun9i_a80_mmc_lock); | |
383 | } | |
384 | CLK_OF_DECLARE(sun9i_a80_mmc, "allwinner,sun9i-a80-mmc-clk", sun9i_a80_mmc_setup); |