[linux-2.6-block.git] / drivers / clk / sunxi / clk-mod0.c

/*
 * Copyright 2013 Emilio López
 *
 * Emilio López <emilio@elopez.com.ar>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include "clk-factors.h"

/**
 * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
 * MOD0 rate is calculated as follows
 * rate = (parent_rate >> p) / (m + 1);
 */

static void sun4i_a10_get_mod0_factors(struct factors_request *req)
{
	u8 div, calcm, calcp;

	/* These clocks can only divide, so we will never be able to achieve
	 * frequencies higher than the parent frequency */
	if (req->rate > req->parent_rate)
		req->rate = req->parent_rate;

	div = DIV_ROUND_UP(req->parent_rate, req->rate);

	if (div < 16)
		calcp = 0;
	else if (div / 2 < 16)
		calcp = 1;
	else if (div / 4 < 16)
		calcp = 2;
	else
		calcp = 3;

	calcm = DIV_ROUND_UP(div, 1 << calcp);

	req->rate = (req->parent_rate >> calcp) / calcm;
	req->m = calcm - 1;
	req->p = calcp;
}

/* user manual says "n" but it's really "p" */
static const struct clk_factors_config sun4i_a10_mod0_config = {
	.mshift = 0,
	.mwidth = 4,
	.pshift = 16,
	.pwidth = 2,
};

static const struct factors_data sun4i_a10_mod0_data = {
	.enable = 31,
	.mux = 24,
	.muxmask = BIT(1) | BIT(0),
	.table = &sun4i_a10_mod0_config,
	.getter = sun4i_a10_get_mod0_factors,
};

static DEFINE_SPINLOCK(sun4i_a10_mod0_lock);

static void __init sun4i_a10_mod0_setup(struct device_node *node)
{
	void __iomem *reg;

	reg = of_iomap(node, 0);
	if (!reg) {
		/*
		 * This happens with mod0 clk nodes instantiated through
		 * mfd, as those do not have their resources assigned at
		 * CLK_OF_DECLARE time yet, so do not print an error.
		 */
		return;
	}

	sunxi_factors_register(node, &sun4i_a10_mod0_data,
			       &sun4i_a10_mod0_lock, reg);
}
CLK_OF_DECLARE(sun4i_a10_mod0, "allwinner,sun4i-a10-mod0-clk", sun4i_a10_mod0_setup);

static int sun4i_a10_mod0_clk_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct resource *r;
	void __iomem *reg;

	if (!np)
		return -ENODEV;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	reg = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(reg))
		return PTR_ERR(reg);

	sunxi_factors_register(np, &sun4i_a10_mod0_data,
			       &sun4i_a10_mod0_lock, reg);
	return 0;
}

static const struct of_device_id sun4i_a10_mod0_clk_dt_ids[] = {
	{ .compatible = "allwinner,sun4i-a10-mod0-clk" },
	{ /* sentinel */ }
};

static struct platform_driver sun4i_a10_mod0_clk_driver = {
	.driver = {
		.name = "sun4i-a10-mod0-clk",
		.of_match_table = sun4i_a10_mod0_clk_dt_ids,
	},
	.probe = sun4i_a10_mod0_clk_probe,
};
builtin_platform_driver(sun4i_a10_mod0_clk_driver);

static const struct factors_data sun9i_a80_mod0_data __initconst = {
	.enable = 31,
	.mux = 24,
	.muxmask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
	.table = &sun4i_a10_mod0_config,
	.getter = sun4i_a10_get_mod0_factors,
};

static void __init sun9i_a80_mod0_setup(struct device_node *node)
{
	void __iomem *reg;

	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
	if (IS_ERR(reg)) {
		pr_err("Could not get registers for mod0-clk: %s\n",
		       node->name);
		return;
	}

	sunxi_factors_register(node, &sun9i_a80_mod0_data,
			       &sun4i_a10_mod0_lock, reg);
}
CLK_OF_DECLARE(sun9i_a80_mod0, "allwinner,sun9i-a80-mod0-clk", sun9i_a80_mod0_setup);

static DEFINE_SPINLOCK(sun5i_a13_mbus_lock);

static void __init sun5i_a13_mbus_setup(struct device_node *node)
{
	struct clk *mbus;
	void __iomem *reg;

	reg = of_iomap(node, 0);
	if (!reg) {
		pr_err("Could not get registers for a13-mbus-clk\n");
		return;
	}

	mbus = sunxi_factors_register(node, &sun4i_a10_mod0_data,
				      &sun5i_a13_mbus_lock, reg);

	/* The MBUS clocks needs to be always enabled */
	__clk_get(mbus);
	clk_prepare_enable(mbus);
}
CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup);

struct mmc_phase {
	struct clk_hw		hw;
	u8			offset;
	void __iomem		*reg;
	spinlock_t		*lock;
};

#define to_mmc_phase(_hw) container_of(_hw, struct mmc_phase, hw)

static int mmc_get_phase(struct clk_hw *hw)
{
	struct clk *mmc, *mmc_parent, *clk = hw->clk;
	struct mmc_phase *phase = to_mmc_phase(hw);
	unsigned int mmc_rate, mmc_parent_rate;
	u16 step, mmc_div;
	u32 value;
	u8 delay;

	value = readl(phase->reg);
	delay = (value >> phase->offset) & 0x3;

	if (!delay)
		return 180;

	/* Get the main MMC clock */
	mmc = clk_get_parent(clk);
	if (!mmc)
		return -EINVAL;

	/* And its rate */
	mmc_rate = clk_get_rate(mmc);
	if (!mmc_rate)
		return -EINVAL;

	/* Now, get the MMC parent (most likely some PLL) */
	mmc_parent = clk_get_parent(mmc);
	if (!mmc_parent)
		return -EINVAL;

	/* And its rate */
	mmc_parent_rate = clk_get_rate(mmc_parent);
	if (!mmc_parent_rate)
		return -EINVAL;

	/* Get MMC clock divider */
	mmc_div = mmc_parent_rate / mmc_rate;

	step = DIV_ROUND_CLOSEST(360, mmc_div);
	return delay * step;
}

static int mmc_set_phase(struct clk_hw *hw, int degrees)
{
	struct clk *mmc, *mmc_parent, *clk = hw->clk;
	struct mmc_phase *phase = to_mmc_phase(hw);
	unsigned int mmc_rate, mmc_parent_rate;
	unsigned long flags;
	u32 value;
	u8 delay;

	/* Get the main MMC clock */
	mmc = clk_get_parent(clk);
	if (!mmc)
		return -EINVAL;

	/* And its rate */
	mmc_rate = clk_get_rate(mmc);
	if (!mmc_rate)
		return -EINVAL;

	/* Now, get the MMC parent (most likely some PLL) */
	mmc_parent = clk_get_parent(mmc);
	if (!mmc_parent)
		return -EINVAL;

	/* And its rate */
	mmc_parent_rate = clk_get_rate(mmc_parent);
	if (!mmc_parent_rate)
		return -EINVAL;

	if (degrees != 180) {
		u16 step, mmc_div;

		/* Get MMC clock divider */
		mmc_div = mmc_parent_rate / mmc_rate;

		/*
		 * We can only outphase the clocks by multiple of the
		 * PLL's period.
		 *
		 * Since the MMC clock in only a divider, and the
		 * formula to get the outphasing in degrees is deg =
		 * 360 * delta / period
		 *
		 * If we simplify this formula, we can see that the
		 * only thing that we're concerned about is the number
		 * of period we want to outphase our clock from, and
		 * the divider set by the MMC clock.
		 */
		step = DIV_ROUND_CLOSEST(360, mmc_div);
		delay = DIV_ROUND_CLOSEST(degrees, step);
	} else {
		delay = 0;
	}

	spin_lock_irqsave(phase->lock, flags);
	value = readl(phase->reg);
	value &= ~GENMASK(phase->offset + 3, phase->offset);
	value |= delay << phase->offset;
	writel(value, phase->reg);
	spin_unlock_irqrestore(phase->lock, flags);

	return 0;
}

static const struct clk_ops mmc_clk_ops = {
	.get_phase	= mmc_get_phase,
	.set_phase	= mmc_set_phase,
};

/*
 * sunxi_mmc_setup - Common setup function for mmc module clocks
 *
 * The only difference between module clocks on different platforms is the
 * width of the mux register bits and the valid values, which are passed in
 * through struct factors_data. The phase clocks parts are identical.
 */
static void __init sunxi_mmc_setup(struct device_node *node,
				   const struct factors_data *data,
				   spinlock_t *lock)
{
	struct clk_onecell_data *clk_data;
	const char *parent;
	void __iomem *reg;
	int i;

	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
	if (IS_ERR(reg)) {
		pr_err("Couldn't map the %s clock registers\n", node->name);
		return;
	}

	clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
	if (!clk_data)
		return;

	clk_data->clks = kcalloc(3, sizeof(*clk_data->clks), GFP_KERNEL);
	if (!clk_data->clks)
		goto err_free_data;

	clk_data->clk_num = 3;
	clk_data->clks[0] = sunxi_factors_register(node, data, lock, reg);
	if (!clk_data->clks[0])
		goto err_free_clks;

	parent = __clk_get_name(clk_data->clks[0]);

	for (i = 1; i < 3; i++) {
		struct clk_init_data init = {
			.num_parents	= 1,
			.parent_names	= &parent,
			.ops		= &mmc_clk_ops,
		};
		struct mmc_phase *phase;

		phase = kmalloc(sizeof(*phase), GFP_KERNEL);
		if (!phase)
			continue;

		phase->hw.init = &init;
		phase->reg = reg;
		phase->lock = lock;

		if (i == 1)
			phase->offset = 8;
		else
			phase->offset = 20;

		if (of_property_read_string_index(node, "clock-output-names",
						  i, &init.name))
			init.name = node->name;

		clk_data->clks[i] = clk_register(NULL, &phase->hw);
		if (IS_ERR(clk_data->clks[i])) {
			kfree(phase);
			continue;
		}
	}

	of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

	return;

err_free_clks:
	kfree(clk_data->clks);
err_free_data:
	kfree(clk_data);
}

static DEFINE_SPINLOCK(sun4i_a10_mmc_lock);

static void __init sun4i_a10_mmc_setup(struct device_node *node)
{
	sunxi_mmc_setup(node, &sun4i_a10_mod0_data, &sun4i_a10_mmc_lock);
}
CLK_OF_DECLARE(sun4i_a10_mmc, "allwinner,sun4i-a10-mmc-clk", sun4i_a10_mmc_setup);

static DEFINE_SPINLOCK(sun9i_a80_mmc_lock);

static void __init sun9i_a80_mmc_setup(struct device_node *node)
{
	sunxi_mmc_setup(node, &sun9i_a80_mod0_data, &sun9i_a80_mmc_lock);
}
CLK_OF_DECLARE(sun9i_a80_mmc, "allwinner,sun9i-a80-mmc-clk", sun9i_a80_mmc_setup);
Commit	Line	Data
992a56e4 MR	1	/*
	2	* Copyright 2013 Emilio López
	3	*
	4	* Emilio López <emilio@elopez.com.ar>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16
9dfefe8c	17	#include <linux/clk.h>
b0b6413f	18	#include <linux/clkdev.h>
992a56e4	19	#include <linux/clk-provider.h>
37e1041f	20	#include <linux/of_address.h>
6ea3953d	21	#include <linux/platform_device.h>
9dfefe8c	22	#include <linux/slab.h>
992a56e4 MR	23
	24	#include "clk-factors.h"
	25
	26	/**
	27	* sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
	28	* MOD0 rate is calculated as follows
	29	* rate = (parent_rate >> p) / (m + 1);
	30	*/
	31
cfa63688	32	static void sun4i_a10_get_mod0_factors(struct factors_request *req)
992a56e4 MR	33	{
	34	u8 div, calcm, calcp;
	35
	36	/* These clocks can only divide, so we will never be able to achieve
	37	* frequencies higher than the parent frequency */
cfa63688 CYT	38	if (req->rate > req->parent_rate)
cfa63688 CYT	39	req->rate = req->parent_rate;
992a56e4	40
cfa63688	41	div = DIV_ROUND_UP(req->parent_rate, req->rate);
992a56e4 MR	42
	43	if (div < 16)
	44	calcp = 0;
	45	else if (div / 2 < 16)
	46	calcp = 1;
	47	else if (div / 4 < 16)
	48	calcp = 2;
	49	else
	50	calcp = 3;
	51
	52	calcm = DIV_ROUND_UP(div, 1 << calcp);
	53
cfa63688 CYT	54	req->rate = (req->parent_rate >> calcp) / calcm;
	55	req->m = calcm - 1;
	56	req->p = calcp;
992a56e4 MR	57	}
	58
	59	/* user manual says "n" but it's really "p" */
b3e919e0	60	static const struct clk_factors_config sun4i_a10_mod0_config = {
992a56e4 MR	61	.mshift = 0,
	62	.mwidth = 4,
	63	.pshift = 16,
	64	.pwidth = 2,
	65	};
	66
6ea3953d	67	static const struct factors_data sun4i_a10_mod0_data = {
992a56e4 MR	68	.enable = 31,
992a56e4 MR	69	.mux = 24,
e94f8cb3	70	.muxmask = BIT(1) \| BIT(0),
992a56e4 MR	71	.table = &sun4i_a10_mod0_config,
	72	.getter = sun4i_a10_get_mod0_factors,
	73	};
	74
	75	static DEFINE_SPINLOCK(sun4i_a10_mod0_lock);
	76
	77	static void __init sun4i_a10_mod0_setup(struct device_node *node)
	78	{
7c74c220 HG	79	void __iomem *reg;
	80
	81	reg = of_iomap(node, 0);
	82	if (!reg) {
6ea3953d HG	83	/*
	84	* This happens with mod0 clk nodes instantiated through
	85	* mfd, as those do not have their resources assigned at
	86	* CLK_OF_DECLARE time yet, so do not print an error.
	87	*/
7c74c220 HG	88	return;
	89	}
	90
	91	sunxi_factors_register(node, &sun4i_a10_mod0_data,
	92	&sun4i_a10_mod0_lock, reg);
992a56e4 MR	93	}
992a56e4 MR	94	CLK_OF_DECLARE(sun4i_a10_mod0, "allwinner,sun4i-a10-mod0-clk", sun4i_a10_mod0_setup);
eaa18f5d	95
6ea3953d HG	96	static int sun4i_a10_mod0_clk_probe(struct platform_device *pdev)
	97	{
	98	struct device_node *np = pdev->dev.of_node;
	99	struct resource *r;
	100	void __iomem *reg;
	101
	102	if (!np)
	103	return -ENODEV;
	104
	105	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	106	reg = devm_ioremap_resource(&pdev->dev, r);
	107	if (IS_ERR(reg))
	108	return PTR_ERR(reg);
	109
	110	sunxi_factors_register(np, &sun4i_a10_mod0_data,
	111	&sun4i_a10_mod0_lock, reg);
	112	return 0;
	113	}
	114
	115	static const struct of_device_id sun4i_a10_mod0_clk_dt_ids[] = {
	116	{ .compatible = "allwinner,sun4i-a10-mod0-clk" },
	117	{ /* sentinel */ }
	118	};
	119
	120	static struct platform_driver sun4i_a10_mod0_clk_driver = {
	121	.driver = {
	122	.name = "sun4i-a10-mod0-clk",
	123	.of_match_table = sun4i_a10_mod0_clk_dt_ids,
	124	},
	125	.probe = sun4i_a10_mod0_clk_probe,
	126	};
77459a0f	127	builtin_platform_driver(sun4i_a10_mod0_clk_driver);
6ea3953d	128
61af4d8d CYT	129	static const struct factors_data sun9i_a80_mod0_data __initconst = {
	130	.enable = 31,
	131	.mux = 24,
	132	.muxmask = BIT(3) \| BIT(2) \| BIT(1) \| BIT(0),
	133	.table = &sun4i_a10_mod0_config,
	134	.getter = sun4i_a10_get_mod0_factors,
	135	};
	136
	137	static void __init sun9i_a80_mod0_setup(struct device_node *node)
	138	{
	139	void __iomem *reg;
	140
	141	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
	142	if (IS_ERR(reg)) {
	143	pr_err("Could not get registers for mod0-clk: %s\n",
	144	node->name);
	145	return;
	146	}
	147
	148	sunxi_factors_register(node, &sun9i_a80_mod0_data,
	149	&sun4i_a10_mod0_lock, reg);
	150	}
	151	CLK_OF_DECLARE(sun9i_a80_mod0, "allwinner,sun9i-a80-mod0-clk", sun9i_a80_mod0_setup);
	152
eaa18f5d MR	153	static DEFINE_SPINLOCK(sun5i_a13_mbus_lock);
	154
	155	static void __init sun5i_a13_mbus_setup(struct device_node *node)
	156	{
7c74c220 HG	157	struct clk *mbus;
	158	void __iomem *reg;
	159
	160	reg = of_iomap(node, 0);
	161	if (!reg) {
	162	pr_err("Could not get registers for a13-mbus-clk\n");
	163	return;
	164	}
	165
	166	mbus = sunxi_factors_register(node, &sun4i_a10_mod0_data,
	167	&sun5i_a13_mbus_lock, reg);
eaa18f5d MR	168
	169	/* The MBUS clocks needs to be always enabled */
	170	__clk_get(mbus);
	171	clk_prepare_enable(mbus);
	172	}
	173	CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup);
37e1041f	174
37e1041f MR	175	struct mmc_phase {
37e1041f MR	176	struct clk_hw hw;
6b0b8ccf	177	u8 offset;
37e1041f	178	void __iomem *reg;
37e1041f MR	179	spinlock_t *lock;
	180	};
	181
	182	#define to_mmc_phase(_hw) container_of(_hw, struct mmc_phase, hw)
	183
	184	static int mmc_get_phase(struct clk_hw *hw)
	185	{
	186	struct clk mmc, mmc_parent, *clk = hw->clk;
	187	struct mmc_phase *phase = to_mmc_phase(hw);
	188	unsigned int mmc_rate, mmc_parent_rate;
	189	u16 step, mmc_div;
	190	u32 value;
	191	u8 delay;
	192
	193	value = readl(phase->reg);
6b0b8ccf	194	delay = (value >> phase->offset) & 0x3;
37e1041f MR	195
	196	if (!delay)
	197	return 180;
	198
	199	/* Get the main MMC clock */
	200	mmc = clk_get_parent(clk);
	201	if (!mmc)
	202	return -EINVAL;
	203
	204	/* And its rate */
	205	mmc_rate = clk_get_rate(mmc);
	206	if (!mmc_rate)
	207	return -EINVAL;
	208
	209	/* Now, get the MMC parent (most likely some PLL) */
	210	mmc_parent = clk_get_parent(mmc);
	211	if (!mmc_parent)
	212	return -EINVAL;
	213
	214	/* And its rate */
	215	mmc_parent_rate = clk_get_rate(mmc_parent);
	216	if (!mmc_parent_rate)
	217	return -EINVAL;
	218
	219	/* Get MMC clock divider */
	220	mmc_div = mmc_parent_rate / mmc_rate;
	221
	222	step = DIV_ROUND_CLOSEST(360, mmc_div);
	223	return delay * step;
	224	}
	225
	226	static int mmc_set_phase(struct clk_hw *hw, int degrees)
	227	{
	228	struct clk mmc, mmc_parent, *clk = hw->clk;
	229	struct mmc_phase *phase = to_mmc_phase(hw);
	230	unsigned int mmc_rate, mmc_parent_rate;
	231	unsigned long flags;
	232	u32 value;
	233	u8 delay;
	234
	235	/* Get the main MMC clock */
	236	mmc = clk_get_parent(clk);
	237	if (!mmc)
	238	return -EINVAL;
	239
	240	/* And its rate */
	241	mmc_rate = clk_get_rate(mmc);
	242	if (!mmc_rate)
	243	return -EINVAL;
	244
	245	/* Now, get the MMC parent (most likely some PLL) */
	246	mmc_parent = clk_get_parent(mmc);
	247	if (!mmc_parent)
	248	return -EINVAL;
	249
	250	/* And its rate */
	251	mmc_parent_rate = clk_get_rate(mmc_parent);
	252	if (!mmc_parent_rate)
	253	return -EINVAL;
	254
	255	if (degrees != 180) {
	256	u16 step, mmc_div;
	257
	258	/* Get MMC clock divider */
259	mmc_div = mmc_parent_rate / mmc_rate;
260
261	/*
262	* We can only outphase the clocks by multiple of the
263	* PLL's period.
264	*
265	* Since the MMC clock in only a divider, and the
266	* formula to get the outphasing in degrees is deg =
267	* 360 * delta / period
268	*
269	* If we simplify this formula, we can see that the
270	* only thing that we're concerned about is the number
271	* of period we want to outphase our clock from, and
272	* the divider set by the MMC clock.
273	*/
274	step = DIV_ROUND_CLOSEST(360, mmc_div);
275	delay = DIV_ROUND_CLOSEST(degrees, step);
276	} else {
277	delay = 0;
278	}
279
280	spin_lock_irqsave(phase->lock, flags);
281	value = readl(phase->reg);
6b0b8ccf MR	282	value &= ~GENMASK(phase->offset + 3, phase->offset);
6b0b8ccf MR	283	value \|= delay << phase->offset;
37e1041f MR	284	writel(value, phase->reg);
	285	spin_unlock_irqrestore(phase->lock, flags);
	286
	287	return 0;
	288	}
	289
	290	static const struct clk_ops mmc_clk_ops = {
	291	.get_phase = mmc_get_phase,
	292	.set_phase = mmc_set_phase,
	293	};
	294
eb378df7 CYT	295	/*
	296	* sunxi_mmc_setup - Common setup function for mmc module clocks
	297	*
	298	* The only difference between module clocks on different platforms is the
	299	* width of the mux register bits and the valid values, which are passed in
	300	* through struct factors_data. The phase clocks parts are identical.
	301	*/
	302	static void __init sunxi_mmc_setup(struct device_node *node,
	303	const struct factors_data *data,
	304	spinlock_t *lock)
6b0b8ccf MR	305	{
	306	struct clk_onecell_data *clk_data;
	307	const char *parent;
	308	void __iomem *reg;
	309	int i;
37e1041f	310
6b0b8ccf MR	311	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
	312	if (IS_ERR(reg)) {
	313	pr_err("Couldn't map the %s clock registers\n", node->name);
	314	return;
	315	}
37e1041f	316
6b0b8ccf MR	317	clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
	318	if (!clk_data)
	319	return;
37e1041f	320
6b0b8ccf MR	321	clk_data->clks = kcalloc(3, sizeof(*clk_data->clks), GFP_KERNEL);
	322	if (!clk_data->clks)
	323	goto err_free_data;
	324
	325	clk_data->clk_num = 3;
eb378df7	326	clk_data->clks[0] = sunxi_factors_register(node, data, lock, reg);
6b0b8ccf MR	327	if (!clk_data->clks[0])
	328	goto err_free_clks;
	329
	330	parent = __clk_get_name(clk_data->clks[0]);
	331
	332	for (i = 1; i < 3; i++) {
	333	struct clk_init_data init = {
	334	.num_parents = 1,
	335	.parent_names = &parent,
	336	.ops = &mmc_clk_ops,
	337	};
	338	struct mmc_phase *phase;
	339
	340	phase = kmalloc(sizeof(*phase), GFP_KERNEL);
	341	if (!phase)
	342	continue;
	343
	344	phase->hw.init = &init;
	345	phase->reg = reg;
eb378df7	346	phase->lock = lock;
6b0b8ccf MR	347
	348	if (i == 1)
	349	phase->offset = 8;
	350	else
	351	phase->offset = 20;
	352
	353	if (of_property_read_string_index(node, "clock-output-names",
	354	i, &init.name))
	355	init.name = node->name;
	356
	357	clk_data->clks[i] = clk_register(NULL, &phase->hw);
	358	if (IS_ERR(clk_data->clks[i])) {
	359	kfree(phase);
	360	continue;
	361	}
	362	}
37e1041f	363
6b0b8ccf	364	of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
37e1041f MR	365
	366	return;
	367
6b0b8ccf MR	368	err_free_clks:
	369	kfree(clk_data->clks);
	370	err_free_data:
	371	kfree(clk_data);
37e1041f	372	}
eb378df7 CYT	373
	374	static DEFINE_SPINLOCK(sun4i_a10_mmc_lock);
	375
	376	static void __init sun4i_a10_mmc_setup(struct device_node *node)
	377	{
	378	sunxi_mmc_setup(node, &sun4i_a10_mod0_data, &sun4i_a10_mmc_lock);
	379	}
6b0b8ccf	380	CLK_OF_DECLARE(sun4i_a10_mmc, "allwinner,sun4i-a10-mmc-clk", sun4i_a10_mmc_setup);
61af4d8d CYT	381
	382	static DEFINE_SPINLOCK(sun9i_a80_mmc_lock);
	383
	384	static void __init sun9i_a80_mmc_setup(struct device_node *node)
	385	{
	386	sunxi_mmc_setup(node, &sun9i_a80_mod0_data, &sun9i_a80_mmc_lock);
	387	}
	388	CLK_OF_DECLARE(sun9i_a80_mmc, "allwinner,sun9i-a80-mmc-clk", sun9i_a80_mmc_setup);