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b1165170 GF |
1 | /* |
2 | * clk-flexgen.c | |
3 | * | |
4 | * Copyright (C) ST-Microelectronics SA 2013 | |
5 | * Author: Maxime Coquelin <maxime.coquelin@st.com> for ST-Microelectronics. | |
6 | * License terms: GNU General Public License (GPL), version 2 */ | |
7 | ||
d5f728ac | 8 | #include <linux/clk.h> |
b1165170 GF |
9 | #include <linux/clk-provider.h> |
10 | #include <linux/module.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/err.h> | |
14 | #include <linux/string.h> | |
15 | #include <linux/of.h> | |
16 | #include <linux/of_address.h> | |
17 | ||
18 | struct flexgen { | |
19 | struct clk_hw hw; | |
20 | ||
21 | /* Crossbar */ | |
22 | struct clk_mux mux; | |
23 | /* Pre-divisor's gate */ | |
24 | struct clk_gate pgate; | |
25 | /* Pre-divisor */ | |
26 | struct clk_divider pdiv; | |
27 | /* Final divisor's gate */ | |
28 | struct clk_gate fgate; | |
29 | /* Final divisor */ | |
30 | struct clk_divider fdiv; | |
31 | }; | |
32 | ||
33 | #define to_flexgen(_hw) container_of(_hw, struct flexgen, hw) | |
34 | ||
35 | static int flexgen_enable(struct clk_hw *hw) | |
36 | { | |
37 | struct flexgen *flexgen = to_flexgen(hw); | |
38 | struct clk_hw *pgate_hw = &flexgen->pgate.hw; | |
39 | struct clk_hw *fgate_hw = &flexgen->fgate.hw; | |
40 | ||
4e907ef6 JMC |
41 | __clk_hw_set_clk(pgate_hw, hw); |
42 | __clk_hw_set_clk(fgate_hw, hw); | |
b1165170 GF |
43 | |
44 | clk_gate_ops.enable(pgate_hw); | |
45 | ||
46 | clk_gate_ops.enable(fgate_hw); | |
47 | ||
836ee0f7 | 48 | pr_debug("%s: flexgen output enabled\n", clk_hw_get_name(hw)); |
b1165170 GF |
49 | return 0; |
50 | } | |
51 | ||
52 | static void flexgen_disable(struct clk_hw *hw) | |
53 | { | |
54 | struct flexgen *flexgen = to_flexgen(hw); | |
55 | struct clk_hw *fgate_hw = &flexgen->fgate.hw; | |
56 | ||
57 | /* disable only the final gate */ | |
4e907ef6 | 58 | __clk_hw_set_clk(fgate_hw, hw); |
b1165170 GF |
59 | |
60 | clk_gate_ops.disable(fgate_hw); | |
61 | ||
836ee0f7 | 62 | pr_debug("%s: flexgen output disabled\n", clk_hw_get_name(hw)); |
b1165170 GF |
63 | } |
64 | ||
65 | static int flexgen_is_enabled(struct clk_hw *hw) | |
66 | { | |
67 | struct flexgen *flexgen = to_flexgen(hw); | |
68 | struct clk_hw *fgate_hw = &flexgen->fgate.hw; | |
69 | ||
4e907ef6 | 70 | __clk_hw_set_clk(fgate_hw, hw); |
b1165170 GF |
71 | |
72 | if (!clk_gate_ops.is_enabled(fgate_hw)) | |
73 | return 0; | |
74 | ||
75 | return 1; | |
76 | } | |
77 | ||
78 | static u8 flexgen_get_parent(struct clk_hw *hw) | |
79 | { | |
80 | struct flexgen *flexgen = to_flexgen(hw); | |
81 | struct clk_hw *mux_hw = &flexgen->mux.hw; | |
82 | ||
4e907ef6 | 83 | __clk_hw_set_clk(mux_hw, hw); |
b1165170 GF |
84 | |
85 | return clk_mux_ops.get_parent(mux_hw); | |
86 | } | |
87 | ||
88 | static int flexgen_set_parent(struct clk_hw *hw, u8 index) | |
89 | { | |
90 | struct flexgen *flexgen = to_flexgen(hw); | |
91 | struct clk_hw *mux_hw = &flexgen->mux.hw; | |
92 | ||
4e907ef6 | 93 | __clk_hw_set_clk(mux_hw, hw); |
b1165170 GF |
94 | |
95 | return clk_mux_ops.set_parent(mux_hw, index); | |
96 | } | |
97 | ||
98 | static inline unsigned long | |
99 | clk_best_div(unsigned long parent_rate, unsigned long rate) | |
100 | { | |
101 | return parent_rate / rate + ((rate > (2*(parent_rate % rate))) ? 0 : 1); | |
102 | } | |
103 | ||
104 | static long flexgen_round_rate(struct clk_hw *hw, unsigned long rate, | |
105 | unsigned long *prate) | |
106 | { | |
107 | unsigned long div; | |
108 | ||
109 | /* Round div according to exact prate and wished rate */ | |
110 | div = clk_best_div(*prate, rate); | |
111 | ||
98d8a60e | 112 | if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { |
b1165170 GF |
113 | *prate = rate * div; |
114 | return rate; | |
115 | } | |
116 | ||
117 | return *prate / div; | |
118 | } | |
119 | ||
8e6dd77c | 120 | static unsigned long flexgen_recalc_rate(struct clk_hw *hw, |
b1165170 GF |
121 | unsigned long parent_rate) |
122 | { | |
123 | struct flexgen *flexgen = to_flexgen(hw); | |
124 | struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; | |
125 | struct clk_hw *fdiv_hw = &flexgen->fdiv.hw; | |
126 | unsigned long mid_rate; | |
127 | ||
4e907ef6 JMC |
128 | __clk_hw_set_clk(pdiv_hw, hw); |
129 | __clk_hw_set_clk(fdiv_hw, hw); | |
b1165170 GF |
130 | |
131 | mid_rate = clk_divider_ops.recalc_rate(pdiv_hw, parent_rate); | |
132 | ||
133 | return clk_divider_ops.recalc_rate(fdiv_hw, mid_rate); | |
134 | } | |
135 | ||
136 | static int flexgen_set_rate(struct clk_hw *hw, unsigned long rate, | |
137 | unsigned long parent_rate) | |
138 | { | |
139 | struct flexgen *flexgen = to_flexgen(hw); | |
140 | struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; | |
141 | struct clk_hw *fdiv_hw = &flexgen->fdiv.hw; | |
edc30077 | 142 | unsigned long div = 0; |
b1165170 GF |
143 | int ret = 0; |
144 | ||
4e907ef6 JMC |
145 | __clk_hw_set_clk(pdiv_hw, hw); |
146 | __clk_hw_set_clk(fdiv_hw, hw); | |
b1165170 | 147 | |
edc30077 | 148 | div = clk_best_div(parent_rate, rate); |
b1165170 | 149 | |
edc30077 PG |
150 | /* |
151 | * pdiv is mainly targeted for low freq results, while fdiv | |
152 | * should be used for div <= 64. The other way round can | |
153 | * lead to 'duty cycle' issues. | |
154 | */ | |
155 | ||
156 | if (div <= 64) { | |
157 | clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate); | |
158 | ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div); | |
159 | } else { | |
160 | clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate); | |
161 | ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div); | |
162 | } | |
b1165170 GF |
163 | |
164 | return ret; | |
165 | } | |
166 | ||
167 | static const struct clk_ops flexgen_ops = { | |
168 | .enable = flexgen_enable, | |
169 | .disable = flexgen_disable, | |
170 | .is_enabled = flexgen_is_enabled, | |
171 | .get_parent = flexgen_get_parent, | |
172 | .set_parent = flexgen_set_parent, | |
173 | .round_rate = flexgen_round_rate, | |
174 | .recalc_rate = flexgen_recalc_rate, | |
175 | .set_rate = flexgen_set_rate, | |
176 | }; | |
177 | ||
8e6dd77c | 178 | static struct clk *clk_register_flexgen(const char *name, |
b1165170 GF |
179 | const char **parent_names, u8 num_parents, |
180 | void __iomem *reg, spinlock_t *lock, u32 idx, | |
181 | unsigned long flexgen_flags) { | |
182 | struct flexgen *fgxbar; | |
183 | struct clk *clk; | |
184 | struct clk_init_data init; | |
185 | u32 xbar_shift; | |
186 | void __iomem *xbar_reg, *fdiv_reg; | |
187 | ||
188 | fgxbar = kzalloc(sizeof(struct flexgen), GFP_KERNEL); | |
189 | if (!fgxbar) | |
190 | return ERR_PTR(-ENOMEM); | |
191 | ||
192 | init.name = name; | |
193 | init.ops = &flexgen_ops; | |
18fee453 | 194 | init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE | flexgen_flags; |
b1165170 GF |
195 | init.parent_names = parent_names; |
196 | init.num_parents = num_parents; | |
197 | ||
198 | xbar_reg = reg + 0x18 + (idx & ~0x3); | |
199 | xbar_shift = (idx % 4) * 0x8; | |
200 | fdiv_reg = reg + 0x164 + idx * 4; | |
201 | ||
202 | /* Crossbar element config */ | |
203 | fgxbar->mux.lock = lock; | |
204 | fgxbar->mux.mask = BIT(6) - 1; | |
205 | fgxbar->mux.reg = xbar_reg; | |
206 | fgxbar->mux.shift = xbar_shift; | |
207 | fgxbar->mux.table = NULL; | |
208 | ||
209 | ||
210 | /* Pre-divider's gate config (in xbar register)*/ | |
211 | fgxbar->pgate.lock = lock; | |
212 | fgxbar->pgate.reg = xbar_reg; | |
213 | fgxbar->pgate.bit_idx = xbar_shift + 6; | |
214 | ||
215 | /* Pre-divider config */ | |
216 | fgxbar->pdiv.lock = lock; | |
217 | fgxbar->pdiv.reg = reg + 0x58 + idx * 4; | |
218 | fgxbar->pdiv.width = 10; | |
219 | ||
220 | /* Final divider's gate config */ | |
221 | fgxbar->fgate.lock = lock; | |
222 | fgxbar->fgate.reg = fdiv_reg; | |
223 | fgxbar->fgate.bit_idx = 6; | |
224 | ||
225 | /* Final divider config */ | |
226 | fgxbar->fdiv.lock = lock; | |
227 | fgxbar->fdiv.reg = fdiv_reg; | |
228 | fgxbar->fdiv.width = 6; | |
229 | ||
230 | fgxbar->hw.init = &init; | |
231 | ||
232 | clk = clk_register(NULL, &fgxbar->hw); | |
233 | if (IS_ERR(clk)) | |
234 | kfree(fgxbar); | |
235 | else | |
236 | pr_debug("%s: parent %s rate %u\n", | |
237 | __clk_get_name(clk), | |
238 | __clk_get_name(clk_get_parent(clk)), | |
239 | (unsigned int)clk_get_rate(clk)); | |
240 | return clk; | |
241 | } | |
242 | ||
243 | static const char ** __init flexgen_get_parents(struct device_node *np, | |
244 | int *num_parents) | |
245 | { | |
246 | const char **parents; | |
caeb057c | 247 | unsigned int nparents; |
b1165170 | 248 | |
0a65239c | 249 | nparents = of_clk_get_parent_count(np); |
caeb057c | 250 | if (WARN_ON(!nparents)) |
b1165170 GF |
251 | return NULL; |
252 | ||
253 | parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL); | |
254 | if (!parents) | |
255 | return NULL; | |
256 | ||
0b4e7f08 | 257 | *num_parents = of_clk_parent_fill(np, parents, nparents); |
b1165170 | 258 | |
b1165170 GF |
259 | return parents; |
260 | } | |
261 | ||
8e6dd77c | 262 | static void __init st_of_flexgen_setup(struct device_node *np) |
b1165170 GF |
263 | { |
264 | struct device_node *pnode; | |
265 | void __iomem *reg; | |
266 | struct clk_onecell_data *clk_data; | |
267 | const char **parents; | |
268 | int num_parents, i; | |
269 | spinlock_t *rlock = NULL; | |
270 | unsigned long flex_flags = 0; | |
a1c22a4b | 271 | int ret; |
b1165170 GF |
272 | |
273 | pnode = of_get_parent(np); | |
274 | if (!pnode) | |
275 | return; | |
276 | ||
277 | reg = of_iomap(pnode, 0); | |
278 | if (!reg) | |
279 | return; | |
280 | ||
281 | parents = flexgen_get_parents(np, &num_parents); | |
282 | if (!parents) | |
283 | return; | |
284 | ||
285 | clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); | |
286 | if (!clk_data) | |
287 | goto err; | |
288 | ||
a1c22a4b AH |
289 | ret = of_property_count_strings(np, "clock-output-names"); |
290 | if (ret <= 0) { | |
b1165170 GF |
291 | pr_err("%s: Failed to get number of output clocks (%d)", |
292 | __func__, clk_data->clk_num); | |
293 | goto err; | |
294 | } | |
a1c22a4b | 295 | clk_data->clk_num = ret; |
b1165170 GF |
296 | |
297 | clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *), | |
298 | GFP_KERNEL); | |
299 | if (!clk_data->clks) | |
300 | goto err; | |
301 | ||
302 | rlock = kzalloc(sizeof(spinlock_t), GFP_KERNEL); | |
303 | if (!rlock) | |
304 | goto err; | |
305 | ||
0f4f2afd GC |
306 | spin_lock_init(rlock); |
307 | ||
b1165170 GF |
308 | for (i = 0; i < clk_data->clk_num; i++) { |
309 | struct clk *clk; | |
310 | const char *clk_name; | |
311 | ||
312 | if (of_property_read_string_index(np, "clock-output-names", | |
313 | i, &clk_name)) { | |
314 | break; | |
315 | } | |
316 | ||
317 | /* | |
318 | * If we read an empty clock name then the output is unused | |
319 | */ | |
320 | if (*clk_name == '\0') | |
321 | continue; | |
322 | ||
323 | clk = clk_register_flexgen(clk_name, parents, num_parents, | |
324 | reg, rlock, i, flex_flags); | |
325 | ||
326 | if (IS_ERR(clk)) | |
327 | goto err; | |
328 | ||
329 | clk_data->clks[i] = clk; | |
330 | } | |
331 | ||
332 | kfree(parents); | |
333 | of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); | |
334 | ||
335 | return; | |
336 | ||
337 | err: | |
338 | if (clk_data) | |
339 | kfree(clk_data->clks); | |
340 | kfree(clk_data); | |
341 | kfree(parents); | |
342 | kfree(rlock); | |
343 | } | |
344 | CLK_OF_DECLARE(flexgen, "st,flexgen", st_of_flexgen_setup); |