[linux-2.6-block.git] / drivers / clk / spear / spear6xx_clock.c

/*
 * SPEAr6xx machines clock framework source file
 *
 * Copyright (C) 2012 ST Microelectronics
 * Viresh Kumar <vireshk@kernel.org>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/io.h>
#include <linux/spinlock_types.h>
#include "clk.h"

static DEFINE_SPINLOCK(_lock);

#define PLL1_CTR			(misc_base + 0x008)
#define PLL1_FRQ			(misc_base + 0x00C)
#define PLL2_CTR			(misc_base + 0x014)
#define PLL2_FRQ			(misc_base + 0x018)
#define PLL_CLK_CFG			(misc_base + 0x020)
	/* PLL_CLK_CFG register masks */
	#define MCTR_CLK_SHIFT		28
	#define MCTR_CLK_MASK		3

#define CORE_CLK_CFG			(misc_base + 0x024)
	/* CORE CLK CFG register masks */
	#define HCLK_RATIO_SHIFT	10
	#define HCLK_RATIO_MASK		2
	#define PCLK_RATIO_SHIFT	8
	#define PCLK_RATIO_MASK		2

#define PERIP_CLK_CFG			(misc_base + 0x028)
	/* PERIP_CLK_CFG register masks */
	#define CLCD_CLK_SHIFT		2
	#define CLCD_CLK_MASK		2
	#define UART_CLK_SHIFT		4
	#define UART_CLK_MASK		1
	#define FIRDA_CLK_SHIFT		5
	#define FIRDA_CLK_MASK		2
	#define GPT0_CLK_SHIFT		8
	#define GPT1_CLK_SHIFT		10
	#define GPT2_CLK_SHIFT		11
	#define GPT3_CLK_SHIFT		12
	#define GPT_CLK_MASK		1

#define PERIP1_CLK_ENB			(misc_base + 0x02C)
	/* PERIP1_CLK_ENB register masks */
	#define UART0_CLK_ENB		3
	#define UART1_CLK_ENB		4
	#define SSP0_CLK_ENB		5
	#define SSP1_CLK_ENB		6
	#define I2C_CLK_ENB		7
	#define JPEG_CLK_ENB		8
	#define FSMC_CLK_ENB		9
	#define FIRDA_CLK_ENB		10
	#define GPT2_CLK_ENB		11
	#define GPT3_CLK_ENB		12
	#define GPIO2_CLK_ENB		13
	#define SSP2_CLK_ENB		14
	#define ADC_CLK_ENB		15
	#define GPT1_CLK_ENB		11
	#define RTC_CLK_ENB		17
	#define GPIO1_CLK_ENB		18
	#define DMA_CLK_ENB		19
	#define SMI_CLK_ENB		21
	#define CLCD_CLK_ENB		22
	#define GMAC_CLK_ENB		23
	#define USBD_CLK_ENB		24
	#define USBH0_CLK_ENB		25
	#define USBH1_CLK_ENB		26

#define PRSC0_CLK_CFG			(misc_base + 0x044)
#define PRSC1_CLK_CFG			(misc_base + 0x048)
#define PRSC2_CLK_CFG			(misc_base + 0x04C)

#define CLCD_CLK_SYNT			(misc_base + 0x05C)
#define FIRDA_CLK_SYNT			(misc_base + 0x060)
#define UART_CLK_SYNT			(misc_base + 0x064)

/* vco rate configuration table, in ascending order of rates */
static struct pll_rate_tbl pll_rtbl[] = {
	{.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */
	{.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */
	{.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */
};

/* aux rate configuration table, in ascending order of rates */
static struct aux_rate_tbl aux_rtbl[] = {
	/* For PLL1 = 332 MHz */
	{.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
	{.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
	{.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
	{.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
};

static const char *clcd_parents[] = { "pll3_clk", "clcd_syn_gclk", };
static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", };
static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", };
static const char *gpt0_1_parents[] = { "pll3_clk", "gpt0_1_syn_clk", };
static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
static const char *gpt3_parents[] = { "pll3_clk", "gpt3_syn_clk", };
static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
	"pll2_clk", };

/* gpt rate configuration table, in ascending order of rates */
static struct gpt_rate_tbl gpt_rtbl[] = {
	/* For pll1 = 332 MHz */
	{.mscale = 4, .nscale = 0}, /* 41.5 MHz */
	{.mscale = 2, .nscale = 0}, /* 55.3 MHz */
	{.mscale = 1, .nscale = 0}, /* 83 MHz */
};

void __init spear6xx_clk_init(void __iomem *misc_base)
{
	struct clk *clk, *clk1;

	clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
			32000);
	clk_register_clkdev(clk, "osc_32k_clk", NULL);

	clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, CLK_IS_ROOT,
			30000000);
	clk_register_clkdev(clk, "osc_30m_clk", NULL);

	/* clock derived from 32 KHz osc clk */
	clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0,
			PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "rtc-spear");

	/* clock derived from 30 MHz osc clk */
	clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
			48000000);
	clk_register_clkdev(clk, "pll3_clk", NULL);

	clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
			0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
			&_lock, &clk1, NULL);
	clk_register_clkdev(clk, "vco1_clk", NULL);
	clk_register_clkdev(clk1, "pll1_clk", NULL);

	clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk",
			0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
			&_lock, &clk1, NULL);
	clk_register_clkdev(clk, "vco2_clk", NULL);
	clk_register_clkdev(clk1, "pll2_clk", NULL);

	clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
			1);
	clk_register_clkdev(clk, NULL, "wdt");

	/* clock derived from pll1 clk */
	clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
			CLK_SET_RATE_PARENT, 1, 1);
	clk_register_clkdev(clk, "cpu_clk", NULL);

	clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
			CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
			HCLK_RATIO_MASK, 0, &_lock);
	clk_register_clkdev(clk, "ahb_clk", NULL);

	clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
			UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
			&_lock, &clk1);
	clk_register_clkdev(clk, "uart_syn_clk", NULL);
	clk_register_clkdev(clk1, "uart_syn_gclk", NULL);

	clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
			ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
			PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
			&_lock);
	clk_register_clkdev(clk, "uart_mclk", NULL);

	clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
			UART0_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "d0000000.serial");

	clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB,
			UART1_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "d0080000.serial");

	clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk",
			0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
			&_lock, &clk1);
	clk_register_clkdev(clk, "firda_syn_clk", NULL);
	clk_register_clkdev(clk1, "firda_syn_gclk", NULL);

	clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
			ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT,
			PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
			&_lock);
	clk_register_clkdev(clk, "firda_mclk", NULL);

	clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
			PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "firda");

	clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk",
			0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
			&_lock, &clk1);
	clk_register_clkdev(clk, "clcd_syn_clk", NULL);
	clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);

	clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
			ARRAY_SIZE(clcd_parents), CLK_SET_RATE_NO_REPARENT,
			PERIP_CLK_CFG, CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0,
			&_lock);
	clk_register_clkdev(clk, "clcd_mclk", NULL);

	clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
			PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "clcd");

	/* gpt clocks */
	clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
			gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
	clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);

	clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
			ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
			PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
	clk_register_clkdev(clk, NULL, "gpt0");

	clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
			ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
			PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
	clk_register_clkdev(clk, "gpt1_mclk", NULL);

	clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
			PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "gpt1");

	clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
			gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
	clk_register_clkdev(clk, "gpt2_syn_clk", NULL);

	clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
			ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_NO_REPARENT,
			PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
	clk_register_clkdev(clk, "gpt2_mclk", NULL);

	clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
			PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "gpt2");

	clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
			gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
	clk_register_clkdev(clk, "gpt3_syn_clk", NULL);

	clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
			ARRAY_SIZE(gpt3_parents), CLK_SET_RATE_NO_REPARENT,
			PERIP_CLK_CFG, GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
	clk_register_clkdev(clk, "gpt3_mclk", NULL);

	clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
			PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "gpt3");

	/* clock derived from pll3 clk */
	clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0,
			PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "e1800000.ehci");
	clk_register_clkdev(clk, NULL, "e1900000.ohci");

	clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0,
			PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "e2000000.ehci");
	clk_register_clkdev(clk, NULL, "e2100000.ohci");

	clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
			USBD_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "designware_udc");

	/* clock derived from ahb clk */
	clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
			1);
	clk_register_clkdev(clk, "ahbmult2_clk", NULL);

	clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
			ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
			PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
	clk_register_clkdev(clk, "ddr_clk", NULL);

	clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
			CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
			PCLK_RATIO_MASK, 0, &_lock);
	clk_register_clkdev(clk, "apb_clk", NULL);

	clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
			DMA_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "fc400000.dma");

	clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
			FSMC_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "d1800000.flash");

	clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
			GMAC_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "e0800000.ethernet");

	clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
			I2C_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "d0200000.i2c");

	clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
			JPEG_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "jpeg");

	clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
			SMI_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "fc000000.flash");

	/* clock derived from apb clk */
	clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
			ADC_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "adc");

	clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1);
	clk_register_clkdev(clk, NULL, "f0100000.gpio");

	clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
			GPIO1_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "fc980000.gpio");

	clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
			GPIO2_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "d8100000.gpio");

	clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
			SSP0_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "ssp-pl022.0");

	clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
			SSP1_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "ssp-pl022.1");

	clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
			SSP2_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "ssp-pl022.2");
}
Commit	Line	Data
5df33a62 VK	1	/*
	2	* SPEAr6xx machines clock framework source file
	3	*
	4	* Copyright (C) 2012 ST Microelectronics
da89947b	5	* Viresh Kumar <vireshk@kernel.org>
5df33a62 VK	6	*
	7	* This file is licensed under the terms of the GNU General Public
	8	* License version 2. This program is licensed "as is" without any
	9	* warranty of any kind, whether express or implied.
	10	*/
	11
	12	#include <linux/clk.h>
	13	#include <linux/clkdev.h>
	14	#include <linux/io.h>
	15	#include <linux/spinlock_types.h>
5df33a62 VK	16	#include "clk.h"
	17
	18	static DEFINE_SPINLOCK(_lock);
	19
d9909ebe AB	20	#define PLL1_CTR (misc_base + 0x008)
	21	#define PLL1_FRQ (misc_base + 0x00C)
	22	#define PLL2_CTR (misc_base + 0x014)
	23	#define PLL2_FRQ (misc_base + 0x018)
	24	#define PLL_CLK_CFG (misc_base + 0x020)
5df33a62 VK	25	/* PLL_CLK_CFG register masks */
	26	#define MCTR_CLK_SHIFT 28
	27	#define MCTR_CLK_MASK 3
	28
d9909ebe	29	#define CORE_CLK_CFG (misc_base + 0x024)
5df33a62 VK	30	/* CORE CLK CFG register masks */
	31	#define HCLK_RATIO_SHIFT 10
	32	#define HCLK_RATIO_MASK 2
	33	#define PCLK_RATIO_SHIFT 8
	34	#define PCLK_RATIO_MASK 2
	35
d9909ebe	36	#define PERIP_CLK_CFG (misc_base + 0x028)
5df33a62 VK	37	/* PERIP_CLK_CFG register masks */
	38	#define CLCD_CLK_SHIFT 2
	39	#define CLCD_CLK_MASK 2
	40	#define UART_CLK_SHIFT 4
	41	#define UART_CLK_MASK 1
	42	#define FIRDA_CLK_SHIFT 5
	43	#define FIRDA_CLK_MASK 2
	44	#define GPT0_CLK_SHIFT 8
	45	#define GPT1_CLK_SHIFT 10
	46	#define GPT2_CLK_SHIFT 11
	47	#define GPT3_CLK_SHIFT 12
	48	#define GPT_CLK_MASK 1
	49
d9909ebe	50	#define PERIP1_CLK_ENB (misc_base + 0x02C)
5df33a62 VK	51	/* PERIP1_CLK_ENB register masks */
	52	#define UART0_CLK_ENB 3
	53	#define UART1_CLK_ENB 4
	54	#define SSP0_CLK_ENB 5
	55	#define SSP1_CLK_ENB 6
	56	#define I2C_CLK_ENB 7
	57	#define JPEG_CLK_ENB 8
	58	#define FSMC_CLK_ENB 9
	59	#define FIRDA_CLK_ENB 10
	60	#define GPT2_CLK_ENB 11
	61	#define GPT3_CLK_ENB 12
	62	#define GPIO2_CLK_ENB 13
	63	#define SSP2_CLK_ENB 14
	64	#define ADC_CLK_ENB 15
	65	#define GPT1_CLK_ENB 11
	66	#define RTC_CLK_ENB 17
	67	#define GPIO1_CLK_ENB 18
	68	#define DMA_CLK_ENB 19
	69	#define SMI_CLK_ENB 21
	70	#define CLCD_CLK_ENB 22
	71	#define GMAC_CLK_ENB 23
	72	#define USBD_CLK_ENB 24
	73	#define USBH0_CLK_ENB 25
	74	#define USBH1_CLK_ENB 26
	75
d9909ebe AB	76	#define PRSC0_CLK_CFG (misc_base + 0x044)
	77	#define PRSC1_CLK_CFG (misc_base + 0x048)
	78	#define PRSC2_CLK_CFG (misc_base + 0x04C)
5df33a62	79
d9909ebe AB	80	#define CLCD_CLK_SYNT (misc_base + 0x05C)
	81	#define FIRDA_CLK_SYNT (misc_base + 0x060)
	82	#define UART_CLK_SYNT (misc_base + 0x064)
5df33a62 VK	83
	84	/* vco rate configuration table, in ascending order of rates */
	85	static struct pll_rate_tbl pll_rtbl[] = {
	86	{.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */
	87	{.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */
	88	{.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */
	89	};
	90
	91	/* aux rate configuration table, in ascending order of rates */
	92	static struct aux_rate_tbl aux_rtbl[] = {
	93	/* For PLL1 = 332 MHz */
ef0fd0a2	94	{.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
5df33a62 VK	95	{.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
	96	{.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
	97	{.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
	98	};
	99
a8f4bf0e VKS	100	static const char *clcd_parents[] = { "pll3_clk", "clcd_syn_gclk", };
	101	static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", };
	102	static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", };
	103	static const char *gpt0_1_parents[] = { "pll3_clk", "gpt0_1_syn_clk", };
	104	static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
	105	static const char *gpt3_parents[] = { "pll3_clk", "gpt3_syn_clk", };
5df33a62 VK	106	static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
	107	"pll2_clk", };
	108
	109	/* gpt rate configuration table, in ascending order of rates */
	110	static struct gpt_rate_tbl gpt_rtbl[] = {
	111	/* For pll1 = 332 MHz */
	112	{.mscale = 4, .nscale = 0}, /* 41.5 MHz */
	113	{.mscale = 2, .nscale = 0}, /* 55.3 MHz */
	114	{.mscale = 1, .nscale = 0}, /* 83 MHz */
	115	};
	116
d9909ebe	117	void __init spear6xx_clk_init(void __iomem *misc_base)
5df33a62 VK	118	{
	119	struct clk clk, clk1;
	120
5df33a62 VK	121	clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
	122	32000);
	123	clk_register_clkdev(clk, "osc_32k_clk", NULL);
	124
	125	clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, CLK_IS_ROOT,
	126	30000000);
	127	clk_register_clkdev(clk, "osc_30m_clk", NULL);
	128
	129	/* clock derived from 32 KHz osc clk */
	130	clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0,
	131	PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
	132	clk_register_clkdev(clk, NULL, "rtc-spear");
	133
	134	/* clock derived from 30 MHz osc clk */
a8f4bf0e	135	clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
5df33a62	136	48000000);
a8f4bf0e	137	clk_register_clkdev(clk, "pll3_clk", NULL);
5df33a62 VK	138
	139	clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
	140	0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
	141	&_lock, &clk1, NULL);
	142	clk_register_clkdev(clk, "vco1_clk", NULL);
	143	clk_register_clkdev(clk1, "pll1_clk", NULL);
	144
a8f4bf0e VKS	145	clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk",
	146	0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
	147	&_lock, &clk1, NULL);
5df33a62 VK	148	clk_register_clkdev(clk, "vco2_clk", NULL);
	149	clk_register_clkdev(clk1, "pll2_clk", NULL);
	150
	151	clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
	152	1);
	153	clk_register_clkdev(clk, NULL, "wdt");
	154
	155	/* clock derived from pll1 clk */
12499792 VKS	156	clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
12499792 VKS	157	CLK_SET_RATE_PARENT, 1, 1);
5df33a62 VK	158	clk_register_clkdev(clk, "cpu_clk", NULL);
	159
	160	clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
	161	CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
	162	HCLK_RATIO_MASK, 0, &_lock);
	163	clk_register_clkdev(clk, "ahb_clk", NULL);
	164
a8f4bf0e VKS	165	clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
	166	UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
	167	&_lock, &clk1);
	168	clk_register_clkdev(clk, "uart_syn_clk", NULL);
	169	clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
5df33a62	170
a8f4bf0e	171	clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
819c1de3 JH	172	ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
	173	PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
	174	&_lock);
a8f4bf0e	175	clk_register_clkdev(clk, "uart_mclk", NULL);
5df33a62	176
a8f4bf0e VKS	177	clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
a8f4bf0e VKS	178	UART0_CLK_ENB, 0, &_lock);
5df33a62 VK	179	clk_register_clkdev(clk, NULL, "d0000000.serial");
5df33a62 VK	180
a8f4bf0e VKS	181	clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB,
a8f4bf0e VKS	182	UART1_CLK_ENB, 0, &_lock);
5df33a62 VK	183	clk_register_clkdev(clk, NULL, "d0080000.serial");
5df33a62 VK	184
a8f4bf0e VKS	185	clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk",
	186	0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
	187	&_lock, &clk1);
	188	clk_register_clkdev(clk, "firda_syn_clk", NULL);
	189	clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
5df33a62	190
a8f4bf0e	191	clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
819c1de3 JH	192	ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT,
	193	PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
	194	&_lock);
a8f4bf0e	195	clk_register_clkdev(clk, "firda_mclk", NULL);
5df33a62	196
a8f4bf0e	197	clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
5df33a62 VK	198	PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
	199	clk_register_clkdev(clk, NULL, "firda");
	200
a8f4bf0e VKS	201	clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk",
	202	0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
	203	&_lock, &clk1);
	204	clk_register_clkdev(clk, "clcd_syn_clk", NULL);
	205	clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);
5df33a62	206
a8f4bf0e	207	clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
819c1de3 JH	208	ARRAY_SIZE(clcd_parents), CLK_SET_RATE_NO_REPARENT,
	209	PERIP_CLK_CFG, CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0,
	210	&_lock);
a8f4bf0e	211	clk_register_clkdev(clk, "clcd_mclk", NULL);
5df33a62	212
a8f4bf0e	213	clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
5df33a62 VK	214	PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock);
	215	clk_register_clkdev(clk, NULL, "clcd");
	216
	217	/* gpt clocks */
a8f4bf0e	218	clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
5df33a62	219	gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
a8f4bf0e	220	clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);
5df33a62	221
a8f4bf0e	222	clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
819c1de3 JH	223	ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
819c1de3 JH	224	PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
5df33a62 VK	225	clk_register_clkdev(clk, NULL, "gpt0");
5df33a62 VK	226
a8f4bf0e	227	clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
819c1de3 JH	228	ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
819c1de3 JH	229	PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
a8f4bf0e	230	clk_register_clkdev(clk, "gpt1_mclk", NULL);
5df33a62	231
a8f4bf0e	232	clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
5df33a62 VK	233	PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
	234	clk_register_clkdev(clk, NULL, "gpt1");
	235
a8f4bf0e	236	clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
5df33a62	237	gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
a8f4bf0e	238	clk_register_clkdev(clk, "gpt2_syn_clk", NULL);
5df33a62	239
a8f4bf0e	240	clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
819c1de3 JH	241	ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_NO_REPARENT,
819c1de3 JH	242	PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
a8f4bf0e	243	clk_register_clkdev(clk, "gpt2_mclk", NULL);
5df33a62	244
a8f4bf0e	245	clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
5df33a62 VK	246	PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
	247	clk_register_clkdev(clk, NULL, "gpt2");
	248
a8f4bf0e	249	clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
5df33a62	250	gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
a8f4bf0e	251	clk_register_clkdev(clk, "gpt3_syn_clk", NULL);
5df33a62	252
a8f4bf0e	253	clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
819c1de3 JH	254	ARRAY_SIZE(gpt3_parents), CLK_SET_RATE_NO_REPARENT,
819c1de3 JH	255	PERIP_CLK_CFG, GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
a8f4bf0e	256	clk_register_clkdev(clk, "gpt3_mclk", NULL);
5df33a62	257
a8f4bf0e	258	clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
5df33a62 VK	259	PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock);
	260	clk_register_clkdev(clk, NULL, "gpt3");
	261
	262	/* clock derived from pll3 clk */
a8f4bf0e	263	clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0,
5df33a62	264	PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
df2449ab RK	265	clk_register_clkdev(clk, NULL, "e1800000.ehci");
df2449ab RK	266	clk_register_clkdev(clk, NULL, "e1900000.ohci");
5df33a62	267
a8f4bf0e	268	clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0,
5df33a62	269	PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
df2449ab RK	270	clk_register_clkdev(clk, NULL, "e2000000.ehci");
df2449ab RK	271	clk_register_clkdev(clk, NULL, "e2100000.ohci");
5df33a62	272
a8f4bf0e VKS	273	clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
a8f4bf0e VKS	274	USBD_CLK_ENB, 0, &_lock);
5df33a62 VK	275	clk_register_clkdev(clk, NULL, "designware_udc");
	276
	277	/* clock derived from ahb clk */
	278	clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
	279	1);
	280	clk_register_clkdev(clk, "ahbmult2_clk", NULL);
	281
	282	clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
819c1de3 JH	283	ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
819c1de3 JH	284	PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
5df33a62 VK	285	clk_register_clkdev(clk, "ddr_clk", NULL);
	286
	287	clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
	288	CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
	289	PCLK_RATIO_MASK, 0, &_lock);
	290	clk_register_clkdev(clk, "apb_clk", NULL);
	291
	292	clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
	293	DMA_CLK_ENB, 0, &_lock);
	294	clk_register_clkdev(clk, NULL, "fc400000.dma");
	295
	296	clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
	297	FSMC_CLK_ENB, 0, &_lock);
	298	clk_register_clkdev(clk, NULL, "d1800000.flash");
	299
	300	clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
	301	GMAC_CLK_ENB, 0, &_lock);
3a35fc3a	302	clk_register_clkdev(clk, NULL, "e0800000.ethernet");
5df33a62 VK	303
	304	clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
	305	I2C_CLK_ENB, 0, &_lock);
	306	clk_register_clkdev(clk, NULL, "d0200000.i2c");
	307
	308	clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
	309	JPEG_CLK_ENB, 0, &_lock);
	310	clk_register_clkdev(clk, NULL, "jpeg");
	311
	312	clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
	313	SMI_CLK_ENB, 0, &_lock);
	314	clk_register_clkdev(clk, NULL, "fc000000.flash");
	315
	316	/* clock derived from apb clk */
	317	clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
	318	ADC_CLK_ENB, 0, &_lock);
	319	clk_register_clkdev(clk, NULL, "adc");
	320
	321	clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1);
	322	clk_register_clkdev(clk, NULL, "f0100000.gpio");
	323
	324	clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
	325	GPIO1_CLK_ENB, 0, &_lock);
	326	clk_register_clkdev(clk, NULL, "fc980000.gpio");
	327
	328	clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
	329	GPIO2_CLK_ENB, 0, &_lock);
	330	clk_register_clkdev(clk, NULL, "d8100000.gpio");
	331
	332	clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
	333	SSP0_CLK_ENB, 0, &_lock);
	334	clk_register_clkdev(clk, NULL, "ssp-pl022.0");
	335
	336	clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
	337	SSP1_CLK_ENB, 0, &_lock);
	338	clk_register_clkdev(clk, NULL, "ssp-pl022.1");
	339
	340	clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
	341	SSP2_CLK_ENB, 0, &_lock);
	342	clk_register_clkdev(clk, NULL, "ssp-pl022.2");
	343	}