[linux-block.git] / drivers / clk / spear / spear6xx_clock.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * SPEAr6xx machines clock framework source file
 *
 * Copyright (C) 2012 ST Microelectronics
 * Viresh Kumar <vireshk@kernel.org>
 */

#include <linux/clkdev.h>
#include <linux/clk/spear.h>
#include <linux/io.h>
#include <linux/spinlock_types.h>
#include "clk.h"

static DEFINE_SPINLOCK(_lock);

#define PLL1_CTR			(misc_base + 0x008)
#define PLL1_FRQ			(misc_base + 0x00C)
#define PLL2_CTR			(misc_base + 0x014)
#define PLL2_FRQ			(misc_base + 0x018)
#define PLL_CLK_CFG			(misc_base + 0x020)
	/* PLL_CLK_CFG register masks */
	#define MCTR_CLK_SHIFT		28
	#define MCTR_CLK_MASK		3

#define CORE_CLK_CFG			(misc_base + 0x024)
	/* CORE CLK CFG register masks */
	#define HCLK_RATIO_SHIFT	10
	#define HCLK_RATIO_MASK		2
	#define PCLK_RATIO_SHIFT	8
	#define PCLK_RATIO_MASK		2

#define PERIP_CLK_CFG			(misc_base + 0x028)
	/* PERIP_CLK_CFG register masks */
	#define CLCD_CLK_SHIFT		2
	#define CLCD_CLK_MASK		2
	#define UART_CLK_SHIFT		4
	#define UART_CLK_MASK		1
	#define FIRDA_CLK_SHIFT		5
	#define FIRDA_CLK_MASK		2
	#define GPT0_CLK_SHIFT		8
	#define GPT1_CLK_SHIFT		10
	#define GPT2_CLK_SHIFT		11
	#define GPT3_CLK_SHIFT		12
	#define GPT_CLK_MASK		1

#define PERIP1_CLK_ENB			(misc_base + 0x02C)
	/* PERIP1_CLK_ENB register masks */
	#define UART0_CLK_ENB		3
	#define UART1_CLK_ENB		4
	#define SSP0_CLK_ENB		5
	#define SSP1_CLK_ENB		6
	#define I2C_CLK_ENB		7
	#define JPEG_CLK_ENB		8
	#define FSMC_CLK_ENB		9
	#define FIRDA_CLK_ENB		10
	#define GPT2_CLK_ENB		11
	#define GPT3_CLK_ENB		12
	#define GPIO2_CLK_ENB		13
	#define SSP2_CLK_ENB		14
	#define ADC_CLK_ENB		15
	#define GPT1_CLK_ENB		11
	#define RTC_CLK_ENB		17
	#define GPIO1_CLK_ENB		18
	#define DMA_CLK_ENB		19
	#define SMI_CLK_ENB		21
	#define CLCD_CLK_ENB		22
	#define GMAC_CLK_ENB		23
	#define USBD_CLK_ENB		24
	#define USBH0_CLK_ENB		25
	#define USBH1_CLK_ENB		26

#define PRSC0_CLK_CFG			(misc_base + 0x044)
#define PRSC1_CLK_CFG			(misc_base + 0x048)
#define PRSC2_CLK_CFG			(misc_base + 0x04C)

#define CLCD_CLK_SYNT			(misc_base + 0x05C)
#define FIRDA_CLK_SYNT			(misc_base + 0x060)
#define UART_CLK_SYNT			(misc_base + 0x064)

/* vco rate configuration table, in ascending order of rates */
static struct pll_rate_tbl pll_rtbl[] = {
	{.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */
	{.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */
	{.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */
};

/* aux rate configuration table, in ascending order of rates */
static struct aux_rate_tbl aux_rtbl[] = {
	/* For PLL1 = 332 MHz */
	{.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
	{.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
	{.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
	{.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
};

static const char *clcd_parents[] = { "pll3_clk", "clcd_syn_gclk", };
static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", };
static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", };
static const char *gpt0_1_parents[] = { "pll3_clk", "gpt0_1_syn_clk", };
static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
static const char *gpt3_parents[] = { "pll3_clk", "gpt3_syn_clk", };
static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
	"pll2_clk", };

/* gpt rate configuration table, in ascending order of rates */
static struct gpt_rate_tbl gpt_rtbl[] = {
	/* For pll1 = 332 MHz */
	{.mscale = 4, .nscale = 0}, /* 41.5 MHz */
	{.mscale = 2, .nscale = 0}, /* 55.3 MHz */
	{.mscale = 1, .nscale = 0}, /* 83 MHz */
};

void __init spear6xx_clk_init(void __iomem *misc_base)
{
	struct clk *clk, *clk1;

	clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
	clk_register_clkdev(clk, "osc_32k_clk", NULL);

	clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000);
	clk_register_clkdev(clk, "osc_30m_clk", NULL);

	/* clock derived from 32 KHz osc clk */
	clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0,
			PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "rtc-spear");

	/* clock derived from 30 MHz osc clk */
	clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
			48000000);
	clk_register_clkdev(clk, "pll3_clk", NULL);

	clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
			0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
			&_lock, &clk1, NULL);
	clk_register_clkdev(clk, "vco1_clk", NULL);
	clk_register_clkdev(clk1, "pll1_clk", NULL);

	clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk",
			0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
			&_lock, &clk1, NULL);
	clk_register_clkdev(clk, "vco2_clk", NULL);
	clk_register_clkdev(clk1, "pll2_clk", NULL);

	clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
			1);
	clk_register_clkdev(clk, NULL, "fc880000.wdt");

	/* clock derived from pll1 clk */
	clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
			CLK_SET_RATE_PARENT, 1, 1);
	clk_register_clkdev(clk, "cpu_clk", NULL);

	clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
			CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
			HCLK_RATIO_MASK, 0, &_lock);
	clk_register_clkdev(clk, "ahb_clk", NULL);

	clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
			UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
			&_lock, &clk1);
	clk_register_clkdev(clk, "uart_syn_clk", NULL);
	clk_register_clkdev(clk1, "uart_syn_gclk", NULL);

	clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
			ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
			PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
			&_lock);
	clk_register_clkdev(clk, "uart_mclk", NULL);

	clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
			UART0_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "d0000000.serial");

	clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB,
			UART1_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "d0080000.serial");

	clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk",
			0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
			&_lock, &clk1);
	clk_register_clkdev(clk, "firda_syn_clk", NULL);
	clk_register_clkdev(clk1, "firda_syn_gclk", NULL);

	clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
			ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT,
			PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
			&_lock);
	clk_register_clkdev(clk, "firda_mclk", NULL);

	clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
			PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "firda");

	clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk",
			0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
			&_lock, &clk1);
	clk_register_clkdev(clk, "clcd_syn_clk", NULL);
	clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);

	clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
			ARRAY_SIZE(clcd_parents), CLK_SET_RATE_NO_REPARENT,
			PERIP_CLK_CFG, CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0,
			&_lock);
	clk_register_clkdev(clk, "clcd_mclk", NULL);

	clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
			PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "clcd");

	/* gpt clocks */
	clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
			gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
	clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);

	clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
			ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
			PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
	clk_register_clkdev(clk, NULL, "gpt0");

	clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
			ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
			PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
	clk_register_clkdev(clk, "gpt1_mclk", NULL);

	clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
			PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "gpt1");

	clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
			gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
	clk_register_clkdev(clk, "gpt2_syn_clk", NULL);

	clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
			ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_NO_REPARENT,
			PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
	clk_register_clkdev(clk, "gpt2_mclk", NULL);

	clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
			PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "gpt2");

	clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
			gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
	clk_register_clkdev(clk, "gpt3_syn_clk", NULL);

	clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
			ARRAY_SIZE(gpt3_parents), CLK_SET_RATE_NO_REPARENT,
			PERIP_CLK_CFG, GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
	clk_register_clkdev(clk, "gpt3_mclk", NULL);

	clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
			PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "gpt3");

	/* clock derived from pll3 clk */
	clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0,
			PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "e1800000.ehci");
	clk_register_clkdev(clk, NULL, "e1900000.ohci");

	clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0,
			PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "e2000000.ehci");
	clk_register_clkdev(clk, NULL, "e2100000.ohci");

	clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
			USBD_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "designware_udc");

	/* clock derived from ahb clk */
	clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
			1);
	clk_register_clkdev(clk, "ahbmult2_clk", NULL);

	clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
			ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
			PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
	clk_register_clkdev(clk, "ddr_clk", NULL);

	clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
			CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
			PCLK_RATIO_MASK, 0, &_lock);
	clk_register_clkdev(clk, "apb_clk", NULL);

	clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
			DMA_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "fc400000.dma");

	clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
			FSMC_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "d1800000.flash");

	clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
			GMAC_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "e0800000.ethernet");

	clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
			I2C_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "d0200000.i2c");

	clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
			JPEG_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "jpeg");

	clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
			SMI_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "fc000000.flash");

	/* clock derived from apb clk */
	clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
			ADC_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "d820b000.adc");

	clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1);
	clk_register_clkdev(clk, NULL, "f0100000.gpio");

	clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
			GPIO1_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "fc980000.gpio");

	clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
			GPIO2_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "d8100000.gpio");

	clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
			SSP0_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "ssp-pl022.0");

	clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
			SSP1_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "ssp-pl022.1");

	clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
			SSP2_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "ssp-pl022.2");
}
Commit	Line	Data
3bb16560	1	// SPDX-License-Identifier: GPL-2.0-only
5df33a62 VK	2	/*
	3	* SPEAr6xx machines clock framework source file
	4	*
	5	* Copyright (C) 2012 ST Microelectronics
da89947b	6	* Viresh Kumar <vireshk@kernel.org>
5df33a62 VK	7	*/
5df33a62 VK	8
5df33a62	9	#include <linux/clkdev.h>
9afd20a5	10	#include <linux/clk/spear.h>
5df33a62 VK	11	#include <linux/io.h>
5df33a62 VK	12	#include <linux/spinlock_types.h>
5df33a62 VK	13	#include "clk.h"
	14
	15	static DEFINE_SPINLOCK(_lock);
	16
d9909ebe AB	17	#define PLL1_CTR (misc_base + 0x008)
	18	#define PLL1_FRQ (misc_base + 0x00C)
	19	#define PLL2_CTR (misc_base + 0x014)
	20	#define PLL2_FRQ (misc_base + 0x018)
	21	#define PLL_CLK_CFG (misc_base + 0x020)
5df33a62 VK	22	/* PLL_CLK_CFG register masks */
	23	#define MCTR_CLK_SHIFT 28
	24	#define MCTR_CLK_MASK 3
	25
d9909ebe	26	#define CORE_CLK_CFG (misc_base + 0x024)
5df33a62 VK	27	/* CORE CLK CFG register masks */
	28	#define HCLK_RATIO_SHIFT 10
	29	#define HCLK_RATIO_MASK 2
	30	#define PCLK_RATIO_SHIFT 8
	31	#define PCLK_RATIO_MASK 2
	32
d9909ebe	33	#define PERIP_CLK_CFG (misc_base + 0x028)
5df33a62 VK	34	/* PERIP_CLK_CFG register masks */
	35	#define CLCD_CLK_SHIFT 2
	36	#define CLCD_CLK_MASK 2
	37	#define UART_CLK_SHIFT 4
	38	#define UART_CLK_MASK 1
	39	#define FIRDA_CLK_SHIFT 5
	40	#define FIRDA_CLK_MASK 2
	41	#define GPT0_CLK_SHIFT 8
	42	#define GPT1_CLK_SHIFT 10
	43	#define GPT2_CLK_SHIFT 11
	44	#define GPT3_CLK_SHIFT 12
	45	#define GPT_CLK_MASK 1
	46
d9909ebe	47	#define PERIP1_CLK_ENB (misc_base + 0x02C)
5df33a62 VK	48	/* PERIP1_CLK_ENB register masks */
	49	#define UART0_CLK_ENB 3
	50	#define UART1_CLK_ENB 4
	51	#define SSP0_CLK_ENB 5
	52	#define SSP1_CLK_ENB 6
	53	#define I2C_CLK_ENB 7
	54	#define JPEG_CLK_ENB 8
	55	#define FSMC_CLK_ENB 9
	56	#define FIRDA_CLK_ENB 10
	57	#define GPT2_CLK_ENB 11
	58	#define GPT3_CLK_ENB 12
	59	#define GPIO2_CLK_ENB 13
	60	#define SSP2_CLK_ENB 14
	61	#define ADC_CLK_ENB 15
	62	#define GPT1_CLK_ENB 11
	63	#define RTC_CLK_ENB 17
	64	#define GPIO1_CLK_ENB 18
	65	#define DMA_CLK_ENB 19
	66	#define SMI_CLK_ENB 21
	67	#define CLCD_CLK_ENB 22
	68	#define GMAC_CLK_ENB 23
	69	#define USBD_CLK_ENB 24
	70	#define USBH0_CLK_ENB 25
	71	#define USBH1_CLK_ENB 26
	72
d9909ebe AB	73	#define PRSC0_CLK_CFG (misc_base + 0x044)
	74	#define PRSC1_CLK_CFG (misc_base + 0x048)
	75	#define PRSC2_CLK_CFG (misc_base + 0x04C)
5df33a62	76
d9909ebe AB	77	#define CLCD_CLK_SYNT (misc_base + 0x05C)
	78	#define FIRDA_CLK_SYNT (misc_base + 0x060)
	79	#define UART_CLK_SYNT (misc_base + 0x064)
5df33a62 VK	80
	81	/* vco rate configuration table, in ascending order of rates */
	82	static struct pll_rate_tbl pll_rtbl[] = {
	83	{.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */
	84	{.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */
	85	{.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */
	86	};
	87
	88	/* aux rate configuration table, in ascending order of rates */
	89	static struct aux_rate_tbl aux_rtbl[] = {
	90	/* For PLL1 = 332 MHz */
ef0fd0a2	91	{.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
5df33a62 VK	92	{.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
	93	{.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
	94	{.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
	95	};
	96
a8f4bf0e VKS	97	static const char *clcd_parents[] = { "pll3_clk", "clcd_syn_gclk", };
	98	static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", };
	99	static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", };
	100	static const char *gpt0_1_parents[] = { "pll3_clk", "gpt0_1_syn_clk", };
	101	static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
	102	static const char *gpt3_parents[] = { "pll3_clk", "gpt3_syn_clk", };
5df33a62 VK	103	static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
	104	"pll2_clk", };
	105
	106	/* gpt rate configuration table, in ascending order of rates */
	107	static struct gpt_rate_tbl gpt_rtbl[] = {
	108	/* For pll1 = 332 MHz */
	109	{.mscale = 4, .nscale = 0}, /* 41.5 MHz */
	110	{.mscale = 2, .nscale = 0}, /* 55.3 MHz */
	111	{.mscale = 1, .nscale = 0}, /* 83 MHz */
	112	};
	113
d9909ebe	114	void __init spear6xx_clk_init(void __iomem *misc_base)
5df33a62 VK	115	{
	116	struct clk clk, clk1;
	117
afb4bdc9	118	clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
5df33a62 VK	119	clk_register_clkdev(clk, "osc_32k_clk", NULL);
5df33a62 VK	120
afb4bdc9	121	clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000);
5df33a62 VK	122	clk_register_clkdev(clk, "osc_30m_clk", NULL);
	123
	124	/* clock derived from 32 KHz osc clk */
	125	clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0,
	126	PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
	127	clk_register_clkdev(clk, NULL, "rtc-spear");
	128
	129	/* clock derived from 30 MHz osc clk */
a8f4bf0e	130	clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
5df33a62	131	48000000);
a8f4bf0e	132	clk_register_clkdev(clk, "pll3_clk", NULL);
5df33a62 VK	133
	134	clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
	135	0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
	136	&_lock, &clk1, NULL);
	137	clk_register_clkdev(clk, "vco1_clk", NULL);
	138	clk_register_clkdev(clk1, "pll1_clk", NULL);
	139
a8f4bf0e VKS	140	clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk",
	141	0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
	142	&_lock, &clk1, NULL);
5df33a62 VK	143	clk_register_clkdev(clk, "vco2_clk", NULL);
	144	clk_register_clkdev(clk1, "pll2_clk", NULL);
	145
	146	clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
	147	1);
1af897df	148	clk_register_clkdev(clk, NULL, "fc880000.wdt");
5df33a62 VK	149
5df33a62 VK	150	/* clock derived from pll1 clk */
12499792 VKS	151	clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
12499792 VKS	152	CLK_SET_RATE_PARENT, 1, 1);
5df33a62 VK	153	clk_register_clkdev(clk, "cpu_clk", NULL);
	154
	155	clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
	156	CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
	157	HCLK_RATIO_MASK, 0, &_lock);
	158	clk_register_clkdev(clk, "ahb_clk", NULL);
	159
a8f4bf0e VKS	160	clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
	161	UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
	162	&_lock, &clk1);
	163	clk_register_clkdev(clk, "uart_syn_clk", NULL);
	164	clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
5df33a62	165
a8f4bf0e	166	clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
819c1de3 JH	167	ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
	168	PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
	169	&_lock);
a8f4bf0e	170	clk_register_clkdev(clk, "uart_mclk", NULL);
5df33a62	171
a8f4bf0e VKS	172	clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
a8f4bf0e VKS	173	UART0_CLK_ENB, 0, &_lock);
5df33a62 VK	174	clk_register_clkdev(clk, NULL, "d0000000.serial");
5df33a62 VK	175
a8f4bf0e VKS	176	clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB,
a8f4bf0e VKS	177	UART1_CLK_ENB, 0, &_lock);
5df33a62 VK	178	clk_register_clkdev(clk, NULL, "d0080000.serial");
5df33a62 VK	179
a8f4bf0e VKS	180	clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk",
	181	0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
	182	&_lock, &clk1);
	183	clk_register_clkdev(clk, "firda_syn_clk", NULL);
	184	clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
5df33a62	185
a8f4bf0e	186	clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
819c1de3 JH	187	ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT,
	188	PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
	189	&_lock);
a8f4bf0e	190	clk_register_clkdev(clk, "firda_mclk", NULL);
5df33a62	191
a8f4bf0e	192	clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
5df33a62 VK	193	PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
	194	clk_register_clkdev(clk, NULL, "firda");
	195
a8f4bf0e VKS	196	clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk",
	197	0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
	198	&_lock, &clk1);
	199	clk_register_clkdev(clk, "clcd_syn_clk", NULL);
	200	clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);
5df33a62	201
a8f4bf0e	202	clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
819c1de3 JH	203	ARRAY_SIZE(clcd_parents), CLK_SET_RATE_NO_REPARENT,
	204	PERIP_CLK_CFG, CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0,
	205	&_lock);
a8f4bf0e	206	clk_register_clkdev(clk, "clcd_mclk", NULL);
5df33a62	207
a8f4bf0e	208	clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
5df33a62 VK	209	PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock);
	210	clk_register_clkdev(clk, NULL, "clcd");
	211
	212	/* gpt clocks */
a8f4bf0e	213	clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
5df33a62	214	gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
a8f4bf0e	215	clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);
5df33a62	216
a8f4bf0e	217	clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
819c1de3 JH	218	ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
819c1de3 JH	219	PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
5df33a62 VK	220	clk_register_clkdev(clk, NULL, "gpt0");
5df33a62 VK	221
a8f4bf0e	222	clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
819c1de3 JH	223	ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
819c1de3 JH	224	PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
a8f4bf0e	225	clk_register_clkdev(clk, "gpt1_mclk", NULL);
5df33a62	226
a8f4bf0e	227	clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
5df33a62 VK	228	PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
	229	clk_register_clkdev(clk, NULL, "gpt1");
	230
a8f4bf0e	231	clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
5df33a62	232	gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
a8f4bf0e	233	clk_register_clkdev(clk, "gpt2_syn_clk", NULL);
5df33a62	234
a8f4bf0e	235	clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
819c1de3 JH	236	ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_NO_REPARENT,
819c1de3 JH	237	PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
a8f4bf0e	238	clk_register_clkdev(clk, "gpt2_mclk", NULL);
5df33a62	239
a8f4bf0e	240	clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
5df33a62 VK	241	PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
	242	clk_register_clkdev(clk, NULL, "gpt2");
	243
a8f4bf0e	244	clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
5df33a62	245	gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
a8f4bf0e	246	clk_register_clkdev(clk, "gpt3_syn_clk", NULL);
5df33a62	247
a8f4bf0e	248	clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
819c1de3 JH	249	ARRAY_SIZE(gpt3_parents), CLK_SET_RATE_NO_REPARENT,
819c1de3 JH	250	PERIP_CLK_CFG, GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
a8f4bf0e	251	clk_register_clkdev(clk, "gpt3_mclk", NULL);
5df33a62	252
a8f4bf0e	253	clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
5df33a62 VK	254	PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock);
	255	clk_register_clkdev(clk, NULL, "gpt3");
	256
	257	/* clock derived from pll3 clk */
a8f4bf0e	258	clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0,
5df33a62	259	PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
df2449ab RK	260	clk_register_clkdev(clk, NULL, "e1800000.ehci");
df2449ab RK	261	clk_register_clkdev(clk, NULL, "e1900000.ohci");
5df33a62	262
a8f4bf0e	263	clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0,
5df33a62	264	PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
df2449ab RK	265	clk_register_clkdev(clk, NULL, "e2000000.ehci");
df2449ab RK	266	clk_register_clkdev(clk, NULL, "e2100000.ohci");
5df33a62	267
a8f4bf0e VKS	268	clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
a8f4bf0e VKS	269	USBD_CLK_ENB, 0, &_lock);
5df33a62 VK	270	clk_register_clkdev(clk, NULL, "designware_udc");
	271
	272	/* clock derived from ahb clk */
	273	clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
	274	1);
	275	clk_register_clkdev(clk, "ahbmult2_clk", NULL);
	276
	277	clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
819c1de3 JH	278	ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
819c1de3 JH	279	PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
5df33a62 VK	280	clk_register_clkdev(clk, "ddr_clk", NULL);
	281
	282	clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
	283	CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
	284	PCLK_RATIO_MASK, 0, &_lock);
	285	clk_register_clkdev(clk, "apb_clk", NULL);
	286
	287	clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
	288	DMA_CLK_ENB, 0, &_lock);
	289	clk_register_clkdev(clk, NULL, "fc400000.dma");
	290
	291	clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
	292	FSMC_CLK_ENB, 0, &_lock);
	293	clk_register_clkdev(clk, NULL, "d1800000.flash");
	294
	295	clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
	296	GMAC_CLK_ENB, 0, &_lock);
3a35fc3a	297	clk_register_clkdev(clk, NULL, "e0800000.ethernet");
5df33a62 VK	298
	299	clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
	300	I2C_CLK_ENB, 0, &_lock);
	301	clk_register_clkdev(clk, NULL, "d0200000.i2c");
	302
	303	clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
	304	JPEG_CLK_ENB, 0, &_lock);
	305	clk_register_clkdev(clk, NULL, "jpeg");
	306
	307	clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
	308	SMI_CLK_ENB, 0, &_lock);
	309	clk_register_clkdev(clk, NULL, "fc000000.flash");
	310
	311	/* clock derived from apb clk */
	312	clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
	313	ADC_CLK_ENB, 0, &_lock);
1b214013	314	clk_register_clkdev(clk, NULL, "d820b000.adc");
5df33a62 VK	315
	316	clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1);
	317	clk_register_clkdev(clk, NULL, "f0100000.gpio");
	318
	319	clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
	320	GPIO1_CLK_ENB, 0, &_lock);
	321	clk_register_clkdev(clk, NULL, "fc980000.gpio");
	322
	323	clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
	324	GPIO2_CLK_ENB, 0, &_lock);
	325	clk_register_clkdev(clk, NULL, "d8100000.gpio");
	326
	327	clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
	328	SSP0_CLK_ENB, 0, &_lock);
	329	clk_register_clkdev(clk, NULL, "ssp-pl022.0");
	330
	331	clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
	332	SSP1_CLK_ENB, 0, &_lock);
	333	clk_register_clkdev(clk, NULL, "ssp-pl022.1");
	334
	335	clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
	336	SSP2_CLK_ENB, 0, &_lock);
	337	clk_register_clkdev(clk, NULL, "ssp-pl022.2");
	338	}