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0b928af1 VK |
1 | /* |
2 | * arch/arm/mach-spear13xx/spear1310_clock.c | |
3 | * | |
4 | * SPEAr1310 machine clock framework source file | |
5 | * | |
6 | * Copyright (C) 2012 ST Microelectronics | |
da89947b | 7 | * Viresh Kumar <vireshk@kernel.org> |
0b928af1 VK |
8 | * |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
0b928af1 VK |
14 | #include <linux/clkdev.h> |
15 | #include <linux/err.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/of_platform.h> | |
18 | #include <linux/spinlock_types.h> | |
0b928af1 VK |
19 | #include "clk.h" |
20 | ||
21 | /* PLL related registers and bit values */ | |
d9909ebe | 22 | #define SPEAR1310_PLL_CFG (misc_base + 0x210) |
0b928af1 VK |
23 | /* PLL_CFG bit values */ |
24 | #define SPEAR1310_CLCD_SYNT_CLK_MASK 1 | |
25 | #define SPEAR1310_CLCD_SYNT_CLK_SHIFT 31 | |
26 | #define SPEAR1310_RAS_SYNT2_3_CLK_MASK 2 | |
27 | #define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT 29 | |
28 | #define SPEAR1310_RAS_SYNT_CLK_MASK 2 | |
29 | #define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT 27 | |
30 | #define SPEAR1310_PLL_CLK_MASK 2 | |
31 | #define SPEAR1310_PLL3_CLK_SHIFT 24 | |
32 | #define SPEAR1310_PLL2_CLK_SHIFT 22 | |
33 | #define SPEAR1310_PLL1_CLK_SHIFT 20 | |
34 | ||
d9909ebe AB |
35 | #define SPEAR1310_PLL1_CTR (misc_base + 0x214) |
36 | #define SPEAR1310_PLL1_FRQ (misc_base + 0x218) | |
37 | #define SPEAR1310_PLL2_CTR (misc_base + 0x220) | |
38 | #define SPEAR1310_PLL2_FRQ (misc_base + 0x224) | |
39 | #define SPEAR1310_PLL3_CTR (misc_base + 0x22C) | |
40 | #define SPEAR1310_PLL3_FRQ (misc_base + 0x230) | |
41 | #define SPEAR1310_PLL4_CTR (misc_base + 0x238) | |
42 | #define SPEAR1310_PLL4_FRQ (misc_base + 0x23C) | |
43 | #define SPEAR1310_PERIP_CLK_CFG (misc_base + 0x244) | |
0b928af1 VK |
44 | /* PERIP_CLK_CFG bit values */ |
45 | #define SPEAR1310_GPT_OSC24_VAL 0 | |
46 | #define SPEAR1310_GPT_APB_VAL 1 | |
47 | #define SPEAR1310_GPT_CLK_MASK 1 | |
48 | #define SPEAR1310_GPT3_CLK_SHIFT 11 | |
49 | #define SPEAR1310_GPT2_CLK_SHIFT 10 | |
50 | #define SPEAR1310_GPT1_CLK_SHIFT 9 | |
51 | #define SPEAR1310_GPT0_CLK_SHIFT 8 | |
52 | #define SPEAR1310_UART_CLK_PLL5_VAL 0 | |
53 | #define SPEAR1310_UART_CLK_OSC24_VAL 1 | |
54 | #define SPEAR1310_UART_CLK_SYNT_VAL 2 | |
55 | #define SPEAR1310_UART_CLK_MASK 2 | |
56 | #define SPEAR1310_UART_CLK_SHIFT 4 | |
57 | ||
58 | #define SPEAR1310_AUX_CLK_PLL5_VAL 0 | |
59 | #define SPEAR1310_AUX_CLK_SYNT_VAL 1 | |
60 | #define SPEAR1310_CLCD_CLK_MASK 2 | |
61 | #define SPEAR1310_CLCD_CLK_SHIFT 2 | |
62 | #define SPEAR1310_C3_CLK_MASK 1 | |
63 | #define SPEAR1310_C3_CLK_SHIFT 1 | |
64 | ||
d9909ebe | 65 | #define SPEAR1310_GMAC_CLK_CFG (misc_base + 0x248) |
0b928af1 VK |
66 | #define SPEAR1310_GMAC_PHY_IF_SEL_MASK 3 |
67 | #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT 4 | |
68 | #define SPEAR1310_GMAC_PHY_CLK_MASK 1 | |
69 | #define SPEAR1310_GMAC_PHY_CLK_SHIFT 3 | |
70 | #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2 | |
71 | #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1 | |
72 | ||
d9909ebe | 73 | #define SPEAR1310_I2S_CLK_CFG (misc_base + 0x24C) |
0b928af1 VK |
74 | /* I2S_CLK_CFG register mask */ |
75 | #define SPEAR1310_I2S_SCLK_X_MASK 0x1F | |
76 | #define SPEAR1310_I2S_SCLK_X_SHIFT 27 | |
77 | #define SPEAR1310_I2S_SCLK_Y_MASK 0x1F | |
78 | #define SPEAR1310_I2S_SCLK_Y_SHIFT 22 | |
79 | #define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT 21 | |
80 | #define SPEAR1310_I2S_SCLK_SYNTH_ENB 20 | |
81 | #define SPEAR1310_I2S_PRS1_CLK_X_MASK 0xFF | |
82 | #define SPEAR1310_I2S_PRS1_CLK_X_SHIFT 12 | |
83 | #define SPEAR1310_I2S_PRS1_CLK_Y_MASK 0xFF | |
84 | #define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT 4 | |
85 | #define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT 3 | |
86 | #define SPEAR1310_I2S_REF_SEL_MASK 1 | |
87 | #define SPEAR1310_I2S_REF_SHIFT 2 | |
88 | #define SPEAR1310_I2S_SRC_CLK_MASK 2 | |
89 | #define SPEAR1310_I2S_SRC_CLK_SHIFT 0 | |
90 | ||
d9909ebe AB |
91 | #define SPEAR1310_C3_CLK_SYNT (misc_base + 0x250) |
92 | #define SPEAR1310_UART_CLK_SYNT (misc_base + 0x254) | |
93 | #define SPEAR1310_GMAC_CLK_SYNT (misc_base + 0x258) | |
94 | #define SPEAR1310_SDHCI_CLK_SYNT (misc_base + 0x25C) | |
95 | #define SPEAR1310_CFXD_CLK_SYNT (misc_base + 0x260) | |
96 | #define SPEAR1310_ADC_CLK_SYNT (misc_base + 0x264) | |
97 | #define SPEAR1310_AMBA_CLK_SYNT (misc_base + 0x268) | |
98 | #define SPEAR1310_CLCD_CLK_SYNT (misc_base + 0x270) | |
99 | #define SPEAR1310_RAS_CLK_SYNT0 (misc_base + 0x280) | |
100 | #define SPEAR1310_RAS_CLK_SYNT1 (misc_base + 0x288) | |
101 | #define SPEAR1310_RAS_CLK_SYNT2 (misc_base + 0x290) | |
102 | #define SPEAR1310_RAS_CLK_SYNT3 (misc_base + 0x298) | |
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103 | /* Check Fractional synthesizer reg masks */ |
104 | ||
d9909ebe | 105 | #define SPEAR1310_PERIP1_CLK_ENB (misc_base + 0x300) |
0b928af1 VK |
106 | /* PERIP1_CLK_ENB register masks */ |
107 | #define SPEAR1310_RTC_CLK_ENB 31 | |
108 | #define SPEAR1310_ADC_CLK_ENB 30 | |
109 | #define SPEAR1310_C3_CLK_ENB 29 | |
110 | #define SPEAR1310_JPEG_CLK_ENB 28 | |
111 | #define SPEAR1310_CLCD_CLK_ENB 27 | |
112 | #define SPEAR1310_DMA_CLK_ENB 25 | |
113 | #define SPEAR1310_GPIO1_CLK_ENB 24 | |
114 | #define SPEAR1310_GPIO0_CLK_ENB 23 | |
115 | #define SPEAR1310_GPT1_CLK_ENB 22 | |
116 | #define SPEAR1310_GPT0_CLK_ENB 21 | |
117 | #define SPEAR1310_I2S0_CLK_ENB 20 | |
118 | #define SPEAR1310_I2S1_CLK_ENB 19 | |
119 | #define SPEAR1310_I2C0_CLK_ENB 18 | |
120 | #define SPEAR1310_SSP_CLK_ENB 17 | |
121 | #define SPEAR1310_UART_CLK_ENB 15 | |
122 | #define SPEAR1310_PCIE_SATA_2_CLK_ENB 14 | |
123 | #define SPEAR1310_PCIE_SATA_1_CLK_ENB 13 | |
124 | #define SPEAR1310_PCIE_SATA_0_CLK_ENB 12 | |
125 | #define SPEAR1310_UOC_CLK_ENB 11 | |
126 | #define SPEAR1310_UHC1_CLK_ENB 10 | |
127 | #define SPEAR1310_UHC0_CLK_ENB 9 | |
128 | #define SPEAR1310_GMAC_CLK_ENB 8 | |
129 | #define SPEAR1310_CFXD_CLK_ENB 7 | |
130 | #define SPEAR1310_SDHCI_CLK_ENB 6 | |
131 | #define SPEAR1310_SMI_CLK_ENB 5 | |
132 | #define SPEAR1310_FSMC_CLK_ENB 4 | |
133 | #define SPEAR1310_SYSRAM0_CLK_ENB 3 | |
134 | #define SPEAR1310_SYSRAM1_CLK_ENB 2 | |
135 | #define SPEAR1310_SYSROM_CLK_ENB 1 | |
136 | #define SPEAR1310_BUS_CLK_ENB 0 | |
137 | ||
d9909ebe | 138 | #define SPEAR1310_PERIP2_CLK_ENB (misc_base + 0x304) |
0b928af1 VK |
139 | /* PERIP2_CLK_ENB register masks */ |
140 | #define SPEAR1310_THSENS_CLK_ENB 8 | |
141 | #define SPEAR1310_I2S_REF_PAD_CLK_ENB 7 | |
142 | #define SPEAR1310_ACP_CLK_ENB 6 | |
143 | #define SPEAR1310_GPT3_CLK_ENB 5 | |
144 | #define SPEAR1310_GPT2_CLK_ENB 4 | |
145 | #define SPEAR1310_KBD_CLK_ENB 3 | |
146 | #define SPEAR1310_CPU_DBG_CLK_ENB 2 | |
147 | #define SPEAR1310_DDR_CORE_CLK_ENB 1 | |
148 | #define SPEAR1310_DDR_CTRL_CLK_ENB 0 | |
149 | ||
d9909ebe | 150 | #define SPEAR1310_RAS_CLK_ENB (misc_base + 0x310) |
0b928af1 VK |
151 | /* RAS_CLK_ENB register masks */ |
152 | #define SPEAR1310_SYNT3_CLK_ENB 17 | |
153 | #define SPEAR1310_SYNT2_CLK_ENB 16 | |
154 | #define SPEAR1310_SYNT1_CLK_ENB 15 | |
155 | #define SPEAR1310_SYNT0_CLK_ENB 14 | |
156 | #define SPEAR1310_PCLK3_CLK_ENB 13 | |
157 | #define SPEAR1310_PCLK2_CLK_ENB 12 | |
158 | #define SPEAR1310_PCLK1_CLK_ENB 11 | |
159 | #define SPEAR1310_PCLK0_CLK_ENB 10 | |
160 | #define SPEAR1310_PLL3_CLK_ENB 9 | |
161 | #define SPEAR1310_PLL2_CLK_ENB 8 | |
162 | #define SPEAR1310_C125M_PAD_CLK_ENB 7 | |
163 | #define SPEAR1310_C30M_CLK_ENB 6 | |
164 | #define SPEAR1310_C48M_CLK_ENB 5 | |
165 | #define SPEAR1310_OSC_25M_CLK_ENB 4 | |
166 | #define SPEAR1310_OSC_32K_CLK_ENB 3 | |
167 | #define SPEAR1310_OSC_24M_CLK_ENB 2 | |
168 | #define SPEAR1310_PCLK_CLK_ENB 1 | |
169 | #define SPEAR1310_ACLK_CLK_ENB 0 | |
170 | ||
171 | /* RAS Area Control Register */ | |
d9909ebe | 172 | #define SPEAR1310_RAS_CTRL_REG0 (ras_base + 0x000) |
0b928af1 VK |
173 | #define SPEAR1310_SSP1_CLK_MASK 3 |
174 | #define SPEAR1310_SSP1_CLK_SHIFT 26 | |
175 | #define SPEAR1310_TDM_CLK_MASK 1 | |
176 | #define SPEAR1310_TDM2_CLK_SHIFT 24 | |
177 | #define SPEAR1310_TDM1_CLK_SHIFT 23 | |
178 | #define SPEAR1310_I2C_CLK_MASK 1 | |
179 | #define SPEAR1310_I2C7_CLK_SHIFT 22 | |
180 | #define SPEAR1310_I2C6_CLK_SHIFT 21 | |
181 | #define SPEAR1310_I2C5_CLK_SHIFT 20 | |
182 | #define SPEAR1310_I2C4_CLK_SHIFT 19 | |
183 | #define SPEAR1310_I2C3_CLK_SHIFT 18 | |
184 | #define SPEAR1310_I2C2_CLK_SHIFT 17 | |
185 | #define SPEAR1310_I2C1_CLK_SHIFT 16 | |
186 | #define SPEAR1310_GPT64_CLK_MASK 1 | |
187 | #define SPEAR1310_GPT64_CLK_SHIFT 15 | |
188 | #define SPEAR1310_RAS_UART_CLK_MASK 1 | |
189 | #define SPEAR1310_UART5_CLK_SHIFT 14 | |
190 | #define SPEAR1310_UART4_CLK_SHIFT 13 | |
191 | #define SPEAR1310_UART3_CLK_SHIFT 12 | |
192 | #define SPEAR1310_UART2_CLK_SHIFT 11 | |
193 | #define SPEAR1310_UART1_CLK_SHIFT 10 | |
194 | #define SPEAR1310_PCI_CLK_MASK 1 | |
195 | #define SPEAR1310_PCI_CLK_SHIFT 0 | |
196 | ||
d9909ebe | 197 | #define SPEAR1310_RAS_CTRL_REG1 (ras_base + 0x004) |
0b928af1 VK |
198 | #define SPEAR1310_PHY_CLK_MASK 0x3 |
199 | #define SPEAR1310_RMII_PHY_CLK_SHIFT 0 | |
200 | #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT 2 | |
201 | ||
d9909ebe | 202 | #define SPEAR1310_RAS_SW_CLK_CTRL (ras_base + 0x0148) |
0b928af1 VK |
203 | #define SPEAR1310_CAN1_CLK_ENB 25 |
204 | #define SPEAR1310_CAN0_CLK_ENB 24 | |
205 | #define SPEAR1310_GPT64_CLK_ENB 23 | |
206 | #define SPEAR1310_SSP1_CLK_ENB 22 | |
207 | #define SPEAR1310_I2C7_CLK_ENB 21 | |
208 | #define SPEAR1310_I2C6_CLK_ENB 20 | |
209 | #define SPEAR1310_I2C5_CLK_ENB 19 | |
210 | #define SPEAR1310_I2C4_CLK_ENB 18 | |
211 | #define SPEAR1310_I2C3_CLK_ENB 17 | |
212 | #define SPEAR1310_I2C2_CLK_ENB 16 | |
213 | #define SPEAR1310_I2C1_CLK_ENB 15 | |
214 | #define SPEAR1310_UART5_CLK_ENB 14 | |
215 | #define SPEAR1310_UART4_CLK_ENB 13 | |
216 | #define SPEAR1310_UART3_CLK_ENB 12 | |
217 | #define SPEAR1310_UART2_CLK_ENB 11 | |
218 | #define SPEAR1310_UART1_CLK_ENB 10 | |
219 | #define SPEAR1310_RS485_1_CLK_ENB 9 | |
220 | #define SPEAR1310_RS485_0_CLK_ENB 8 | |
221 | #define SPEAR1310_TDM2_CLK_ENB 7 | |
222 | #define SPEAR1310_TDM1_CLK_ENB 6 | |
223 | #define SPEAR1310_PCI_CLK_ENB 5 | |
224 | #define SPEAR1310_GMII_CLK_ENB 4 | |
225 | #define SPEAR1310_MII2_CLK_ENB 3 | |
226 | #define SPEAR1310_MII1_CLK_ENB 2 | |
227 | #define SPEAR1310_MII0_CLK_ENB 1 | |
228 | #define SPEAR1310_ESRAM_CLK_ENB 0 | |
229 | ||
230 | static DEFINE_SPINLOCK(_lock); | |
231 | ||
232 | /* pll rate configuration table, in ascending order of rates */ | |
233 | static struct pll_rate_tbl pll_rtbl[] = { | |
234 | /* PCLK 24MHz */ | |
235 | {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */ | |
236 | {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */ | |
237 | {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */ | |
238 | {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */ | |
239 | {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */ | |
240 | {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */ | |
241 | {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */ | |
242 | }; | |
243 | ||
244 | /* vco-pll4 rate configuration table, in ascending order of rates */ | |
245 | static struct pll_rate_tbl pll4_rtbl[] = { | |
246 | {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */ | |
247 | {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */ | |
248 | {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */ | |
249 | {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */ | |
250 | }; | |
251 | ||
252 | /* aux rate configuration table, in ascending order of rates */ | |
253 | static struct aux_rate_tbl aux_rtbl[] = { | |
254 | /* For VCO1div2 = 500 MHz */ | |
255 | {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */ | |
256 | {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */ | |
257 | {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */ | |
258 | {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */ | |
259 | {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */ | |
260 | {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */ | |
261 | }; | |
262 | ||
263 | /* gmac rate configuration table, in ascending order of rates */ | |
264 | static struct aux_rate_tbl gmac_rtbl[] = { | |
265 | /* For gmac phy input clk */ | |
266 | {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */ | |
267 | {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */ | |
268 | {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */ | |
269 | {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */ | |
270 | }; | |
271 | ||
272 | /* clcd rate configuration table, in ascending order of rates */ | |
273 | static struct frac_rate_tbl clcd_rtbl[] = { | |
274 | {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/ | |
275 | {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/ | |
276 | {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */ | |
277 | {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */ | |
278 | {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/ | |
279 | {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/ | |
280 | {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */ | |
281 | {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/ | |
282 | {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/ | |
283 | {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/ | |
284 | }; | |
285 | ||
286 | /* i2s prescaler1 masks */ | |
37d2f45d | 287 | static const struct aux_clk_masks i2s_prs1_masks = { |
0b928af1 VK |
288 | .eq_sel_mask = AUX_EQ_SEL_MASK, |
289 | .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT, | |
290 | .eq1_mask = AUX_EQ1_SEL, | |
291 | .eq2_mask = AUX_EQ2_SEL, | |
292 | .xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK, | |
293 | .xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT, | |
294 | .yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK, | |
295 | .yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT, | |
296 | }; | |
297 | ||
298 | /* i2s sclk (bit clock) syynthesizers masks */ | |
299 | static struct aux_clk_masks i2s_sclk_masks = { | |
300 | .eq_sel_mask = AUX_EQ_SEL_MASK, | |
301 | .eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT, | |
302 | .eq1_mask = AUX_EQ1_SEL, | |
303 | .eq2_mask = AUX_EQ2_SEL, | |
304 | .xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK, | |
305 | .xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT, | |
306 | .yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK, | |
307 | .yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT, | |
308 | .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB, | |
309 | }; | |
310 | ||
311 | /* i2s prs1 aux rate configuration table, in ascending order of rates */ | |
312 | static struct aux_rate_tbl i2s_prs1_rtbl[] = { | |
313 | /* For parent clk = 49.152 MHz */ | |
ef0fd0a2 DS |
314 | {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */ |
315 | {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */ | |
316 | {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */ | |
317 | {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */ | |
318 | ||
319 | /* | |
320 | * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz | |
321 | * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz | |
322 | */ | |
323 | {.xscale = 1, .yscale = 3, .eq = 0}, | |
324 | ||
325 | /* For parent clk = 49.152 MHz */ | |
326 | {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/ | |
327 | ||
0b928af1 VK |
328 | {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */ |
329 | }; | |
330 | ||
331 | /* i2s sclk aux rate configuration table, in ascending order of rates */ | |
332 | static struct aux_rate_tbl i2s_sclk_rtbl[] = { | |
333 | /* For i2s_ref_clk = 12.288MHz */ | |
334 | {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */ | |
335 | {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */ | |
336 | }; | |
337 | ||
338 | /* adc rate configuration table, in ascending order of rates */ | |
339 | /* possible adc range is 2.5 MHz to 20 MHz. */ | |
340 | static struct aux_rate_tbl adc_rtbl[] = { | |
341 | /* For ahb = 166.67 MHz */ | |
342 | {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */ | |
343 | {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */ | |
344 | {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */ | |
345 | {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */ | |
346 | }; | |
347 | ||
348 | /* General synth rate configuration table, in ascending order of rates */ | |
349 | static struct frac_rate_tbl gen_rtbl[] = { | |
350 | /* For vco1div4 = 250 MHz */ | |
351 | {.div = 0x14000}, /* 25 MHz */ | |
352 | {.div = 0x0A000}, /* 50 MHz */ | |
353 | {.div = 0x05000}, /* 100 MHz */ | |
354 | {.div = 0x02000}, /* 250 MHz */ | |
355 | }; | |
356 | ||
357 | /* clock parents */ | |
358 | static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", }; | |
359 | static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", }; | |
e28f1aa1 VKS |
360 | static const char *uart0_parents[] = { "pll5_clk", "uart_syn_gclk", }; |
361 | static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", }; | |
362 | static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk", | |
0b928af1 | 363 | "osc_25m_clk", }; |
e28f1aa1 | 364 | static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", }; |
0b928af1 | 365 | static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", }; |
e28f1aa1 | 366 | static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", }; |
0b928af1 VK |
367 | static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk", |
368 | "i2s_src_pad_clk", }; | |
e28f1aa1 | 369 | static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", }; |
0b928af1 VK |
370 | static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk", |
371 | "pll3_clk", }; | |
372 | static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk", | |
373 | "pll2_clk", }; | |
374 | static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none", | |
e28f1aa1 | 375 | "ras_pll2_clk", "ras_syn0_clk", }; |
0b928af1 | 376 | static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk", |
e28f1aa1 VKS |
377 | "ras_pll2_clk", "ras_syn0_clk", }; |
378 | static const char *uart_parents[] = { "ras_apb_clk", "gen_syn3_clk", }; | |
379 | static const char *i2c_parents[] = { "ras_apb_clk", "gen_syn1_clk", }; | |
380 | static const char *ssp1_parents[] = { "ras_apb_clk", "gen_syn1_clk", | |
0b928af1 | 381 | "ras_plclk0_clk", }; |
e28f1aa1 VKS |
382 | static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", }; |
383 | static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", }; | |
0b928af1 | 384 | |
d9909ebe | 385 | void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) |
0b928af1 VK |
386 | { |
387 | struct clk *clk, *clk1; | |
388 | ||
afb4bdc9 | 389 | clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); |
0b928af1 VK |
390 | clk_register_clkdev(clk, "osc_32k_clk", NULL); |
391 | ||
afb4bdc9 | 392 | clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000); |
0b928af1 VK |
393 | clk_register_clkdev(clk, "osc_24m_clk", NULL); |
394 | ||
afb4bdc9 | 395 | clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000); |
0b928af1 VK |
396 | clk_register_clkdev(clk, "osc_25m_clk", NULL); |
397 | ||
afb4bdc9 | 398 | clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000); |
e28f1aa1 | 399 | clk_register_clkdev(clk, "gmii_pad_clk", NULL); |
0b928af1 | 400 | |
afb4bdc9 SB |
401 | clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0, |
402 | 12288000); | |
0b928af1 VK |
403 | clk_register_clkdev(clk, "i2s_src_pad_clk", NULL); |
404 | ||
405 | /* clock derived from 32 KHz osc clk */ | |
406 | clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, | |
407 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0, | |
408 | &_lock); | |
df2449ab | 409 | clk_register_clkdev(clk, NULL, "e0580000.rtc"); |
0b928af1 VK |
410 | |
411 | /* clock derived from 24 or 25 MHz osc clk */ | |
412 | /* vco-pll */ | |
e28f1aa1 | 413 | clk = clk_register_mux(NULL, "vco1_mclk", vco_parents, |
819c1de3 JH |
414 | ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, |
415 | SPEAR1310_PLL_CFG, SPEAR1310_PLL1_CLK_SHIFT, | |
416 | SPEAR1310_PLL_CLK_MASK, 0, &_lock); | |
e28f1aa1 VKS |
417 | clk_register_clkdev(clk, "vco1_mclk", NULL); |
418 | clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", | |
0b928af1 VK |
419 | 0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl, |
420 | ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); | |
421 | clk_register_clkdev(clk, "vco1_clk", NULL); | |
422 | clk_register_clkdev(clk1, "pll1_clk", NULL); | |
423 | ||
e28f1aa1 | 424 | clk = clk_register_mux(NULL, "vco2_mclk", vco_parents, |
819c1de3 JH |
425 | ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, |
426 | SPEAR1310_PLL_CFG, SPEAR1310_PLL2_CLK_SHIFT, | |
427 | SPEAR1310_PLL_CLK_MASK, 0, &_lock); | |
e28f1aa1 VKS |
428 | clk_register_clkdev(clk, "vco2_mclk", NULL); |
429 | clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", | |
0b928af1 VK |
430 | 0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl, |
431 | ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); | |
432 | clk_register_clkdev(clk, "vco2_clk", NULL); | |
433 | clk_register_clkdev(clk1, "pll2_clk", NULL); | |
434 | ||
e28f1aa1 | 435 | clk = clk_register_mux(NULL, "vco3_mclk", vco_parents, |
819c1de3 JH |
436 | ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, |
437 | SPEAR1310_PLL_CFG, SPEAR1310_PLL3_CLK_SHIFT, | |
438 | SPEAR1310_PLL_CLK_MASK, 0, &_lock); | |
e28f1aa1 VKS |
439 | clk_register_clkdev(clk, "vco3_mclk", NULL); |
440 | clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", | |
0b928af1 VK |
441 | 0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl, |
442 | ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); | |
443 | clk_register_clkdev(clk, "vco3_clk", NULL); | |
444 | clk_register_clkdev(clk1, "pll3_clk", NULL); | |
445 | ||
446 | clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk", | |
447 | 0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl, | |
448 | ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL); | |
449 | clk_register_clkdev(clk, "vco4_clk", NULL); | |
450 | clk_register_clkdev(clk1, "pll4_clk", NULL); | |
451 | ||
452 | clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0, | |
453 | 48000000); | |
454 | clk_register_clkdev(clk, "pll5_clk", NULL); | |
455 | ||
456 | clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0, | |
457 | 25000000); | |
458 | clk_register_clkdev(clk, "pll6_clk", NULL); | |
459 | ||
460 | /* vco div n clocks */ | |
461 | clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1, | |
462 | 2); | |
463 | clk_register_clkdev(clk, "vco1div2_clk", NULL); | |
464 | ||
465 | clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1, | |
466 | 4); | |
467 | clk_register_clkdev(clk, "vco1div4_clk", NULL); | |
468 | ||
469 | clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1, | |
470 | 2); | |
471 | clk_register_clkdev(clk, "vco2div2_clk", NULL); | |
472 | ||
473 | clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1, | |
474 | 2); | |
475 | clk_register_clkdev(clk, "vco3div2_clk", NULL); | |
476 | ||
477 | /* peripherals */ | |
478 | clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1, | |
479 | 128); | |
e28f1aa1 | 480 | clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0, |
0b928af1 VK |
481 | SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0, |
482 | &_lock); | |
483 | clk_register_clkdev(clk, NULL, "spear_thermal"); | |
484 | ||
485 | /* clock derived from pll4 clk */ | |
486 | clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1, | |
487 | 1); | |
488 | clk_register_clkdev(clk, "ddr_clk", NULL); | |
489 | ||
490 | /* clock derived from pll1 clk */ | |
12499792 VKS |
491 | clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", |
492 | CLK_SET_RATE_PARENT, 1, 2); | |
0b928af1 VK |
493 | clk_register_clkdev(clk, "cpu_clk", NULL); |
494 | ||
495 | clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, | |
496 | 2); | |
497 | clk_register_clkdev(clk, NULL, "ec800620.wdt"); | |
498 | ||
cd4b519a VKS |
499 | clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1, |
500 | 2); | |
501 | clk_register_clkdev(clk, NULL, "smp_twd"); | |
502 | ||
0b928af1 VK |
503 | clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1, |
504 | 6); | |
505 | clk_register_clkdev(clk, "ahb_clk", NULL); | |
506 | ||
507 | clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1, | |
508 | 12); | |
509 | clk_register_clkdev(clk, "apb_clk", NULL); | |
510 | ||
511 | /* gpt clocks */ | |
e28f1aa1 | 512 | clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents, |
819c1de3 JH |
513 | ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, |
514 | SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT0_CLK_SHIFT, | |
515 | SPEAR1310_GPT_CLK_MASK, 0, &_lock); | |
e28f1aa1 VKS |
516 | clk_register_clkdev(clk, "gpt0_mclk", NULL); |
517 | clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0, | |
0b928af1 VK |
518 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0, |
519 | &_lock); | |
520 | clk_register_clkdev(clk, NULL, "gpt0"); | |
521 | ||
e28f1aa1 | 522 | clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents, |
819c1de3 JH |
523 | ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, |
524 | SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT1_CLK_SHIFT, | |
525 | SPEAR1310_GPT_CLK_MASK, 0, &_lock); | |
e28f1aa1 VKS |
526 | clk_register_clkdev(clk, "gpt1_mclk", NULL); |
527 | clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, | |
0b928af1 VK |
528 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0, |
529 | &_lock); | |
530 | clk_register_clkdev(clk, NULL, "gpt1"); | |
531 | ||
e28f1aa1 | 532 | clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents, |
819c1de3 JH |
533 | ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, |
534 | SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT2_CLK_SHIFT, | |
535 | SPEAR1310_GPT_CLK_MASK, 0, &_lock); | |
e28f1aa1 VKS |
536 | clk_register_clkdev(clk, "gpt2_mclk", NULL); |
537 | clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, | |
0b928af1 VK |
538 | SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0, |
539 | &_lock); | |
540 | clk_register_clkdev(clk, NULL, "gpt2"); | |
541 | ||
e28f1aa1 | 542 | clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents, |
819c1de3 JH |
543 | ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, |
544 | SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT3_CLK_SHIFT, | |
545 | SPEAR1310_GPT_CLK_MASK, 0, &_lock); | |
e28f1aa1 VKS |
546 | clk_register_clkdev(clk, "gpt3_mclk", NULL); |
547 | clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, | |
0b928af1 VK |
548 | SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0, |
549 | &_lock); | |
550 | clk_register_clkdev(clk, NULL, "gpt3"); | |
551 | ||
552 | /* others */ | |
e28f1aa1 VKS |
553 | clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk", |
554 | 0, SPEAR1310_UART_CLK_SYNT, NULL, aux_rtbl, | |
555 | ARRAY_SIZE(aux_rtbl), &_lock, &clk1); | |
556 | clk_register_clkdev(clk, "uart_syn_clk", NULL); | |
557 | clk_register_clkdev(clk1, "uart_syn_gclk", NULL); | |
0b928af1 | 558 | |
e28f1aa1 | 559 | clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, |
819c1de3 JH |
560 | ARRAY_SIZE(uart0_parents), |
561 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
12499792 VKS |
562 | SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT, |
563 | SPEAR1310_UART_CLK_MASK, 0, &_lock); | |
e28f1aa1 | 564 | clk_register_clkdev(clk, "uart0_mclk", NULL); |
0b928af1 | 565 | |
12499792 VKS |
566 | clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", |
567 | CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, | |
568 | SPEAR1310_UART_CLK_ENB, 0, &_lock); | |
0b928af1 VK |
569 | clk_register_clkdev(clk, NULL, "e0000000.serial"); |
570 | ||
e28f1aa1 | 571 | clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk", |
0b928af1 VK |
572 | "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL, |
573 | aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); | |
e28f1aa1 VKS |
574 | clk_register_clkdev(clk, "sdhci_syn_clk", NULL); |
575 | clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL); | |
0b928af1 | 576 | |
12499792 VKS |
577 | clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", |
578 | CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, | |
579 | SPEAR1310_SDHCI_CLK_ENB, 0, &_lock); | |
0b928af1 VK |
580 | clk_register_clkdev(clk, NULL, "b3000000.sdhci"); |
581 | ||
e28f1aa1 VKS |
582 | clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", |
583 | 0, SPEAR1310_CFXD_CLK_SYNT, NULL, aux_rtbl, | |
584 | ARRAY_SIZE(aux_rtbl), &_lock, &clk1); | |
585 | clk_register_clkdev(clk, "cfxd_syn_clk", NULL); | |
586 | clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL); | |
0b928af1 | 587 | |
12499792 VKS |
588 | clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", |
589 | CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, | |
590 | SPEAR1310_CFXD_CLK_ENB, 0, &_lock); | |
0b928af1 VK |
591 | clk_register_clkdev(clk, NULL, "b2800000.cf"); |
592 | clk_register_clkdev(clk, NULL, "arasan_xd"); | |
593 | ||
e28f1aa1 VKS |
594 | clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", |
595 | 0, SPEAR1310_C3_CLK_SYNT, NULL, aux_rtbl, | |
596 | ARRAY_SIZE(aux_rtbl), &_lock, &clk1); | |
597 | clk_register_clkdev(clk, "c3_syn_clk", NULL); | |
598 | clk_register_clkdev(clk1, "c3_syn_gclk", NULL); | |
0b928af1 | 599 | |
e28f1aa1 | 600 | clk = clk_register_mux(NULL, "c3_mclk", c3_parents, |
819c1de3 JH |
601 | ARRAY_SIZE(c3_parents), |
602 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
12499792 VKS |
603 | SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT, |
604 | SPEAR1310_C3_CLK_MASK, 0, &_lock); | |
e28f1aa1 | 605 | clk_register_clkdev(clk, "c3_mclk", NULL); |
0b928af1 | 606 | |
e28f1aa1 | 607 | clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0, |
0b928af1 VK |
608 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0, |
609 | &_lock); | |
610 | clk_register_clkdev(clk, NULL, "c3"); | |
611 | ||
612 | /* gmac */ | |
e28f1aa1 | 613 | clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents, |
819c1de3 JH |
614 | ARRAY_SIZE(gmac_phy_input_parents), |
615 | CLK_SET_RATE_NO_REPARENT, SPEAR1310_GMAC_CLK_CFG, | |
0b928af1 VK |
616 | SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT, |
617 | SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock); | |
e28f1aa1 | 618 | clk_register_clkdev(clk, "phy_input_mclk", NULL); |
0b928af1 | 619 | |
e28f1aa1 VKS |
620 | clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk", |
621 | 0, SPEAR1310_GMAC_CLK_SYNT, NULL, gmac_rtbl, | |
622 | ARRAY_SIZE(gmac_rtbl), &_lock, &clk1); | |
623 | clk_register_clkdev(clk, "phy_syn_clk", NULL); | |
624 | clk_register_clkdev(clk1, "phy_syn_gclk", NULL); | |
0b928af1 | 625 | |
e28f1aa1 | 626 | clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents, |
819c1de3 | 627 | ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT, |
0b928af1 VK |
628 | SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT, |
629 | SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock); | |
df2449ab | 630 | clk_register_clkdev(clk, "stmmacphy.0", NULL); |
0b928af1 VK |
631 | |
632 | /* clcd */ | |
e28f1aa1 | 633 | clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, |
819c1de3 JH |
634 | ARRAY_SIZE(clcd_synth_parents), |
635 | CLK_SET_RATE_NO_REPARENT, SPEAR1310_CLCD_CLK_SYNT, | |
636 | SPEAR1310_CLCD_SYNT_CLK_SHIFT, | |
0b928af1 | 637 | SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock); |
e28f1aa1 | 638 | clk_register_clkdev(clk, "clcd_syn_mclk", NULL); |
0b928af1 | 639 | |
e28f1aa1 | 640 | clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0, |
0b928af1 VK |
641 | SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl, |
642 | ARRAY_SIZE(clcd_rtbl), &_lock); | |
e28f1aa1 | 643 | clk_register_clkdev(clk, "clcd_syn_clk", NULL); |
0b928af1 | 644 | |
e28f1aa1 | 645 | clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, |
819c1de3 JH |
646 | ARRAY_SIZE(clcd_pixel_parents), |
647 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
0b928af1 VK |
648 | SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT, |
649 | SPEAR1310_CLCD_CLK_MASK, 0, &_lock); | |
e0b9c210 | 650 | clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); |
0b928af1 | 651 | |
e28f1aa1 | 652 | clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0, |
0b928af1 VK |
653 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0, |
654 | &_lock); | |
df2449ab | 655 | clk_register_clkdev(clk, NULL, "e1000000.clcd"); |
0b928af1 VK |
656 | |
657 | /* i2s */ | |
e28f1aa1 | 658 | clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, |
819c1de3 JH |
659 | ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT, |
660 | SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_SRC_CLK_SHIFT, | |
661 | SPEAR1310_I2S_SRC_CLK_MASK, 0, &_lock); | |
e0b9c210 | 662 | clk_register_clkdev(clk, "i2s_src_mclk", NULL); |
0b928af1 | 663 | |
e28f1aa1 | 664 | clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0, |
0b928af1 VK |
665 | SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl, |
666 | ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL); | |
667 | clk_register_clkdev(clk, "i2s_prs1_clk", NULL); | |
668 | ||
e28f1aa1 | 669 | clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, |
819c1de3 JH |
670 | ARRAY_SIZE(i2s_ref_parents), |
671 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
12499792 VKS |
672 | SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT, |
673 | SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock); | |
674 | clk_register_clkdev(clk, "i2s_ref_mclk", NULL); | |
0b928af1 | 675 | |
e28f1aa1 | 676 | clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, |
0b928af1 VK |
677 | SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB, |
678 | 0, &_lock); | |
679 | clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL); | |
680 | ||
e28f1aa1 | 681 | clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", |
463f9e20 | 682 | "i2s_ref_mclk", 0, SPEAR1310_I2S_CLK_CFG, |
0b928af1 VK |
683 | &i2s_sclk_masks, i2s_sclk_rtbl, |
684 | ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1); | |
685 | clk_register_clkdev(clk, "i2s_sclk_clk", NULL); | |
e28f1aa1 | 686 | clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL); |
0b928af1 VK |
687 | |
688 | /* clock derived from ahb clk */ | |
689 | clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, | |
690 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0, | |
691 | &_lock); | |
692 | clk_register_clkdev(clk, NULL, "e0280000.i2c"); | |
693 | ||
694 | clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, | |
695 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0, | |
696 | &_lock); | |
697 | clk_register_clkdev(clk, NULL, "ea800000.dma"); | |
698 | clk_register_clkdev(clk, NULL, "eb000000.dma"); | |
699 | ||
700 | clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, | |
701 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0, | |
702 | &_lock); | |
703 | clk_register_clkdev(clk, NULL, "b2000000.jpeg"); | |
704 | ||
705 | clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, | |
706 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0, | |
707 | &_lock); | |
708 | clk_register_clkdev(clk, NULL, "e2000000.eth"); | |
709 | ||
710 | clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, | |
711 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0, | |
712 | &_lock); | |
713 | clk_register_clkdev(clk, NULL, "b0000000.flash"); | |
714 | ||
715 | clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, | |
716 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0, | |
717 | &_lock); | |
718 | clk_register_clkdev(clk, NULL, "ea000000.flash"); | |
719 | ||
720 | clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0, | |
721 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0, | |
722 | &_lock); | |
df2449ab RK |
723 | clk_register_clkdev(clk, NULL, "e4000000.ohci"); |
724 | clk_register_clkdev(clk, NULL, "e4800000.ehci"); | |
0b928af1 VK |
725 | |
726 | clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0, | |
727 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0, | |
728 | &_lock); | |
df2449ab RK |
729 | clk_register_clkdev(clk, NULL, "e5000000.ohci"); |
730 | clk_register_clkdev(clk, NULL, "e5800000.ehci"); | |
0b928af1 VK |
731 | |
732 | clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0, | |
733 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0, | |
734 | &_lock); | |
df2449ab | 735 | clk_register_clkdev(clk, NULL, "e3800000.otg"); |
0b928af1 VK |
736 | |
737 | clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0, | |
738 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB, | |
739 | 0, &_lock); | |
22a69230 | 740 | clk_register_clkdev(clk, NULL, "b1000000.pcie"); |
df2449ab | 741 | clk_register_clkdev(clk, NULL, "b1000000.ahci"); |
0b928af1 VK |
742 | |
743 | clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0, | |
744 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB, | |
745 | 0, &_lock); | |
22a69230 | 746 | clk_register_clkdev(clk, NULL, "b1800000.pcie"); |
df2449ab | 747 | clk_register_clkdev(clk, NULL, "b1800000.ahci"); |
0b928af1 VK |
748 | |
749 | clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0, | |
750 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB, | |
751 | 0, &_lock); | |
22a69230 | 752 | clk_register_clkdev(clk, NULL, "b4000000.pcie"); |
df2449ab | 753 | clk_register_clkdev(clk, NULL, "b4000000.ahci"); |
0b928af1 VK |
754 | |
755 | clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, | |
756 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0, | |
757 | &_lock); | |
758 | clk_register_clkdev(clk, "sysram0_clk", NULL); | |
759 | ||
760 | clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0, | |
761 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0, | |
762 | &_lock); | |
763 | clk_register_clkdev(clk, "sysram1_clk", NULL); | |
764 | ||
e28f1aa1 | 765 | clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk", |
0b928af1 VK |
766 | 0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl, |
767 | ARRAY_SIZE(adc_rtbl), &_lock, &clk1); | |
e28f1aa1 VKS |
768 | clk_register_clkdev(clk, "adc_syn_clk", NULL); |
769 | clk_register_clkdev(clk1, "adc_syn_gclk", NULL); | |
0b928af1 | 770 | |
12499792 VKS |
771 | clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", |
772 | CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, | |
773 | SPEAR1310_ADC_CLK_ENB, 0, &_lock); | |
df2449ab | 774 | clk_register_clkdev(clk, NULL, "e0080000.adc"); |
0b928af1 VK |
775 | |
776 | /* clock derived from apb clk */ | |
777 | clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, | |
778 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0, | |
779 | &_lock); | |
780 | clk_register_clkdev(clk, NULL, "e0100000.spi"); | |
781 | ||
782 | clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, | |
783 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0, | |
784 | &_lock); | |
785 | clk_register_clkdev(clk, NULL, "e0600000.gpio"); | |
786 | ||
787 | clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, | |
788 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0, | |
789 | &_lock); | |
790 | clk_register_clkdev(clk, NULL, "e0680000.gpio"); | |
791 | ||
792 | clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0, | |
793 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0, | |
794 | &_lock); | |
795 | clk_register_clkdev(clk, NULL, "e0180000.i2s"); | |
796 | ||
797 | clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0, | |
798 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0, | |
799 | &_lock); | |
800 | clk_register_clkdev(clk, NULL, "e0200000.i2s"); | |
801 | ||
802 | clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0, | |
803 | SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0, | |
804 | &_lock); | |
805 | clk_register_clkdev(clk, NULL, "e0300000.kbd"); | |
806 | ||
807 | /* RAS clks */ | |
e28f1aa1 | 808 | clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, |
819c1de3 JH |
809 | ARRAY_SIZE(gen_synth0_1_parents), |
810 | CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG, | |
e28f1aa1 | 811 | SPEAR1310_RAS_SYNT0_1_CLK_SHIFT, |
0b928af1 | 812 | SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); |
e28f1aa1 | 813 | clk_register_clkdev(clk, "gen_syn0_1_clk", NULL); |
0b928af1 | 814 | |
e28f1aa1 | 815 | clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents, |
819c1de3 JH |
816 | ARRAY_SIZE(gen_synth2_3_parents), |
817 | CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG, | |
e28f1aa1 | 818 | SPEAR1310_RAS_SYNT2_3_CLK_SHIFT, |
0b928af1 | 819 | SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); |
e28f1aa1 | 820 | clk_register_clkdev(clk, "gen_syn2_3_clk", NULL); |
0b928af1 | 821 | |
e28f1aa1 | 822 | clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0, |
0b928af1 VK |
823 | SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl), |
824 | &_lock); | |
e28f1aa1 | 825 | clk_register_clkdev(clk, "gen_syn0_clk", NULL); |
0b928af1 | 826 | |
e28f1aa1 | 827 | clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0, |
0b928af1 VK |
828 | SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl), |
829 | &_lock); | |
e28f1aa1 | 830 | clk_register_clkdev(clk, "gen_syn1_clk", NULL); |
0b928af1 | 831 | |
e28f1aa1 | 832 | clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0, |
0b928af1 VK |
833 | SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl), |
834 | &_lock); | |
e28f1aa1 | 835 | clk_register_clkdev(clk, "gen_syn2_clk", NULL); |
0b928af1 | 836 | |
e28f1aa1 | 837 | clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0, |
0b928af1 VK |
838 | SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl), |
839 | &_lock); | |
e28f1aa1 | 840 | clk_register_clkdev(clk, "gen_syn3_clk", NULL); |
0b928af1 VK |
841 | |
842 | clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0, | |
843 | SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0, | |
844 | &_lock); | |
845 | clk_register_clkdev(clk, "ras_osc_24m_clk", NULL); | |
846 | ||
847 | clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0, | |
848 | SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0, | |
849 | &_lock); | |
850 | clk_register_clkdev(clk, "ras_osc_25m_clk", NULL); | |
851 | ||
852 | clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0, | |
853 | SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0, | |
854 | &_lock); | |
855 | clk_register_clkdev(clk, "ras_osc_32k_clk", NULL); | |
856 | ||
857 | clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0, | |
858 | SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0, | |
859 | &_lock); | |
860 | clk_register_clkdev(clk, "ras_pll2_clk", NULL); | |
861 | ||
862 | clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0, | |
863 | SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0, | |
864 | &_lock); | |
865 | clk_register_clkdev(clk, "ras_pll3_clk", NULL); | |
866 | ||
e28f1aa1 | 867 | clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_pad_clk", 0, |
0b928af1 VK |
868 | SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0, |
869 | &_lock); | |
870 | clk_register_clkdev(clk, "ras_tx125_clk", NULL); | |
871 | ||
872 | clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0, | |
873 | 30000000); | |
874 | clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0, | |
875 | SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0, | |
876 | &_lock); | |
877 | clk_register_clkdev(clk, "ras_30m_clk", NULL); | |
878 | ||
879 | clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0, | |
880 | 48000000); | |
881 | clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0, | |
882 | SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0, | |
883 | &_lock); | |
884 | clk_register_clkdev(clk, "ras_48m_clk", NULL); | |
885 | ||
886 | clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, | |
887 | SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0, | |
888 | &_lock); | |
889 | clk_register_clkdev(clk, "ras_ahb_clk", NULL); | |
890 | ||
891 | clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, | |
892 | SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0, | |
893 | &_lock); | |
894 | clk_register_clkdev(clk, "ras_apb_clk", NULL); | |
895 | ||
afb4bdc9 | 896 | clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, 0, |
0b928af1 VK |
897 | 50000000); |
898 | ||
afb4bdc9 | 899 | clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, 0, 50000000); |
0b928af1 VK |
900 | |
901 | clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0, | |
902 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0, | |
903 | &_lock); | |
904 | clk_register_clkdev(clk, NULL, "c_can_platform.0"); | |
905 | ||
906 | clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0, | |
907 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0, | |
908 | &_lock); | |
909 | clk_register_clkdev(clk, NULL, "c_can_platform.1"); | |
910 | ||
911 | clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0, | |
912 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0, | |
913 | &_lock); | |
914 | clk_register_clkdev(clk, NULL, "5c400000.eth"); | |
915 | ||
916 | clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0, | |
917 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0, | |
918 | &_lock); | |
919 | clk_register_clkdev(clk, NULL, "5c500000.eth"); | |
920 | ||
921 | clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0, | |
922 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0, | |
923 | &_lock); | |
924 | clk_register_clkdev(clk, NULL, "5c600000.eth"); | |
925 | ||
926 | clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0, | |
927 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0, | |
928 | &_lock); | |
929 | clk_register_clkdev(clk, NULL, "5c700000.eth"); | |
930 | ||
e28f1aa1 | 931 | clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk", |
0b928af1 | 932 | smii_rgmii_phy_parents, |
819c1de3 JH |
933 | ARRAY_SIZE(smii_rgmii_phy_parents), |
934 | CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG1, | |
0b928af1 VK |
935 | SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT, |
936 | SPEAR1310_PHY_CLK_MASK, 0, &_lock); | |
df2449ab RK |
937 | clk_register_clkdev(clk, "stmmacphy.1", NULL); |
938 | clk_register_clkdev(clk, "stmmacphy.2", NULL); | |
939 | clk_register_clkdev(clk, "stmmacphy.4", NULL); | |
0b928af1 | 940 | |
e28f1aa1 | 941 | clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents, |
819c1de3 | 942 | ARRAY_SIZE(rmii_phy_parents), CLK_SET_RATE_NO_REPARENT, |
0b928af1 VK |
943 | SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT, |
944 | SPEAR1310_PHY_CLK_MASK, 0, &_lock); | |
df2449ab | 945 | clk_register_clkdev(clk, "stmmacphy.3", NULL); |
0b928af1 | 946 | |
e28f1aa1 | 947 | clk = clk_register_mux(NULL, "uart1_mclk", uart_parents, |
819c1de3 JH |
948 | ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, |
949 | SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART1_CLK_SHIFT, | |
950 | SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); | |
e28f1aa1 | 951 | clk_register_clkdev(clk, "uart1_mclk", NULL); |
0b928af1 | 952 | |
e28f1aa1 | 953 | clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0, |
0b928af1 VK |
954 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0, |
955 | &_lock); | |
956 | clk_register_clkdev(clk, NULL, "5c800000.serial"); | |
957 | ||
e28f1aa1 | 958 | clk = clk_register_mux(NULL, "uart2_mclk", uart_parents, |
819c1de3 JH |
959 | ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, |
960 | SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART2_CLK_SHIFT, | |
961 | SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); | |
e28f1aa1 | 962 | clk_register_clkdev(clk, "uart2_mclk", NULL); |
0b928af1 | 963 | |
e28f1aa1 | 964 | clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0, |
0b928af1 VK |
965 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0, |
966 | &_lock); | |
967 | clk_register_clkdev(clk, NULL, "5c900000.serial"); | |
968 | ||
e28f1aa1 | 969 | clk = clk_register_mux(NULL, "uart3_mclk", uart_parents, |
819c1de3 JH |
970 | ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, |
971 | SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART3_CLK_SHIFT, | |
972 | SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); | |
e28f1aa1 | 973 | clk_register_clkdev(clk, "uart3_mclk", NULL); |
0b928af1 | 974 | |
e28f1aa1 | 975 | clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0, |
0b928af1 VK |
976 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0, |
977 | &_lock); | |
978 | clk_register_clkdev(clk, NULL, "5ca00000.serial"); | |
979 | ||
e28f1aa1 | 980 | clk = clk_register_mux(NULL, "uart4_mclk", uart_parents, |
819c1de3 JH |
981 | ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, |
982 | SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART4_CLK_SHIFT, | |
983 | SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); | |
e28f1aa1 | 984 | clk_register_clkdev(clk, "uart4_mclk", NULL); |
0b928af1 | 985 | |
e28f1aa1 | 986 | clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0, |
0b928af1 VK |
987 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0, |
988 | &_lock); | |
989 | clk_register_clkdev(clk, NULL, "5cb00000.serial"); | |
990 | ||
e28f1aa1 | 991 | clk = clk_register_mux(NULL, "uart5_mclk", uart_parents, |
819c1de3 JH |
992 | ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, |
993 | SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART5_CLK_SHIFT, | |
994 | SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); | |
e28f1aa1 | 995 | clk_register_clkdev(clk, "uart5_mclk", NULL); |
0b928af1 | 996 | |
e28f1aa1 | 997 | clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0, |
0b928af1 VK |
998 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0, |
999 | &_lock); | |
1000 | clk_register_clkdev(clk, NULL, "5cc00000.serial"); | |
1001 | ||
e28f1aa1 | 1002 | clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents, |
819c1de3 JH |
1003 | ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, |
1004 | SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C1_CLK_SHIFT, | |
1005 | SPEAR1310_I2C_CLK_MASK, 0, &_lock); | |
e28f1aa1 | 1006 | clk_register_clkdev(clk, "i2c1_mclk", NULL); |
0b928af1 | 1007 | |
e28f1aa1 | 1008 | clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0, |
0b928af1 VK |
1009 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0, |
1010 | &_lock); | |
1011 | clk_register_clkdev(clk, NULL, "5cd00000.i2c"); | |
1012 | ||
e28f1aa1 | 1013 | clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents, |
819c1de3 JH |
1014 | ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, |
1015 | SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C2_CLK_SHIFT, | |
1016 | SPEAR1310_I2C_CLK_MASK, 0, &_lock); | |
e28f1aa1 | 1017 | clk_register_clkdev(clk, "i2c2_mclk", NULL); |
0b928af1 | 1018 | |
e28f1aa1 | 1019 | clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0, |
0b928af1 VK |
1020 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0, |
1021 | &_lock); | |
1022 | clk_register_clkdev(clk, NULL, "5ce00000.i2c"); | |
1023 | ||
e28f1aa1 | 1024 | clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents, |
819c1de3 JH |
1025 | ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, |
1026 | SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C3_CLK_SHIFT, | |
1027 | SPEAR1310_I2C_CLK_MASK, 0, &_lock); | |
e28f1aa1 | 1028 | clk_register_clkdev(clk, "i2c3_mclk", NULL); |
0b928af1 | 1029 | |
e28f1aa1 | 1030 | clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0, |
0b928af1 VK |
1031 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0, |
1032 | &_lock); | |
1033 | clk_register_clkdev(clk, NULL, "5cf00000.i2c"); | |
1034 | ||
e28f1aa1 | 1035 | clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents, |
819c1de3 JH |
1036 | ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, |
1037 | SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C4_CLK_SHIFT, | |
1038 | SPEAR1310_I2C_CLK_MASK, 0, &_lock); | |
e28f1aa1 | 1039 | clk_register_clkdev(clk, "i2c4_mclk", NULL); |
0b928af1 | 1040 | |
e28f1aa1 | 1041 | clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0, |
0b928af1 VK |
1042 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0, |
1043 | &_lock); | |
1044 | clk_register_clkdev(clk, NULL, "5d000000.i2c"); | |
1045 | ||
e28f1aa1 | 1046 | clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents, |
819c1de3 JH |
1047 | ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, |
1048 | SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C5_CLK_SHIFT, | |
1049 | SPEAR1310_I2C_CLK_MASK, 0, &_lock); | |
e28f1aa1 | 1050 | clk_register_clkdev(clk, "i2c5_mclk", NULL); |
0b928af1 | 1051 | |
e28f1aa1 | 1052 | clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0, |
0b928af1 VK |
1053 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0, |
1054 | &_lock); | |
1055 | clk_register_clkdev(clk, NULL, "5d100000.i2c"); | |
1056 | ||
e28f1aa1 | 1057 | clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents, |
819c1de3 JH |
1058 | ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, |
1059 | SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C6_CLK_SHIFT, | |
1060 | SPEAR1310_I2C_CLK_MASK, 0, &_lock); | |
e28f1aa1 | 1061 | clk_register_clkdev(clk, "i2c6_mclk", NULL); |
0b928af1 | 1062 | |
e28f1aa1 | 1063 | clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0, |
0b928af1 VK |
1064 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0, |
1065 | &_lock); | |
1066 | clk_register_clkdev(clk, NULL, "5d200000.i2c"); | |
1067 | ||
e28f1aa1 | 1068 | clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents, |
819c1de3 JH |
1069 | ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, |
1070 | SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C7_CLK_SHIFT, | |
1071 | SPEAR1310_I2C_CLK_MASK, 0, &_lock); | |
e28f1aa1 | 1072 | clk_register_clkdev(clk, "i2c7_mclk", NULL); |
0b928af1 | 1073 | |
e28f1aa1 | 1074 | clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0, |
0b928af1 VK |
1075 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0, |
1076 | &_lock); | |
1077 | clk_register_clkdev(clk, NULL, "5d300000.i2c"); | |
1078 | ||
e28f1aa1 | 1079 | clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents, |
819c1de3 JH |
1080 | ARRAY_SIZE(ssp1_parents), CLK_SET_RATE_NO_REPARENT, |
1081 | SPEAR1310_RAS_CTRL_REG0, SPEAR1310_SSP1_CLK_SHIFT, | |
1082 | SPEAR1310_SSP1_CLK_MASK, 0, &_lock); | |
e28f1aa1 | 1083 | clk_register_clkdev(clk, "ssp1_mclk", NULL); |
0b928af1 | 1084 | |
e28f1aa1 | 1085 | clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0, |
0b928af1 VK |
1086 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0, |
1087 | &_lock); | |
1088 | clk_register_clkdev(clk, NULL, "5d400000.spi"); | |
1089 | ||
e28f1aa1 | 1090 | clk = clk_register_mux(NULL, "pci_mclk", pci_parents, |
819c1de3 JH |
1091 | ARRAY_SIZE(pci_parents), CLK_SET_RATE_NO_REPARENT, |
1092 | SPEAR1310_RAS_CTRL_REG0, SPEAR1310_PCI_CLK_SHIFT, | |
1093 | SPEAR1310_PCI_CLK_MASK, 0, &_lock); | |
e28f1aa1 | 1094 | clk_register_clkdev(clk, "pci_mclk", NULL); |
0b928af1 | 1095 | |
e28f1aa1 | 1096 | clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0, |
0b928af1 VK |
1097 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0, |
1098 | &_lock); | |
1099 | clk_register_clkdev(clk, NULL, "pci"); | |
1100 | ||
e28f1aa1 | 1101 | clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents, |
819c1de3 JH |
1102 | ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT, |
1103 | SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM1_CLK_SHIFT, | |
1104 | SPEAR1310_TDM_CLK_MASK, 0, &_lock); | |
e28f1aa1 | 1105 | clk_register_clkdev(clk, "tdm1_mclk", NULL); |
0b928af1 | 1106 | |
e28f1aa1 | 1107 | clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0, |
0b928af1 VK |
1108 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0, |
1109 | &_lock); | |
1110 | clk_register_clkdev(clk, NULL, "tdm_hdlc.0"); | |
1111 | ||
e28f1aa1 | 1112 | clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents, |
819c1de3 JH |
1113 | ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT, |
1114 | SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM2_CLK_SHIFT, | |
1115 | SPEAR1310_TDM_CLK_MASK, 0, &_lock); | |
e28f1aa1 | 1116 | clk_register_clkdev(clk, "tdm2_mclk", NULL); |
0b928af1 | 1117 | |
e28f1aa1 | 1118 | clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0, |
0b928af1 VK |
1119 | SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0, |
1120 | &_lock); | |
1121 | clk_register_clkdev(clk, NULL, "tdm_hdlc.1"); | |
1122 | } |