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a636cd6c | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
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2 | /* |
3 | * Clock tree for CSR SiRFprimaII | |
4 | * | |
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5 | * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group |
6 | * company. | |
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7 | */ |
8 | ||
9 | #include <linux/module.h> | |
10 | #include <linux/bitops.h> | |
11 | #include <linux/io.h> | |
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12 | #include <linux/clkdev.h> |
13 | #include <linux/clk-provider.h> | |
14 | #include <linux/of_address.h> | |
15 | #include <linux/syscore_ops.h> | |
16 | ||
17 | #include "prima2.h" | |
18 | #include "clk-common.c" | |
19 | ||
20 | static struct clk_dmn clk_mmc01 = { | |
21 | .regofs = SIRFSOC_CLKC_MMC_CFG, | |
22 | .enable_bit = 59, | |
23 | .hw = { | |
24 | .init = &clk_mmc01_init, | |
25 | }, | |
26 | }; | |
27 | ||
28 | static struct clk_dmn clk_mmc23 = { | |
29 | .regofs = SIRFSOC_CLKC_MMC_CFG, | |
30 | .enable_bit = 60, | |
31 | .hw = { | |
32 | .init = &clk_mmc23_init, | |
33 | }, | |
34 | }; | |
35 | ||
36 | static struct clk_dmn clk_mmc45 = { | |
37 | .regofs = SIRFSOC_CLKC_MMC_CFG, | |
38 | .enable_bit = 61, | |
39 | .hw = { | |
40 | .init = &clk_mmc45_init, | |
41 | }, | |
42 | }; | |
43 | ||
0777066d | 44 | static const struct clk_init_data clk_nand_init = { |
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45 | .name = "nand", |
46 | .ops = &ios_ops, | |
47 | .parent_names = std_clk_io_parents, | |
48 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
49 | }; | |
50 | ||
51 | static struct clk_std clk_nand = { | |
52 | .enable_bit = 34, | |
53 | .hw = { | |
54 | .init = &clk_nand_init, | |
55 | }, | |
56 | }; | |
57 | ||
58 | enum prima2_clk_index { | |
59 | /* 0 1 2 3 4 5 6 7 8 9 */ | |
60 | rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, | |
61 | mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0, | |
62 | spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1, | |
63 | usp2, vip, gfx, mm, lcd, vpp, mmc01, mmc23, mmc45, usbpll, | |
64 | usb0, usb1, cphif, maxclk, | |
65 | }; | |
66 | ||
67 | static __initdata struct clk_hw *prima2_clk_hw_array[maxclk] = { | |
68 | NULL, /* dummy */ | |
69 | NULL, | |
70 | &clk_pll1.hw, | |
71 | &clk_pll2.hw, | |
72 | &clk_pll3.hw, | |
73 | &clk_mem.hw, | |
74 | &clk_sys.hw, | |
75 | &clk_security.hw, | |
76 | &clk_dsp.hw, | |
77 | &clk_gps.hw, | |
78 | &clk_mf.hw, | |
79 | &clk_io.hw, | |
80 | &clk_cpu.hw, | |
81 | &clk_uart0.hw, | |
82 | &clk_uart1.hw, | |
83 | &clk_uart2.hw, | |
84 | &clk_tsc.hw, | |
85 | &clk_i2c0.hw, | |
86 | &clk_i2c1.hw, | |
87 | &clk_spi0.hw, | |
88 | &clk_spi1.hw, | |
89 | &clk_pwmc.hw, | |
90 | &clk_efuse.hw, | |
91 | &clk_pulse.hw, | |
92 | &clk_dmac0.hw, | |
93 | &clk_dmac1.hw, | |
94 | &clk_nand.hw, | |
95 | &clk_audio.hw, | |
96 | &clk_usp0.hw, | |
97 | &clk_usp1.hw, | |
98 | &clk_usp2.hw, | |
99 | &clk_vip.hw, | |
100 | &clk_gfx.hw, | |
101 | &clk_mm.hw, | |
102 | &clk_lcd.hw, | |
103 | &clk_vpp.hw, | |
104 | &clk_mmc01.hw, | |
105 | &clk_mmc23.hw, | |
106 | &clk_mmc45.hw, | |
107 | &usb_pll_clk_hw, | |
108 | &clk_usb0.hw, | |
109 | &clk_usb1.hw, | |
110 | &clk_cphif.hw, | |
111 | }; | |
112 | ||
113 | static struct clk *prima2_clks[maxclk]; | |
114 | ||
115 | static void __init prima2_clk_init(struct device_node *np) | |
116 | { | |
117 | struct device_node *rscnp; | |
118 | int i; | |
119 | ||
120 | rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc"); | |
121 | sirfsoc_rsc_vbase = of_iomap(rscnp, 0); | |
122 | if (!sirfsoc_rsc_vbase) | |
123 | panic("unable to map rsc registers\n"); | |
124 | of_node_put(rscnp); | |
125 | ||
126 | sirfsoc_clk_vbase = of_iomap(np, 0); | |
127 | if (!sirfsoc_clk_vbase) | |
128 | panic("unable to map clkc registers\n"); | |
129 | ||
130 | /* These are always available (RTC and 26MHz OSC)*/ | |
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131 | prima2_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL, 0, 32768); |
132 | prima2_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL, 0, | |
133 | 26000000); | |
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134 | |
135 | for (i = pll1; i < maxclk; i++) { | |
136 | prima2_clks[i] = clk_register(NULL, prima2_clk_hw_array[i]); | |
137 | BUG_ON(!prima2_clks[i]); | |
138 | } | |
139 | clk_register_clkdev(prima2_clks[cpu], NULL, "cpu"); | |
140 | clk_register_clkdev(prima2_clks[io], NULL, "io"); | |
141 | clk_register_clkdev(prima2_clks[mem], NULL, "mem"); | |
142 | clk_register_clkdev(prima2_clks[mem], NULL, "osc"); | |
143 | ||
144 | clk_data.clks = prima2_clks; | |
145 | clk_data.clk_num = maxclk; | |
146 | ||
147 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
148 | } | |
149 | CLK_OF_DECLARE(prima2_clk, "sirf,prima2-clkc", prima2_clk_init); |