projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 7bf21bc8 BS |
1 | /* |
| 2 | * Clock tree for CSR SiRFatlasVI | |
| 3 | * | |
| 77366929 BS |
4 | * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group |
| 5 | * company. | |
| 7bf21bc8 BS |
6 | * |
| 7 | * Licensed under GPLv2 or later. | |
| 8 | */ | |
| 9 | ||
| 10 | #include <linux/module.h> | |
| 11 | #include <linux/bitops.h> | |
| 12 | #include <linux/io.h> | |
| 13 | #include <linux/clk.h> | |
| 14 | #include <linux/clkdev.h> | |
| 15 | #include <linux/clk-provider.h> | |
| 16 | #include <linux/of_address.h> | |
| 17 | #include <linux/syscore_ops.h> | |
| 18 | ||
| 19 | #include "atlas6.h" | |
| 20 | #include "clk-common.c" | |
| 21 | ||
| 22 | static struct clk_dmn clk_mmc01 = { | |
| 23 | .regofs = SIRFSOC_CLKC_MMC01_CFG, | |
| 24 | .enable_bit = 59, | |
| 25 | .hw = { | |
| 26 | .init = &clk_mmc01_init, | |
| 27 | }, | |
| 28 | }; | |
| 29 | ||
| 30 | static struct clk_dmn clk_mmc23 = { | |
| 31 | .regofs = SIRFSOC_CLKC_MMC23_CFG, | |
| 32 | .enable_bit = 60, | |
| 33 | .hw = { | |
| 34 | .init = &clk_mmc23_init, | |
| 35 | }, | |
| 36 | }; | |
| 37 | ||
| 38 | static struct clk_dmn clk_mmc45 = { | |
| 39 | .regofs = SIRFSOC_CLKC_MMC45_CFG, | |
| 40 | .enable_bit = 61, | |
| 41 | .hw = { | |
| 42 | .init = &clk_mmc45_init, | |
| 43 | }, | |
| 44 | }; | |
| 45 | ||
| 46 | static struct clk_init_data clk_nand_init = { | |
| 47 | .name = "nand", | |
| 48 | .ops = &dmn_ops, | |
| 49 | .parent_names = dmn_clk_parents, | |
| 50 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | |
| 51 | }; | |
| 52 | ||
| 53 | static struct clk_dmn clk_nand = { | |
| 54 | .regofs = SIRFSOC_CLKC_NAND_CFG, | |
| 55 | .enable_bit = 34, | |
| 56 | .hw = { | |
| 57 | .init = &clk_nand_init, | |
| 58 | }, | |
| 59 | }; | |
| 60 | ||
| 61 | enum atlas6_clk_index { | |
| 62 | /* 0 1 2 3 4 5 6 7 8 9 */ | |
| 63 | rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, | |
| 64 | mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0, | |
| 65 | spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1, | |
| 66 | usp2, vip, gfx, gfx2d, lcd, vpp, mmc01, mmc23, mmc45, usbpll, | |
| 67 | usb0, usb1, cphif, maxclk, | |
| 68 | }; | |
| 69 | ||
| 70 | static __initdata struct clk_hw *atlas6_clk_hw_array[maxclk] = { | |
| 71 | NULL, /* dummy */ | |
| 72 | NULL, | |
| 73 | &clk_pll1.hw, | |
| 74 | &clk_pll2.hw, | |
| 75 | &clk_pll3.hw, | |
| 76 | &clk_mem.hw, | |
| 77 | &clk_sys.hw, | |
| 78 | &clk_security.hw, | |
| 79 | &clk_dsp.hw, | |
| 80 | &clk_gps.hw, | |
| 81 | &clk_mf.hw, | |
| 82 | &clk_io.hw, | |
| 83 | &clk_cpu.hw, | |
| 84 | &clk_uart0.hw, | |
| 85 | &clk_uart1.hw, | |
| 86 | &clk_uart2.hw, | |
| 87 | &clk_tsc.hw, | |
| 88 | &clk_i2c0.hw, | |
| 89 | &clk_i2c1.hw, | |
| 90 | &clk_spi0.hw, | |
| 91 | &clk_spi1.hw, | |
| 92 | &clk_pwmc.hw, | |
| 93 | &clk_efuse.hw, | |
| 94 | &clk_pulse.hw, | |
| 95 | &clk_dmac0.hw, | |
| 96 | &clk_dmac1.hw, | |
| 97 | &clk_nand.hw, | |
| 98 | &clk_audio.hw, | |
| 99 | &clk_usp0.hw, | |
| 100 | &clk_usp1.hw, | |
| 101 | &clk_usp2.hw, | |
| 102 | &clk_vip.hw, | |
| 103 | &clk_gfx.hw, | |
| 104 | &clk_gfx2d.hw, | |
| 105 | &clk_lcd.hw, | |
| 106 | &clk_vpp.hw, | |
| 107 | &clk_mmc01.hw, | |
| 108 | &clk_mmc23.hw, | |
| 109 | &clk_mmc45.hw, | |
| 110 | &usb_pll_clk_hw, | |
| 111 | &clk_usb0.hw, | |
| 112 | &clk_usb1.hw, | |
| 113 | &clk_cphif.hw, | |
| 114 | }; | |
| 115 | ||
| 116 | static struct clk *atlas6_clks[maxclk]; | |
| 117 | ||
| 118 | static void __init atlas6_clk_init(struct device_node *np) | |
| 119 | { | |
| 120 | struct device_node *rscnp; | |
| 121 | int i; | |
| 122 | ||
| 123 | rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc"); | |
| 124 | sirfsoc_rsc_vbase = of_iomap(rscnp, 0); | |
| 125 | if (!sirfsoc_rsc_vbase) | |
| 126 | panic("unable to map rsc registers\n"); | |
| 127 | of_node_put(rscnp); | |
| 128 | ||
| 129 | sirfsoc_clk_vbase = of_iomap(np, 0); | |
| 130 | if (!sirfsoc_clk_vbase) | |
| 131 | panic("unable to map clkc registers\n"); | |
| 132 | ||
| 133 | /* These are always available (RTC and 26MHz OSC)*/ | |
| 134 | atlas6_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL, | |
| 135 | CLK_IS_ROOT, 32768); | |
| 136 | atlas6_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL, | |
| 137 | CLK_IS_ROOT, 26000000); | |
| 138 | ||
| 139 | for (i = pll1; i < maxclk; i++) { | |
| 140 | atlas6_clks[i] = clk_register(NULL, atlas6_clk_hw_array[i]); | |
| 141 | BUG_ON(!atlas6_clks[i]); | |
| 142 | } | |
| 143 | clk_register_clkdev(atlas6_clks[cpu], NULL, "cpu"); | |
| 144 | clk_register_clkdev(atlas6_clks[io], NULL, "io"); | |
| 145 | clk_register_clkdev(atlas6_clks[mem], NULL, "mem"); | |
| 146 | clk_register_clkdev(atlas6_clks[mem], NULL, "osc"); | |
| 147 | ||
| 148 | clk_data.clks = atlas6_clks; | |
| 149 | clk_data.clk_num = maxclk; | |
| 150 | ||
| 151 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
| 152 | } | |
| 153 | CLK_OF_DECLARE(atlas6_clk, "sirf,atlas6-clkc", atlas6_clk_init); |