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clk: shmobile: r8a7795: Add SD divider support
[linux-2.6-block.git] / drivers / clk / shmobile / r8a7795-cpg-mssr.c
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c5dae0df
GU		 1/*
2 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
3 *
4 * Copyright (C) 2015 Glider bvba
5 *
6 * Based on clk-rcar-gen3.c
7 *
8 * Copyright (C) 2015 Renesas Electronics Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 */
14
15#include <linux/bug.h>
16#include <linux/clk-provider.h>
17#include <linux/device.h>
18#include <linux/err.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/kernel.h>
22#include <linux/of.h>
90c073e5 23#include <linux/slab.h>
c5dae0df
GU		 24
25#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
26
27#include "renesas-cpg-mssr.h"
28
29
30enum clk_ids {
31 /* Core Clock Outputs exported to DT */
32 LAST_DT_CORE_CLK = R8A7795_CLK_OSC,
33
34 /* External Input Clocks */
35 CLK_EXTAL,
36 CLK_EXTALR,
37
38 /* Internal Core Clocks */
39 CLK_MAIN,
40 CLK_PLL0,
41 CLK_PLL1,
42 CLK_PLL2,
43 CLK_PLL3,
44 CLK_PLL4,
45 CLK_PLL1_DIV2,
46 CLK_PLL1_DIV4,
47 CLK_S0,
48 CLK_S1,
49 CLK_S2,
50 CLK_S3,
51 CLK_SDSRC,
52 CLK_SSPSRC,
53
54 /* Module Clocks */
55 MOD_CLK_BASE
56};
57
58enum r8a7795_clk_types {
59 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
60 CLK_TYPE_GEN3_PLL0,
61 CLK_TYPE_GEN3_PLL1,
62 CLK_TYPE_GEN3_PLL2,
63 CLK_TYPE_GEN3_PLL3,
64 CLK_TYPE_GEN3_PLL4,
90c073e5 65 CLK_TYPE_GEN3_SD,
c5dae0df
GU		 66};
67
68static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
69 /* External Clock Inputs */
70 DEF_INPUT("extal", CLK_EXTAL),
71 DEF_INPUT("extalr", CLK_EXTALR),
72
73 /* Internal Core Clocks */
74 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
75 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
76 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
77 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
78 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
79 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
80
81 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
82 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
83 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
84 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
85 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
86 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
87
88 /* Core Clock Outputs */
89 DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
90 DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
91 DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
92 DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
93 DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
94 DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
95 DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
96 DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
97 DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
98 DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
99 DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
100 DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
101 DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
102 DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
103 DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
90c073e5
DB		 104
105 DEF_SD("sd0", R8A7795_CLK_SD0, CLK_PLL1_DIV2, 0x0074),
106 DEF_SD("sd1", R8A7795_CLK_SD1, CLK_PLL1_DIV2, 0x0078),
107 DEF_SD("sd2", R8A7795_CLK_SD2, CLK_PLL1_DIV2, 0x0268),
108 DEF_SD("sd3", R8A7795_CLK_SD3, CLK_PLL1_DIV2, 0x026c),
109
c5dae0df
GU		 110 DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
111 DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
112
113 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
114 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),
115};
116
117static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
118 DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
119 DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
120 DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
121 DEF_MOD("scif1", 206, R8A7795_CLK_S3D4),
122 DEF_MOD("scif0", 207, R8A7795_CLK_S3D4),
123 DEF_MOD("msiof3", 208, R8A7795_CLK_MSO),
124 DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
125 DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
126 DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
127 DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
128 DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1),
129 DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S3D1),
130 DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
90c073e5
DB		 131 DEF_MOD("sdif3", 311, R8A7795_CLK_SD3),
132 DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
133 DEF_MOD("sdif1", 313, R8A7795_CLK_SD1),
134 DEF_MOD("sdif0", 314, R8A7795_CLK_SD0),
c5dae0df
GU		 135 DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
136 DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
b7c9b91d
YS		 137 DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1),
138 DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
c5dae0df
GU		 139 DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
140 DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4),
141 DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4),
142 DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
143 DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
144 DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
145 DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
146 DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
147 DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1),
148 DEF_MOD("vspd2", 621, R8A7795_CLK_S2D1),
149 DEF_MOD("vspd1", 622, R8A7795_CLK_S2D1),
150 DEF_MOD("vspd0", 623, R8A7795_CLK_S2D1),
151 DEF_MOD("vspbc", 624, R8A7795_CLK_S2D1),
152 DEF_MOD("vspbd", 626, R8A7795_CLK_S2D1),
153 DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1),
154 DEF_MOD("vspi1", 630, R8A7795_CLK_S2D1),
155 DEF_MOD("vspi0", 631, R8A7795_CLK_S2D1),
156 DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
157 DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
158 DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
159 DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
160 DEF_MOD("du3", 721, R8A7795_CLK_S2D1),
161 DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
162 DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
163 DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
164 DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
165 DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
166 DEF_MOD("etheravb", 812, R8A7795_CLK_S3D2),
c1c5864d 167 DEF_MOD("sata0", 815, R8A7795_CLK_S3D2),
c5dae0df
GU		 168 DEF_MOD("gpio7", 905, R8A7795_CLK_CP),
169 DEF_MOD("gpio6", 906, R8A7795_CLK_CP),
170 DEF_MOD("gpio5", 907, R8A7795_CLK_CP),
171 DEF_MOD("gpio4", 908, R8A7795_CLK_CP),
172 DEF_MOD("gpio3", 909, R8A7795_CLK_CP),
173 DEF_MOD("gpio2", 910, R8A7795_CLK_CP),
174 DEF_MOD("gpio1", 911, R8A7795_CLK_CP),
175 DEF_MOD("gpio0", 912, R8A7795_CLK_CP),
176 DEF_MOD("i2c6", 918, R8A7795_CLK_S3D2),
177 DEF_MOD("i2c5", 919, R8A7795_CLK_S3D2),
178 DEF_MOD("i2c4", 927, R8A7795_CLK_S3D2),
179 DEF_MOD("i2c3", 928, R8A7795_CLK_S3D2),
180 DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
181 DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
182 DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
183 DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
184 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
185 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
186 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
187 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
188 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
189 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
190 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
191 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
192 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
193 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
194 DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
195 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
196 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
197 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
198 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
199 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
200 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
201 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
202 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
203 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
204 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
205 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
206 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
207 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
208 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
209};
210
211static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
212 MOD_CLK_ID(408), /* INTC-AP (GIC) */
213};
214
90c073e5
DB		 215/* -----------------------------------------------------------------------------
216 * SDn Clock
217 *
218 */
219#define CPG_SD_STP_HCK BIT(9)
220#define CPG_SD_STP_CK BIT(8)
221
222#define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
223#define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
224
225#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
226{ \
227 .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
228 ((stp_ck) ? CPG_SD_STP_CK : 0) | \
229 ((sd_srcfc) << 2) | \
230 ((sd_fc) << 0), \
231 .div = (sd_div), \
232}
233
234struct sd_div_table {
235 u32 val;
236 unsigned int div;
237};
238
239struct sd_clock {
240 struct clk_hw hw;
241 void __iomem *reg;
242 const struct sd_div_table *div_table;
243 unsigned int div_num;
244 unsigned int div_min;
245 unsigned int div_max;
246};
247
248/* SDn divider
249 * sd_srcfc sd_fc div
250 * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
251 *-------------------------------------------------------------------
252 * 0 0 0 (1) 1 (4) 4
253 * 0 0 1 (2) 1 (4) 8
254 * 1 0 2 (4) 1 (4) 16
255 * 1 0 3 (8) 1 (4) 32
256 * 1 0 4 (16) 1 (4) 64
257 * 0 0 0 (1) 0 (2) 2
258 * 0 0 1 (2) 0 (2) 4
259 * 1 0 2 (4) 0 (2) 8
260 * 1 0 3 (8) 0 (2) 16
261 * 1 0 4 (16) 0 (2) 32
262 */
263static const struct sd_div_table cpg_sd_div_table[] = {
264/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
265 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
266 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
267 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
268 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
269 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
270 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
271 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
272 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
273 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
274 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
275};
276
277#define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
278
279static int cpg_sd_clock_enable(struct clk_hw *hw)
280{
281 struct sd_clock *clock = to_sd_clock(hw);
282 u32 val, sd_fc;
283 unsigned int i;
284
285 val = clk_readl(clock->reg);
286
287 sd_fc = val & CPG_SD_FC_MASK;
288 for (i = 0; i < clock->div_num; i++)
289 if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
290 break;
291
292 if (i >= clock->div_num)
293 return -EINVAL;
294
295 val &= ~(CPG_SD_STP_MASK);
296 val |= clock->div_table[i].val & CPG_SD_STP_MASK;
297
298 clk_writel(val, clock->reg);
299
300 return 0;
301}
302
303static void cpg_sd_clock_disable(struct clk_hw *hw)
304{
305 struct sd_clock *clock = to_sd_clock(hw);
306
307 clk_writel(clk_readl(clock->reg) | CPG_SD_STP_MASK, clock->reg);
308}
309
310static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
311{
312 struct sd_clock *clock = to_sd_clock(hw);
313
314 return !(clk_readl(clock->reg) & CPG_SD_STP_MASK);
315}
316
317static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
318 unsigned long parent_rate)
319{
320 struct sd_clock *clock = to_sd_clock(hw);
321 unsigned long rate = parent_rate;
322 u32 val, sd_fc;
323 unsigned int i;
324
325 val = clk_readl(clock->reg);
326
327 sd_fc = val & CPG_SD_FC_MASK;
328 for (i = 0; i < clock->div_num; i++)
329 if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
330 break;
331
332 if (i >= clock->div_num)
333 return -EINVAL;
334
335 return DIV_ROUND_CLOSEST(rate, clock->div_table[i].div);
336}
337
338static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
339 unsigned long rate,
340 unsigned long parent_rate)
341{
342 unsigned int div;
343
344 if (!rate)
345 rate = 1;
346
347 div = DIV_ROUND_CLOSEST(parent_rate, rate);
348
349 return clamp_t(unsigned int, div, clock->div_min, clock->div_max);
350}
351
352static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
353 unsigned long *parent_rate)
354{
355 struct sd_clock *clock = to_sd_clock(hw);
356 unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);
357
358 return DIV_ROUND_CLOSEST(*parent_rate, div);
359}
360
361static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
362 unsigned long parent_rate)
363{
364 struct sd_clock *clock = to_sd_clock(hw);
365 unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
366 u32 val;
367 unsigned int i;
368
369 for (i = 0; i < clock->div_num; i++)
370 if (div == clock->div_table[i].div)
371 break;
372
373 if (i >= clock->div_num)
374 return -EINVAL;
375
376 val = clk_readl(clock->reg);
377 val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
378 val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
379 clk_writel(val, clock->reg);
380
381 return 0;
382}
383
384static const struct clk_ops cpg_sd_clock_ops = {
385 .enable = cpg_sd_clock_enable,
386 .disable = cpg_sd_clock_disable,
387 .is_enabled = cpg_sd_clock_is_enabled,
388 .recalc_rate = cpg_sd_clock_recalc_rate,
389 .round_rate = cpg_sd_clock_round_rate,
390 .set_rate = cpg_sd_clock_set_rate,
391};
392
393static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
394 void __iomem *base,
395 const char *parent_name)
396{
397 struct clk_init_data init;
398 struct sd_clock *clock;
399 struct clk *clk;
400 unsigned int i;
401
402 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
403 if (!clock)
404 return ERR_PTR(-ENOMEM);
405
406 init.name = core->name;
407 init.ops = &cpg_sd_clock_ops;
408 init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
409 init.parent_names = &parent_name;
410 init.num_parents = 1;
411
412 clock->reg = base + core->offset;
413 clock->hw.init = &init;
414 clock->div_table = cpg_sd_div_table;
415 clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
416
417 clock->div_max = clock->div_table[0].div;
418 clock->div_min = clock->div_max;
419 for (i = 1; i < clock->div_num; i++) {
420 clock->div_max = max(clock->div_max, clock->div_table[i].div);
421 clock->div_min = min(clock->div_min, clock->div_table[i].div);
422 }
423
424 clk = clk_register(NULL, &clock->hw);
425 if (IS_ERR(clk))
426 kfree(clock);
427
428 return clk;
429}
c5dae0df
GU		 430
431#define CPG_PLL0CR 0x00d8
432#define CPG_PLL2CR 0x002c
433#define CPG_PLL4CR 0x01f4
434
435/*
436 * CPG Clock Data
437 */
438
439/*
440 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
441 * 14 13 19 17 (MHz)
442 *-------------------------------------------------------------------
443 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
444 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
445 * 0 0 1 0 Prohibited setting
446 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
447 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
448 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
449 * 0 1 1 0 Prohibited setting
450 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
451 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
452 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
453 * 1 0 1 0 Prohibited setting
454 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
455 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
456 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
457 * 1 1 1 0 Prohibited setting
458 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
459 */
460#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
461 (((md) & BIT(13)) >> 11) | \
462 (((md) & BIT(19)) >> 18) | \
463 (((md) & BIT(17)) >> 17))
464
465struct cpg_pll_config {
466 unsigned int extal_div;
467 unsigned int pll1_mult;
468 unsigned int pll3_mult;
469};
470
471static const struct cpg_pll_config cpg_pll_configs[16] __initconst = {
472 /* EXTAL div PLL1 mult PLL3 mult */
473 { 1, 192, 192, },
474 { 1, 192, 128, },
475 { 0, /* Prohibited setting */ },
476 { 1, 192, 192, },
477 { 1, 160, 160, },
478 { 1, 160, 106, },
479 { 0, /* Prohibited setting */ },
480 { 1, 160, 160, },
481 { 1, 128, 128, },
482 { 1, 128, 84, },
483 { 0, /* Prohibited setting */ },
484 { 1, 128, 128, },
485 { 2, 192, 192, },
486 { 2, 192, 128, },
487 { 0, /* Prohibited setting */ },
488 { 2, 192, 192, },
489};
490
491static const struct cpg_pll_config *cpg_pll_config __initdata;
492
493static
494struct clk * __init r8a7795_cpg_clk_register(struct device *dev,
495 const struct cpg_core_clk *core,
496 const struct cpg_mssr_info *info,
497 struct clk **clks,
498 void __iomem *base)
499{
500 const struct clk *parent;
501 unsigned int mult = 1;
502 unsigned int div = 1;
503 u32 value;
504
505 parent = clks[core->parent];
506 if (IS_ERR(parent))
507 return ERR_CAST(parent);
508
509 switch (core->type) {
510 case CLK_TYPE_GEN3_MAIN:
511 div = cpg_pll_config->extal_div;
512 break;
513
514 case CLK_TYPE_GEN3_PLL0:
515 /*
516 * PLL0 is a configurable multiplier clock. Register it as a
517 * fixed factor clock for now as there's no generic multiplier
518 * clock implementation and we currently have no need to change
519 * the multiplier value.
520 */
521 value = readl(base + CPG_PLL0CR);
522 mult = (((value >> 24) & 0x7f) + 1) * 2;
523 break;
524
525 case CLK_TYPE_GEN3_PLL1:
526 mult = cpg_pll_config->pll1_mult;
527 break;
528
529 case CLK_TYPE_GEN3_PLL2:
530 /*
531 * PLL2 is a configurable multiplier clock. Register it as a
532 * fixed factor clock for now as there's no generic multiplier
533 * clock implementation and we currently have no need to change
534 * the multiplier value.
535 */
536 value = readl(base + CPG_PLL2CR);
537 mult = (((value >> 24) & 0x7f) + 1) * 2;
538 break;
539
540 case CLK_TYPE_GEN3_PLL3:
541 mult = cpg_pll_config->pll3_mult;
542 break;
543
544 case CLK_TYPE_GEN3_PLL4:
545 /*
546 * PLL4 is a configurable multiplier clock. Register it as a
547 * fixed factor clock for now as there's no generic multiplier
548 * clock implementation and we currently have no need to change
549 * the multiplier value.
550 */
551 value = readl(base + CPG_PLL4CR);
552 mult = (((value >> 24) & 0x7f) + 1) * 2;
553 break;
554
90c073e5
DB		 555 case CLK_TYPE_GEN3_SD:
556 return cpg_sd_clk_register(core, base, __clk_get_name(parent));
557
c5dae0df
GU		 558 default:
559 return ERR_PTR(-EINVAL);
560 }
561
562 return clk_register_fixed_factor(NULL, core->name,
563 __clk_get_name(parent), 0, mult, div);
564}
565
566/*
567 * Reset register definitions.
568 */
569#define MODEMR 0xe6160060
570
571static u32 rcar_gen3_read_mode_pins(void)
572{
573 void __iomem *modemr = ioremap_nocache(MODEMR, 4);
574 u32 mode;
575
576 BUG_ON(!modemr);
577 mode = ioread32(modemr);
578 iounmap(modemr);
579
580 return mode;
581}
582
583static int __init r8a7795_cpg_mssr_init(struct device *dev)
584{
585 u32 cpg_mode = rcar_gen3_read_mode_pins();
586
587 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
588 if (!cpg_pll_config->extal_div) {
589 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
590 return -EINVAL;
591 }
592
593 return 0;
594}
595
596const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
597 /* Core Clocks */
598 .core_clks = r8a7795_core_clks,
599 .num_core_clks = ARRAY_SIZE(r8a7795_core_clks),
600 .last_dt_core_clk = LAST_DT_CORE_CLK,
601 .num_total_core_clks = MOD_CLK_BASE,
602
603 /* Module Clocks */
604 .mod_clks = r8a7795_mod_clks,
605 .num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks),
606 .num_hw_mod_clks = 12 * 32,
607
608 /* Critical Module Clocks */
609 .crit_mod_clks = r8a7795_crit_mod_clks,
610 .num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks),
611
612 /* Callbacks */
613 .init = r8a7795_cpg_mssr_init,
614 .cpg_clk_register = r8a7795_cpg_clk_register,
615};
Linux 6.x block layer and io_uring tree(s)