[linux-2.6-block.git] / drivers / clk / samsung / clk-s3c2410-dclk.c

/*
 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Common Clock Framework support for s3c24xx external clock output.
 */

#include <linux/clkdev.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include "clk.h"

/* legacy access to misccr, until dt conversion is finished */
#include <mach/hardware.h>
#include <mach/regs-gpio.h>

#define MUX_DCLK0	0
#define MUX_DCLK1	1
#define DIV_DCLK0	2
#define DIV_DCLK1	3
#define GATE_DCLK0	4
#define GATE_DCLK1	5
#define MUX_CLKOUT0	6
#define MUX_CLKOUT1	7
#define DCLK_MAX_CLKS	(MUX_CLKOUT1 + 1)

enum supported_socs {
	S3C2410,
	S3C2412,
	S3C2440,
	S3C2443,
};

struct s3c24xx_dclk_drv_data {
	const char **clkout0_parent_names;
	int clkout0_num_parents;
	const char **clkout1_parent_names;
	int clkout1_num_parents;
	const char **mux_parent_names;
	int mux_num_parents;
};

/*
 * Clock for output-parent selection in misccr
 */

struct s3c24xx_clkout {
	struct clk_hw		hw;
	u32			mask;
	u8			shift;
};

#define to_s3c24xx_clkout(_hw) container_of(_hw, struct s3c24xx_clkout, hw)

static u8 s3c24xx_clkout_get_parent(struct clk_hw *hw)
{
	struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
	int num_parents = clk_hw_get_num_parents(hw);
	u32 val;

	val = readl_relaxed(S3C24XX_MISCCR) >> clkout->shift;
	val >>= clkout->shift;
	val &= clkout->mask;

	if (val >= num_parents)
		return -EINVAL;

	return val;
}

static int s3c24xx_clkout_set_parent(struct clk_hw *hw, u8 index)
{
	struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);

	s3c2410_modify_misccr((clkout->mask << clkout->shift),
			      (index << clkout->shift));

	return 0;
}

static const struct clk_ops s3c24xx_clkout_ops = {
	.get_parent = s3c24xx_clkout_get_parent,
	.set_parent = s3c24xx_clkout_set_parent,
	.determine_rate = __clk_mux_determine_rate,
};

static struct clk_hw *s3c24xx_register_clkout(struct device *dev,
		const char *name, const char **parent_names, u8 num_parents,
		u8 shift, u32 mask)
{
	struct s3c24xx_clkout *clkout;
	struct clk_init_data init;
	int ret;

	/* allocate the clkout */
	clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
	if (!clkout)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &s3c24xx_clkout_ops;
	init.flags = CLK_IS_BASIC;
	init.parent_names = parent_names;
	init.num_parents = num_parents;

	clkout->shift = shift;
	clkout->mask = mask;
	clkout->hw.init = &init;

	ret = clk_hw_register(dev, &clkout->hw);
	if (ret)
		return ERR_PTR(ret);

	return &clkout->hw;
}

/*
 * dclk and clkout init
 */

struct s3c24xx_dclk {
	struct device *dev;
	void __iomem *base;
	struct notifier_block dclk0_div_change_nb;
	struct notifier_block dclk1_div_change_nb;
	spinlock_t dclk_lock;
	unsigned long reg_save;
	/* clk_data must be the last entry in the structure */
	struct clk_hw_onecell_data clk_data;
};

#define to_s3c24xx_dclk0(x) \
		container_of(x, struct s3c24xx_dclk, dclk0_div_change_nb)

#define to_s3c24xx_dclk1(x) \
		container_of(x, struct s3c24xx_dclk, dclk1_div_change_nb)

static const char *dclk_s3c2410_p[] = { "pclk", "uclk" };
static const char *clkout0_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
			     "gate_dclk0" };
static const char *clkout1_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
			     "gate_dclk1" };

static const char *clkout0_s3c2412_p[] = { "mpll", "upll", "rtc_clkout",
			     "hclk", "pclk", "gate_dclk0" };
static const char *clkout1_s3c2412_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
			     "gate_dclk1" };

static const char *clkout0_s3c2440_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
			     "gate_dclk0" };
static const char *clkout1_s3c2440_p[] = { "mpll", "upll", "rtc_clkout",
			     "hclk", "pclk", "gate_dclk1" };

static const char *dclk_s3c2443_p[] = { "pclk", "epll" };
static const char *clkout0_s3c2443_p[] = { "xti", "epll", "armclk", "hclk", "pclk",
			     "gate_dclk0" };
static const char *clkout1_s3c2443_p[] = { "dummy", "epll", "rtc_clkout",
			     "hclk", "pclk", "gate_dclk1" };

#define DCLKCON_DCLK_DIV_MASK		0xf
#define DCLKCON_DCLK0_DIV_SHIFT		4
#define DCLKCON_DCLK0_CMP_SHIFT		8
#define DCLKCON_DCLK1_DIV_SHIFT		20
#define DCLKCON_DCLK1_CMP_SHIFT		24

static void s3c24xx_dclk_update_cmp(struct s3c24xx_dclk *s3c24xx_dclk,
				    int div_shift, int cmp_shift)
{
	unsigned long flags = 0;
	u32 dclk_con, div, cmp;

	spin_lock_irqsave(&s3c24xx_dclk->dclk_lock, flags);

	dclk_con = readl_relaxed(s3c24xx_dclk->base);

	div = ((dclk_con >> div_shift) & DCLKCON_DCLK_DIV_MASK) + 1;
	cmp = ((div + 1) / 2) - 1;

	dclk_con &= ~(DCLKCON_DCLK_DIV_MASK << cmp_shift);
	dclk_con |= (cmp << cmp_shift);

	writel_relaxed(dclk_con, s3c24xx_dclk->base);

	spin_unlock_irqrestore(&s3c24xx_dclk->dclk_lock, flags);
}

static int s3c24xx_dclk0_div_notify(struct notifier_block *nb,
			       unsigned long event, void *data)
{
	struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk0(nb);

	if (event == POST_RATE_CHANGE) {
		s3c24xx_dclk_update_cmp(s3c24xx_dclk,
			DCLKCON_DCLK0_DIV_SHIFT, DCLKCON_DCLK0_CMP_SHIFT);
	}

	return NOTIFY_DONE;
}

static int s3c24xx_dclk1_div_notify(struct notifier_block *nb,
			       unsigned long event, void *data)
{
	struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk1(nb);

	if (event == POST_RATE_CHANGE) {
		s3c24xx_dclk_update_cmp(s3c24xx_dclk,
			DCLKCON_DCLK1_DIV_SHIFT, DCLKCON_DCLK1_CMP_SHIFT);
	}

	return NOTIFY_DONE;
}

#ifdef CONFIG_PM_SLEEP
static int s3c24xx_dclk_suspend(struct device *dev)
{
	struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);

	s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base);
	return 0;
}

static int s3c24xx_dclk_resume(struct device *dev)
{
	struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);

	writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base);
	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(s3c24xx_dclk_pm_ops,
			 s3c24xx_dclk_suspend, s3c24xx_dclk_resume);

static int s3c24xx_dclk_probe(struct platform_device *pdev)
{
	struct s3c24xx_dclk *s3c24xx_dclk;
	struct resource *mem;
	struct s3c24xx_dclk_drv_data *dclk_variant;
	struct clk_hw **clk_table;
	int ret, i;

	s3c24xx_dclk = devm_kzalloc(&pdev->dev,
				    struct_size(s3c24xx_dclk, clk_data.hws,
						DCLK_MAX_CLKS),
				    GFP_KERNEL);
	if (!s3c24xx_dclk)
		return -ENOMEM;

	clk_table = s3c24xx_dclk->clk_data.hws;

	s3c24xx_dclk->dev = &pdev->dev;
	s3c24xx_dclk->clk_data.num = DCLK_MAX_CLKS;
	platform_set_drvdata(pdev, s3c24xx_dclk);
	spin_lock_init(&s3c24xx_dclk->dclk_lock);

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	s3c24xx_dclk->base = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(s3c24xx_dclk->base))
		return PTR_ERR(s3c24xx_dclk->base);

	dclk_variant = (struct s3c24xx_dclk_drv_data *)
				platform_get_device_id(pdev)->driver_data;


	clk_table[MUX_DCLK0] = clk_hw_register_mux(&pdev->dev, "mux_dclk0",
				dclk_variant->mux_parent_names,
				dclk_variant->mux_num_parents, 0,
				s3c24xx_dclk->base, 1, 1, 0,
				&s3c24xx_dclk->dclk_lock);
	clk_table[MUX_DCLK1] = clk_hw_register_mux(&pdev->dev, "mux_dclk1",
				dclk_variant->mux_parent_names,
				dclk_variant->mux_num_parents, 0,
				s3c24xx_dclk->base, 17, 1, 0,
				&s3c24xx_dclk->dclk_lock);

	clk_table[DIV_DCLK0] = clk_hw_register_divider(&pdev->dev, "div_dclk0",
				"mux_dclk0", 0, s3c24xx_dclk->base,
				4, 4, 0, &s3c24xx_dclk->dclk_lock);
	clk_table[DIV_DCLK1] = clk_hw_register_divider(&pdev->dev, "div_dclk1",
				"mux_dclk1", 0, s3c24xx_dclk->base,
				20, 4, 0, &s3c24xx_dclk->dclk_lock);

	clk_table[GATE_DCLK0] = clk_hw_register_gate(&pdev->dev, "gate_dclk0",
				"div_dclk0", CLK_SET_RATE_PARENT,
				s3c24xx_dclk->base, 0, 0,
				&s3c24xx_dclk->dclk_lock);
	clk_table[GATE_DCLK1] = clk_hw_register_gate(&pdev->dev, "gate_dclk1",
				"div_dclk1", CLK_SET_RATE_PARENT,
				s3c24xx_dclk->base, 16, 0,
				&s3c24xx_dclk->dclk_lock);

	clk_table[MUX_CLKOUT0] = s3c24xx_register_clkout(&pdev->dev,
				"clkout0", dclk_variant->clkout0_parent_names,
				dclk_variant->clkout0_num_parents, 4, 7);
	clk_table[MUX_CLKOUT1] = s3c24xx_register_clkout(&pdev->dev,
				"clkout1", dclk_variant->clkout1_parent_names,
				dclk_variant->clkout1_num_parents, 8, 7);

	for (i = 0; i < DCLK_MAX_CLKS; i++)
		if (IS_ERR(clk_table[i])) {
			dev_err(&pdev->dev, "clock %d failed to register\n", i);
			ret = PTR_ERR(clk_table[i]);
			goto err_clk_register;
		}

	ret = clk_hw_register_clkdev(clk_table[MUX_DCLK0], "dclk0", NULL);
	if (!ret)
		ret = clk_hw_register_clkdev(clk_table[MUX_DCLK1], "dclk1",
					     NULL);
	if (!ret)
		ret = clk_hw_register_clkdev(clk_table[MUX_CLKOUT0],
					     "clkout0", NULL);
	if (!ret)
		ret = clk_hw_register_clkdev(clk_table[MUX_CLKOUT1],
					     "clkout1", NULL);
	if (ret) {
		dev_err(&pdev->dev, "failed to register aliases, %d\n", ret);
		goto err_clk_register;
	}

	s3c24xx_dclk->dclk0_div_change_nb.notifier_call =
						s3c24xx_dclk0_div_notify;

	s3c24xx_dclk->dclk1_div_change_nb.notifier_call =
						s3c24xx_dclk1_div_notify;

	ret = clk_notifier_register(clk_table[DIV_DCLK0]->clk,
				    &s3c24xx_dclk->dclk0_div_change_nb);
	if (ret)
		goto err_clk_register;

	ret = clk_notifier_register(clk_table[DIV_DCLK1]->clk,
				    &s3c24xx_dclk->dclk1_div_change_nb);
	if (ret)
		goto err_dclk_notify;

	return 0;

err_dclk_notify:
	clk_notifier_unregister(clk_table[DIV_DCLK0]->clk,
				&s3c24xx_dclk->dclk0_div_change_nb);
err_clk_register:
	for (i = 0; i < DCLK_MAX_CLKS; i++)
		if (clk_table[i] && !IS_ERR(clk_table[i]))
			clk_hw_unregister(clk_table[i]);

	return ret;
}

static int s3c24xx_dclk_remove(struct platform_device *pdev)
{
	struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
	struct clk_hw **clk_table = s3c24xx_dclk->clk_data.hws;
	int i;

	clk_notifier_unregister(clk_table[DIV_DCLK1]->clk,
				&s3c24xx_dclk->dclk1_div_change_nb);
	clk_notifier_unregister(clk_table[DIV_DCLK0]->clk,
				&s3c24xx_dclk->dclk0_div_change_nb);

	for (i = 0; i < DCLK_MAX_CLKS; i++)
		clk_hw_unregister(clk_table[i]);

	return 0;
}

static struct s3c24xx_dclk_drv_data dclk_variants[] = {
	[S3C2410] = {
		.clkout0_parent_names = clkout0_s3c2410_p,
		.clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2410_p),
		.clkout1_parent_names = clkout1_s3c2410_p,
		.clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2410_p),
		.mux_parent_names = dclk_s3c2410_p,
		.mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
	},
	[S3C2412] = {
		.clkout0_parent_names = clkout0_s3c2412_p,
		.clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2412_p),
		.clkout1_parent_names = clkout1_s3c2412_p,
		.clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2412_p),
		.mux_parent_names = dclk_s3c2410_p,
		.mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
	},
	[S3C2440] = {
		.clkout0_parent_names = clkout0_s3c2440_p,
		.clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2440_p),
		.clkout1_parent_names = clkout1_s3c2440_p,
		.clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2440_p),
		.mux_parent_names = dclk_s3c2410_p,
		.mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
	},
	[S3C2443] = {
		.clkout0_parent_names = clkout0_s3c2443_p,
		.clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2443_p),
		.clkout1_parent_names = clkout1_s3c2443_p,
		.clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2443_p),
		.mux_parent_names = dclk_s3c2443_p,
		.mux_num_parents = ARRAY_SIZE(dclk_s3c2443_p),
	},
};

static const struct platform_device_id s3c24xx_dclk_driver_ids[] = {
	{
		.name		= "s3c2410-dclk",
		.driver_data	= (kernel_ulong_t)&dclk_variants[S3C2410],
	}, {
		.name		= "s3c2412-dclk",
		.driver_data	= (kernel_ulong_t)&dclk_variants[S3C2412],
	}, {
		.name		= "s3c2440-dclk",
		.driver_data	= (kernel_ulong_t)&dclk_variants[S3C2440],
	}, {
		.name		= "s3c2443-dclk",
		.driver_data	= (kernel_ulong_t)&dclk_variants[S3C2443],
	},
	{ }
};

MODULE_DEVICE_TABLE(platform, s3c24xx_dclk_driver_ids);

static struct platform_driver s3c24xx_dclk_driver = {
	.driver = {
		.name			= "s3c24xx-dclk",
		.pm			= &s3c24xx_dclk_pm_ops,
		.suppress_bind_attrs	= true,
	},
	.probe = s3c24xx_dclk_probe,
	.remove = s3c24xx_dclk_remove,
	.id_table = s3c24xx_dclk_driver_ids,
};
module_platform_driver(s3c24xx_dclk_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
MODULE_DESCRIPTION("Driver for the S3C24XX external clock outputs");
Commit	Line	Data
5799ea12 HS	1	/*
	2	* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* Common Clock Framework support for s3c24xx external clock output.
	9	*/
	10
6f1ed07a SB	11	#include <linux/clkdev.h>
	12	#include <linux/slab.h>
	13	#include <linux/clk.h>
	14	#include <linux/clk-provider.h>
5799ea12 HS	15	#include <linux/platform_device.h>
	16	#include <linux/module.h>
	17	#include "clk.h"
	18
	19	/* legacy access to misccr, until dt conversion is finished */
	20	#include <mach/hardware.h>
	21	#include <mach/regs-gpio.h>
	22
	23	#define MUX_DCLK0 0
	24	#define MUX_DCLK1 1
	25	#define DIV_DCLK0 2
	26	#define DIV_DCLK1 3
	27	#define GATE_DCLK0 4
	28	#define GATE_DCLK1 5
	29	#define MUX_CLKOUT0 6
	30	#define MUX_CLKOUT1 7
	31	#define DCLK_MAX_CLKS (MUX_CLKOUT1 + 1)
	32
	33	enum supported_socs {
	34	S3C2410,
	35	S3C2412,
	36	S3C2440,
	37	S3C2443,
	38	};
	39
	40	struct s3c24xx_dclk_drv_data {
	41	const char **clkout0_parent_names;
	42	int clkout0_num_parents;
	43	const char **clkout1_parent_names;
	44	int clkout1_num_parents;
	45	const char **mux_parent_names;
	46	int mux_num_parents;
	47	};
	48
	49	/*
	50	* Clock for output-parent selection in misccr
	51	*/
	52
	53	struct s3c24xx_clkout {
	54	struct clk_hw hw;
	55	u32 mask;
	56	u8 shift;
	57	};
	58
	59	#define to_s3c24xx_clkout(_hw) container_of(_hw, struct s3c24xx_clkout, hw)
	60
	61	static u8 s3c24xx_clkout_get_parent(struct clk_hw *hw)
	62	{
	63	struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
497295af	64	int num_parents = clk_hw_get_num_parents(hw);
5799ea12 HS	65	u32 val;
	66
	67	val = readl_relaxed(S3C24XX_MISCCR) >> clkout->shift;
	68	val >>= clkout->shift;
	69	val &= clkout->mask;
	70
	71	if (val >= num_parents)
	72	return -EINVAL;
	73
	74	return val;
	75	}
	76
	77	static int s3c24xx_clkout_set_parent(struct clk_hw *hw, u8 index)
	78	{
	79	struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
5799ea12 HS	80
	81	s3c2410_modify_misccr((clkout->mask << clkout->shift),
	82	(index << clkout->shift));
	83
c5e949c1	84	return 0;
5799ea12 HS	85	}
5799ea12 HS	86
1237dc44	87	static const struct clk_ops s3c24xx_clkout_ops = {
5799ea12 HS	88	.get_parent = s3c24xx_clkout_get_parent,
	89	.set_parent = s3c24xx_clkout_set_parent,
	90	.determine_rate = __clk_mux_determine_rate,
	91	};
	92
ecb1f1f7 MS	93	static struct clk_hw s3c24xx_register_clkout(struct device dev,
ecb1f1f7 MS	94	const char name, const char *parent_names, u8 num_parents,
5799ea12 HS	95	u8 shift, u32 mask)
	96	{
	97	struct s3c24xx_clkout *clkout;
5799ea12	98	struct clk_init_data init;
ecb1f1f7	99	int ret;
5799ea12 HS	100
	101	/* allocate the clkout */
	102	clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
	103	if (!clkout)
	104	return ERR_PTR(-ENOMEM);
	105
	106	init.name = name;
	107	init.ops = &s3c24xx_clkout_ops;
	108	init.flags = CLK_IS_BASIC;
	109	init.parent_names = parent_names;
	110	init.num_parents = num_parents;
	111
	112	clkout->shift = shift;
	113	clkout->mask = mask;
	114	clkout->hw.init = &init;
	115
ecb1f1f7 MS	116	ret = clk_hw_register(dev, &clkout->hw);
	117	if (ret)
	118	return ERR_PTR(ret);
5799ea12	119
ecb1f1f7	120	return &clkout->hw;
5799ea12 HS	121	}
	122
	123	/*
	124	* dclk and clkout init
	125	*/
	126
	127	struct s3c24xx_dclk {
	128	struct device *dev;
	129	void __iomem *base;
5799ea12 HS	130	struct notifier_block dclk0_div_change_nb;
	131	struct notifier_block dclk1_div_change_nb;
	132	spinlock_t dclk_lock;
	133	unsigned long reg_save;
ecb1f1f7 MS	134	/* clk_data must be the last entry in the structure */
ecb1f1f7 MS	135	struct clk_hw_onecell_data clk_data;
5799ea12 HS	136	};
	137
	138	#define to_s3c24xx_dclk0(x) \
	139	container_of(x, struct s3c24xx_dclk, dclk0_div_change_nb)
	140
	141	#define to_s3c24xx_dclk1(x) \
	142	container_of(x, struct s3c24xx_dclk, dclk1_div_change_nb)
	143
5a3babfc HS	144	static const char *dclk_s3c2410_p[] = { "pclk", "uclk" };
5a3babfc HS	145	static const char *clkout0_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
5799ea12	146	"gate_dclk0" };
5a3babfc	147	static const char *clkout1_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
5799ea12 HS	148	"gate_dclk1" };
5799ea12 HS	149
5a3babfc	150	static const char *clkout0_s3c2412_p[] = { "mpll", "upll", "rtc_clkout",
5799ea12	151	"hclk", "pclk", "gate_dclk0" };
708cec66	152	static const char *clkout1_s3c2412_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
5799ea12 HS	153	"gate_dclk1" };
5799ea12 HS	154
5a3babfc	155	static const char *clkout0_s3c2440_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
5799ea12	156	"gate_dclk0" };
5a3babfc	157	static const char *clkout1_s3c2440_p[] = { "mpll", "upll", "rtc_clkout",
5799ea12 HS	158	"hclk", "pclk", "gate_dclk1" };
5799ea12 HS	159
5a3babfc HS	160	static const char *dclk_s3c2443_p[] = { "pclk", "epll" };
5a3babfc HS	161	static const char *clkout0_s3c2443_p[] = { "xti", "epll", "armclk", "hclk", "pclk",
5799ea12	162	"gate_dclk0" };
5a3babfc	163	static const char *clkout1_s3c2443_p[] = { "dummy", "epll", "rtc_clkout",
5799ea12 HS	164	"hclk", "pclk", "gate_dclk1" };
	165
	166	#define DCLKCON_DCLK_DIV_MASK 0xf
	167	#define DCLKCON_DCLK0_DIV_SHIFT 4
	168	#define DCLKCON_DCLK0_CMP_SHIFT 8
	169	#define DCLKCON_DCLK1_DIV_SHIFT 20
	170	#define DCLKCON_DCLK1_CMP_SHIFT 24
	171
	172	static void s3c24xx_dclk_update_cmp(struct s3c24xx_dclk *s3c24xx_dclk,
	173	int div_shift, int cmp_shift)
	174	{
	175	unsigned long flags = 0;
	176	u32 dclk_con, div, cmp;
	177
	178	spin_lock_irqsave(&s3c24xx_dclk->dclk_lock, flags);
	179
	180	dclk_con = readl_relaxed(s3c24xx_dclk->base);
	181
	182	div = ((dclk_con >> div_shift) & DCLKCON_DCLK_DIV_MASK) + 1;
	183	cmp = ((div + 1) / 2) - 1;
	184
	185	dclk_con &= ~(DCLKCON_DCLK_DIV_MASK << cmp_shift);
	186	dclk_con \|= (cmp << cmp_shift);
	187
	188	writel_relaxed(dclk_con, s3c24xx_dclk->base);
	189
	190	spin_unlock_irqrestore(&s3c24xx_dclk->dclk_lock, flags);
	191	}
	192
	193	static int s3c24xx_dclk0_div_notify(struct notifier_block *nb,
	194	unsigned long event, void *data)
	195	{
	196	struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk0(nb);
	197
	198	if (event == POST_RATE_CHANGE) {
	199	s3c24xx_dclk_update_cmp(s3c24xx_dclk,
	200	DCLKCON_DCLK0_DIV_SHIFT, DCLKCON_DCLK0_CMP_SHIFT);
	201	}
	202
	203	return NOTIFY_DONE;
	204	}
	205
	206	static int s3c24xx_dclk1_div_notify(struct notifier_block *nb,
	207	unsigned long event, void *data)
	208	{
	209	struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk1(nb);
	210
	211	if (event == POST_RATE_CHANGE) {
	212	s3c24xx_dclk_update_cmp(s3c24xx_dclk,
	213	DCLKCON_DCLK1_DIV_SHIFT, DCLKCON_DCLK1_CMP_SHIFT);
	214	}
	215
	216	return NOTIFY_DONE;
	217	}
	218
	219	#ifdef CONFIG_PM_SLEEP
	220	static int s3c24xx_dclk_suspend(struct device *dev)
	221	{
5c5e4fe3	222	struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
5799ea12 HS	223
	224	s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base);
	225	return 0;
	226	}
	227
	228	static int s3c24xx_dclk_resume(struct device *dev)
	229	{
5c5e4fe3	230	struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
5799ea12 HS	231
	232	writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base);
	233	return 0;
	234	}
	235	#endif
	236
	237	static SIMPLE_DEV_PM_OPS(s3c24xx_dclk_pm_ops,
	238	s3c24xx_dclk_suspend, s3c24xx_dclk_resume);
	239
	240	static int s3c24xx_dclk_probe(struct platform_device *pdev)
	241	{
	242	struct s3c24xx_dclk *s3c24xx_dclk;
	243	struct resource *mem;
5799ea12	244	struct s3c24xx_dclk_drv_data *dclk_variant;
ecb1f1f7	245	struct clk_hw **clk_table;
5799ea12 HS	246	int ret, i;
5799ea12 HS	247
0ed2dd03 KC	248	s3c24xx_dclk = devm_kzalloc(&pdev->dev,
	249	struct_size(s3c24xx_dclk, clk_data.hws,
	250	DCLK_MAX_CLKS),
	251	GFP_KERNEL);
5799ea12 HS	252	if (!s3c24xx_dclk)
	253	return -ENOMEM;
	254
ecb1f1f7 MS	255	clk_table = s3c24xx_dclk->clk_data.hws;
ecb1f1f7 MS	256
5799ea12	257	s3c24xx_dclk->dev = &pdev->dev;
ecb1f1f7	258	s3c24xx_dclk->clk_data.num = DCLK_MAX_CLKS;
5799ea12 HS	259	platform_set_drvdata(pdev, s3c24xx_dclk);
	260	spin_lock_init(&s3c24xx_dclk->dclk_lock);
	261
5799ea12 HS	262	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	263	s3c24xx_dclk->base = devm_ioremap_resource(&pdev->dev, mem);
	264	if (IS_ERR(s3c24xx_dclk->base))
	265	return PTR_ERR(s3c24xx_dclk->base);
	266
	267	dclk_variant = (struct s3c24xx_dclk_drv_data *)
	268	platform_get_device_id(pdev)->driver_data;
	269
	270
ecb1f1f7	271	clk_table[MUX_DCLK0] = clk_hw_register_mux(&pdev->dev, "mux_dclk0",
5799ea12 HS	272	dclk_variant->mux_parent_names,
	273	dclk_variant->mux_num_parents, 0,
	274	s3c24xx_dclk->base, 1, 1, 0,
	275	&s3c24xx_dclk->dclk_lock);
ecb1f1f7	276	clk_table[MUX_DCLK1] = clk_hw_register_mux(&pdev->dev, "mux_dclk1",
5799ea12 HS	277	dclk_variant->mux_parent_names,
	278	dclk_variant->mux_num_parents, 0,
	279	s3c24xx_dclk->base, 17, 1, 0,
	280	&s3c24xx_dclk->dclk_lock);
	281
ecb1f1f7	282	clk_table[DIV_DCLK0] = clk_hw_register_divider(&pdev->dev, "div_dclk0",
5799ea12 HS	283	"mux_dclk0", 0, s3c24xx_dclk->base,
5799ea12 HS	284	4, 4, 0, &s3c24xx_dclk->dclk_lock);
ecb1f1f7	285	clk_table[DIV_DCLK1] = clk_hw_register_divider(&pdev->dev, "div_dclk1",
5799ea12 HS	286	"mux_dclk1", 0, s3c24xx_dclk->base,
	287	20, 4, 0, &s3c24xx_dclk->dclk_lock);
	288
ecb1f1f7	289	clk_table[GATE_DCLK0] = clk_hw_register_gate(&pdev->dev, "gate_dclk0",
5799ea12 HS	290	"div_dclk0", CLK_SET_RATE_PARENT,
	291	s3c24xx_dclk->base, 0, 0,
	292	&s3c24xx_dclk->dclk_lock);
ecb1f1f7	293	clk_table[GATE_DCLK1] = clk_hw_register_gate(&pdev->dev, "gate_dclk1",
5799ea12 HS	294	"div_dclk1", CLK_SET_RATE_PARENT,
	295	s3c24xx_dclk->base, 16, 0,
	296	&s3c24xx_dclk->dclk_lock);
	297
	298	clk_table[MUX_CLKOUT0] = s3c24xx_register_clkout(&pdev->dev,
	299	"clkout0", dclk_variant->clkout0_parent_names,
	300	dclk_variant->clkout0_num_parents, 4, 7);
	301	clk_table[MUX_CLKOUT1] = s3c24xx_register_clkout(&pdev->dev,
	302	"clkout1", dclk_variant->clkout1_parent_names,
	303	dclk_variant->clkout1_num_parents, 8, 7);
	304
	305	for (i = 0; i < DCLK_MAX_CLKS; i++)
	306	if (IS_ERR(clk_table[i])) {
	307	dev_err(&pdev->dev, "clock %d failed to register\n", i);
	308	ret = PTR_ERR(clk_table[i]);
	309	goto err_clk_register;
	310	}
	311
ecb1f1f7	312	ret = clk_hw_register_clkdev(clk_table[MUX_DCLK0], "dclk0", NULL);
5799ea12	313	if (!ret)
ecb1f1f7 MS	314	ret = clk_hw_register_clkdev(clk_table[MUX_DCLK1], "dclk1",
ecb1f1f7 MS	315	NULL);
5799ea12	316	if (!ret)
ecb1f1f7 MS	317	ret = clk_hw_register_clkdev(clk_table[MUX_CLKOUT0],
ecb1f1f7 MS	318	"clkout0", NULL);
5799ea12	319	if (!ret)
ecb1f1f7 MS	320	ret = clk_hw_register_clkdev(clk_table[MUX_CLKOUT1],
ecb1f1f7 MS	321	"clkout1", NULL);
5799ea12 HS	322	if (ret) {
	323	dev_err(&pdev->dev, "failed to register aliases, %d\n", ret);
	324	goto err_clk_register;
	325	}
	326
	327	s3c24xx_dclk->dclk0_div_change_nb.notifier_call =
	328	s3c24xx_dclk0_div_notify;
	329
	330	s3c24xx_dclk->dclk1_div_change_nb.notifier_call =
	331	s3c24xx_dclk1_div_notify;
	332
ecb1f1f7	333	ret = clk_notifier_register(clk_table[DIV_DCLK0]->clk,
5799ea12 HS	334	&s3c24xx_dclk->dclk0_div_change_nb);
	335	if (ret)
	336	goto err_clk_register;
	337
ecb1f1f7	338	ret = clk_notifier_register(clk_table[DIV_DCLK1]->clk,
5799ea12 HS	339	&s3c24xx_dclk->dclk1_div_change_nb);
	340	if (ret)
	341	goto err_dclk_notify;
	342
	343	return 0;
	344
	345	err_dclk_notify:
ecb1f1f7	346	clk_notifier_unregister(clk_table[DIV_DCLK0]->clk,
5799ea12 HS	347	&s3c24xx_dclk->dclk0_div_change_nb);
	348	err_clk_register:
	349	for (i = 0; i < DCLK_MAX_CLKS; i++)
	350	if (clk_table[i] && !IS_ERR(clk_table[i]))
ecb1f1f7	351	clk_hw_unregister(clk_table[i]);
5799ea12 HS	352
	353	return ret;
	354	}
	355
	356	static int s3c24xx_dclk_remove(struct platform_device *pdev)
	357	{
	358	struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
ecb1f1f7	359	struct clk_hw **clk_table = s3c24xx_dclk->clk_data.hws;
5799ea12 HS	360	int i;
5799ea12 HS	361
ecb1f1f7	362	clk_notifier_unregister(clk_table[DIV_DCLK1]->clk,
5799ea12	363	&s3c24xx_dclk->dclk1_div_change_nb);
ecb1f1f7	364	clk_notifier_unregister(clk_table[DIV_DCLK0]->clk,
5799ea12 HS	365	&s3c24xx_dclk->dclk0_div_change_nb);
	366
	367	for (i = 0; i < DCLK_MAX_CLKS; i++)
ecb1f1f7	368	clk_hw_unregister(clk_table[i]);
5799ea12 HS	369
	370	return 0;
	371	}
	372
	373	static struct s3c24xx_dclk_drv_data dclk_variants[] = {
	374	[S3C2410] = {
	375	.clkout0_parent_names = clkout0_s3c2410_p,
	376	.clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2410_p),
	377	.clkout1_parent_names = clkout1_s3c2410_p,
	378	.clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2410_p),
	379	.mux_parent_names = dclk_s3c2410_p,
	380	.mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
	381	},
	382	[S3C2412] = {
	383	.clkout0_parent_names = clkout0_s3c2412_p,
	384	.clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2412_p),
	385	.clkout1_parent_names = clkout1_s3c2412_p,
	386	.clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2412_p),
	387	.mux_parent_names = dclk_s3c2410_p,
	388	.mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
	389	},
	390	[S3C2440] = {
	391	.clkout0_parent_names = clkout0_s3c2440_p,
	392	.clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2440_p),
	393	.clkout1_parent_names = clkout1_s3c2440_p,
	394	.clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2440_p),
	395	.mux_parent_names = dclk_s3c2410_p,
	396	.mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
	397	},
	398	[S3C2443] = {
	399	.clkout0_parent_names = clkout0_s3c2443_p,
	400	.clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2443_p),
	401	.clkout1_parent_names = clkout1_s3c2443_p,
	402	.clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2443_p),
	403	.mux_parent_names = dclk_s3c2443_p,
	404	.mux_num_parents = ARRAY_SIZE(dclk_s3c2443_p),
	405	},
	406	};
	407
d5255ec3	408	static const struct platform_device_id s3c24xx_dclk_driver_ids[] = {
5799ea12 HS	409	{
	410	.name = "s3c2410-dclk",
	411	.driver_data = (kernel_ulong_t)&dclk_variants[S3C2410],
	412	}, {
	413	.name = "s3c2412-dclk",
	414	.driver_data = (kernel_ulong_t)&dclk_variants[S3C2412],
	415	}, {
	416	.name = "s3c2440-dclk",
	417	.driver_data = (kernel_ulong_t)&dclk_variants[S3C2440],
	418	}, {
	419	.name = "s3c2443-dclk",
	420	.driver_data = (kernel_ulong_t)&dclk_variants[S3C2443],
	421	},
	422	{ }
	423	};
	424
	425	MODULE_DEVICE_TABLE(platform, s3c24xx_dclk_driver_ids);
	426
	427	static struct platform_driver s3c24xx_dclk_driver = {
	428	.driver = {
f4f4dd0c KK	429	.name = "s3c24xx-dclk",
	430	.pm = &s3c24xx_dclk_pm_ops,
	431	.suppress_bind_attrs = true,
5799ea12 HS	432	},
	433	.probe = s3c24xx_dclk_probe,
	434	.remove = s3c24xx_dclk_remove,
	435	.id_table = s3c24xx_dclk_driver_ids,
	436	};
	437	module_platform_driver(s3c24xx_dclk_driver);
	438
	439	MODULE_LICENSE("GPL v2");
	440	MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
	441	MODULE_DESCRIPTION("Driver for the S3C24XX external clock outputs");