[linux-2.6-block.git] / drivers / clk / samsung / clk-pll.h

/*
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 * Copyright (c) 2013 Linaro Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Common Clock Framework support for all PLL's in Samsung platforms
*/

#ifndef __SAMSUNG_CLK_PLL_H
#define __SAMSUNG_CLK_PLL_H

enum samsung_pll_type {
	pll_2126,
	pll_3000,
	pll_35xx,
	pll_36xx,
	pll_2550,
	pll_2650,
	pll_4500,
	pll_4502,
	pll_4508,
	pll_4600,
	pll_4650,
	pll_4650c,
	pll_6552,
	pll_6552_s3c2416,
	pll_6553,
	pll_s3c2410_mpll,
	pll_s3c2410_upll,
	pll_s3c2440_mpll,
	pll_2550xx,
	pll_2650xx,
	pll_1450x,
	pll_1451x,
	pll_1452x,
	pll_1460x,
};

#define PLL_35XX_RATE(_rate, _m, _p, _s)			\
	{							\
		.rate	=	(_rate),				\
		.mdiv	=	(_m),				\
		.pdiv	=	(_p),				\
		.sdiv	=	(_s),				\
	}

#define PLL_36XX_RATE(_rate, _m, _p, _s, _k)			\
	{							\
		.rate	=	(_rate),				\
		.mdiv	=	(_m),				\
		.pdiv	=	(_p),				\
		.sdiv	=	(_s),				\
		.kdiv	=	(_k),				\
	}

#define PLL_45XX_RATE(_rate, _m, _p, _s, _afc)			\
	{							\
		.rate	=	(_rate),			\
		.mdiv	=	(_m),				\
		.pdiv	=	(_p),				\
		.sdiv	=	(_s),				\
		.afc	=	(_afc),				\
	}

#define PLL_4600_RATE(_rate, _m, _p, _s, _k, _vsel)		\
	{							\
		.rate	=	(_rate),			\
		.mdiv	=	(_m),				\
		.pdiv	=	(_p),				\
		.sdiv	=	(_s),				\
		.kdiv	=	(_k),				\
		.vsel	=	(_vsel),			\
	}

#define PLL_4650_RATE(_rate, _m, _p, _s, _k, _mfr, _mrr, _vsel)	\
	{							\
		.rate	=	(_rate),			\
		.mdiv	=	(_m),				\
		.pdiv	=	(_p),				\
		.sdiv	=	(_s),				\
		.kdiv	=	(_k),				\
		.mfr	=	(_mfr),				\
		.mrr	=	(_mrr),				\
		.vsel	=	(_vsel),			\
	}

/* NOTE: Rate table should be kept sorted in descending order. */

struct samsung_pll_rate_table {
	unsigned int rate;
	unsigned int pdiv;
	unsigned int mdiv;
	unsigned int sdiv;
	unsigned int kdiv;
	unsigned int afc;
	unsigned int mfr;
	unsigned int mrr;
	unsigned int vsel;
};

extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
			const char *pname, const void __iomem *reg_base,
			const unsigned long offset);

#endif /* __SAMSUNG_CLK_PLL_H */
Commit	Line	Data
1c4c5fe0 TA	1	/*
	2	* Copyright (c) 2013 Samsung Electronics Co., Ltd.
	3	* Copyright (c) 2013 Linaro Ltd.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* Common Clock Framework support for all PLL's in Samsung platforms
	10	*/
	11
	12	#ifndef __SAMSUNG_CLK_PLL_H
	13	#define __SAMSUNG_CLK_PLL_H
	14
07dc76fa	15	enum samsung_pll_type {
a951b1d9 HS	16	pll_2126,
a951b1d9 HS	17	pll_3000,
07dc76fa YSB	18	pll_35xx,
	19	pll_36xx,
	20	pll_2550,
	21	pll_2650,
52b06016 TF	22	pll_4500,
	23	pll_4502,
	24	pll_4508,
c50d11f3 TF	25	pll_4600,
	26	pll_4650,
	27	pll_4650c,
40ef723c	28	pll_6552,
06654acb	29	pll_6552_s3c2416,
40ef723c	30	pll_6553,
ea5d6a8d HS	31	pll_s3c2410_mpll,
	32	pll_s3c2410_upll,
	33	pll_s3c2440_mpll,
84329847	34	pll_2550xx,
eefe119b	35	pll_2650xx,
0c23e2af NKC	36	pll_1450x,
	37	pll_1451x,
	38	pll_1452x,
	39	pll_1460x,
07dc76fa YSB	40	};
07dc76fa YSB	41
3ff6e0d8 YSB	42	#define PLL_35XX_RATE(_rate, _m, _p, _s) \
	43	{ \
	44	.rate = (_rate), \
	45	.mdiv = (_m), \
	46	.pdiv = (_p), \
	47	.sdiv = (_s), \
	48	}
	49
	50	#define PLL_36XX_RATE(_rate, _m, _p, _s, _k) \
	51	{ \
	52	.rate = (_rate), \
	53	.mdiv = (_m), \
	54	.pdiv = (_p), \
	55	.sdiv = (_s), \
	56	.kdiv = (_k), \
	57	}
	58
b4054ac6 TF	59	#define PLL_45XX_RATE(_rate, _m, _p, _s, _afc) \
	60	{ \
	61	.rate = (_rate), \
	62	.mdiv = (_m), \
	63	.pdiv = (_p), \
	64	.sdiv = (_s), \
	65	.afc = (_afc), \
	66	}
	67
5c89658a TF	68	#define PLL_4600_RATE(_rate, _m, _p, _s, _k, _vsel) \
	69	{ \
	70	.rate = (_rate), \
	71	.mdiv = (_m), \
	72	.pdiv = (_p), \
	73	.sdiv = (_s), \
	74	.kdiv = (_k), \
	75	.vsel = (_vsel), \
	76	}
	77
	78	#define PLL_4650_RATE(_rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
	79	{ \
	80	.rate = (_rate), \
	81	.mdiv = (_m), \
	82	.pdiv = (_p), \
	83	.sdiv = (_s), \
	84	.kdiv = (_k), \
	85	.mfr = (_mfr), \
	86	.mrr = (_mrr), \
	87	.vsel = (_vsel), \
	88	}
	89
3ff6e0d8 YSB	90	/* NOTE: Rate table should be kept sorted in descending order. */
	91
	92	struct samsung_pll_rate_table {
	93	unsigned int rate;
	94	unsigned int pdiv;
	95	unsigned int mdiv;
	96	unsigned int sdiv;
	97	unsigned int kdiv;
b4054ac6	98	unsigned int afc;
5c89658a TF	99	unsigned int mfr;
	100	unsigned int mrr;
	101	unsigned int vsel;
3ff6e0d8 YSB	102	};
3ff6e0d8 YSB	103
1c4c5fe0 TA	104	extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
	105	const char pname, const void __iomem reg_base,
	106	const unsigned long offset);
	107
	108	#endif /* __SAMSUNG_CLK_PLL_H */