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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1c4c5fe0 TA |
2 | /* |
3 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
4 | * Copyright (c) 2013 Linaro Ltd. | |
5 | * | |
1c4c5fe0 TA |
6 | * This file contains the utility functions to register the pll clocks. |
7 | */ | |
8 | ||
9 | #include <linux/errno.h> | |
b4054ac6 | 10 | #include <linux/hrtimer.h> |
44a9e78f | 11 | #include <linux/iopoll.h> |
ea5d6a8d | 12 | #include <linux/delay.h> |
6f1ed07a | 13 | #include <linux/slab.h> |
44a9e78f | 14 | #include <linux/timekeeping.h> |
62e59c4e SB |
15 | #include <linux/clk-provider.h> |
16 | #include <linux/io.h> | |
1c4c5fe0 TA |
17 | #include "clk.h" |
18 | #include "clk-pll.h" | |
19 | ||
44a9e78f SN |
20 | #define PLL_TIMEOUT_US 20000U |
21 | #define PLL_TIMEOUT_LOOPS 1000000U | |
b4054ac6 | 22 | |
079dbead YSB |
23 | struct samsung_clk_pll { |
24 | struct clk_hw hw; | |
25 | void __iomem *lock_reg; | |
26 | void __iomem *con_reg; | |
6edfa11c SN |
27 | /* PLL enable control bit offset in @con_reg register */ |
28 | unsigned short enable_offs; | |
29 | /* PLL lock status bit offset in @con_reg register */ | |
30 | unsigned short lock_offs; | |
07dc76fa | 31 | enum samsung_pll_type type; |
3ff6e0d8 YSB |
32 | unsigned int rate_count; |
33 | const struct samsung_pll_rate_table *rate_table; | |
079dbead YSB |
34 | }; |
35 | ||
36 | #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw) | |
37 | ||
dfa89319 YSB |
38 | static const struct samsung_pll_rate_table *samsung_get_pll_settings( |
39 | struct samsung_clk_pll *pll, unsigned long rate) | |
40 | { | |
41 | const struct samsung_pll_rate_table *rate_table = pll->rate_table; | |
42 | int i; | |
43 | ||
44 | for (i = 0; i < pll->rate_count; i++) { | |
45 | if (rate == rate_table[i].rate) | |
46 | return &rate_table[i]; | |
47 | } | |
48 | ||
49 | return NULL; | |
50 | } | |
51 | ||
52 | static long samsung_pll_round_rate(struct clk_hw *hw, | |
53 | unsigned long drate, unsigned long *prate) | |
54 | { | |
55 | struct samsung_clk_pll *pll = to_clk_pll(hw); | |
56 | const struct samsung_pll_rate_table *rate_table = pll->rate_table; | |
57 | int i; | |
58 | ||
59 | /* Assumming rate_table is in descending order */ | |
60 | for (i = 0; i < pll->rate_count; i++) { | |
61 | if (drate >= rate_table[i].rate) | |
62 | return rate_table[i].rate; | |
63 | } | |
64 | ||
65 | /* return minimum supported value */ | |
66 | return rate_table[i - 1].rate; | |
67 | } | |
68 | ||
44a9e78f SN |
69 | static bool pll_early_timeout = true; |
70 | ||
71 | static int __init samsung_pll_disable_early_timeout(void) | |
72 | { | |
73 | pll_early_timeout = false; | |
74 | return 0; | |
75 | } | |
76 | arch_initcall(samsung_pll_disable_early_timeout); | |
77 | ||
78 | /* Wait until the PLL is locked */ | |
79 | static int samsung_pll_lock_wait(struct samsung_clk_pll *pll, | |
80 | unsigned int reg_mask) | |
81 | { | |
82 | int i, ret; | |
83 | u32 val; | |
84 | ||
85 | /* | |
86 | * This function might be called when the timekeeping API can't be used | |
87 | * to detect timeouts. One situation is when the clocksource is not yet | |
88 | * initialized, another when the timekeeping is suspended. udelay() also | |
89 | * cannot be used when the clocksource is not running on arm64, since | |
90 | * the current timer is used as cycle counter. So a simple busy loop | |
91 | * is used here in that special cases. The limit of iterations has been | |
92 | * derived from experimental measurements of various PLLs on multiple | |
93 | * Exynos SoC variants. Single register read time was usually in range | |
94 | * 0.4...1.5 us, never less than 0.4 us. | |
95 | */ | |
96 | if (pll_early_timeout || timekeeping_suspended) { | |
97 | i = PLL_TIMEOUT_LOOPS; | |
98 | while (i-- > 0) { | |
99 | if (readl_relaxed(pll->con_reg) & reg_mask) | |
100 | return 0; | |
101 | ||
102 | cpu_relax(); | |
103 | } | |
104 | ret = -ETIMEDOUT; | |
105 | } else { | |
106 | ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val, | |
107 | val & reg_mask, 0, PLL_TIMEOUT_US); | |
108 | } | |
109 | ||
110 | if (ret < 0) | |
111 | pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw)); | |
112 | ||
113 | return ret; | |
114 | } | |
115 | ||
6edfa11c SN |
116 | static int samsung_pll3xxx_enable(struct clk_hw *hw) |
117 | { | |
118 | struct samsung_clk_pll *pll = to_clk_pll(hw); | |
119 | u32 tmp; | |
120 | ||
121 | tmp = readl_relaxed(pll->con_reg); | |
122 | tmp |= BIT(pll->enable_offs); | |
123 | writel_relaxed(tmp, pll->con_reg); | |
124 | ||
44a9e78f | 125 | return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); |
6edfa11c SN |
126 | } |
127 | ||
128 | static void samsung_pll3xxx_disable(struct clk_hw *hw) | |
129 | { | |
130 | struct samsung_clk_pll *pll = to_clk_pll(hw); | |
131 | u32 tmp; | |
132 | ||
133 | tmp = readl_relaxed(pll->con_reg); | |
134 | tmp &= ~BIT(pll->enable_offs); | |
135 | writel_relaxed(tmp, pll->con_reg); | |
136 | } | |
137 | ||
a951b1d9 HS |
138 | /* |
139 | * PLL2126 Clock Type | |
140 | */ | |
141 | ||
142 | #define PLL2126_MDIV_MASK (0xff) | |
143 | #define PLL2126_PDIV_MASK (0x3f) | |
144 | #define PLL2126_SDIV_MASK (0x3) | |
145 | #define PLL2126_MDIV_SHIFT (16) | |
146 | #define PLL2126_PDIV_SHIFT (8) | |
147 | #define PLL2126_SDIV_SHIFT (0) | |
148 | ||
149 | static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw, | |
150 | unsigned long parent_rate) | |
151 | { | |
152 | struct samsung_clk_pll *pll = to_clk_pll(hw); | |
153 | u32 pll_con, mdiv, pdiv, sdiv; | |
154 | u64 fvco = parent_rate; | |
155 | ||
4de10339 | 156 | pll_con = readl_relaxed(pll->con_reg); |
a951b1d9 HS |
157 | mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK; |
158 | pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK; | |
159 | sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK; | |
160 | ||
161 | fvco *= (mdiv + 8); | |
162 | do_div(fvco, (pdiv + 2) << sdiv); | |
163 | ||
164 | return (unsigned long)fvco; | |
165 | } | |
166 | ||
167 | static const struct clk_ops samsung_pll2126_clk_ops = { | |
168 | .recalc_rate = samsung_pll2126_recalc_rate, | |
169 | }; | |
170 | ||
171 | /* | |
172 | * PLL3000 Clock Type | |
173 | */ | |
174 | ||
175 | #define PLL3000_MDIV_MASK (0xff) | |
176 | #define PLL3000_PDIV_MASK (0x3) | |
177 | #define PLL3000_SDIV_MASK (0x3) | |
178 | #define PLL3000_MDIV_SHIFT (16) | |
179 | #define PLL3000_PDIV_SHIFT (8) | |
180 | #define PLL3000_SDIV_SHIFT (0) | |
181 | ||
182 | static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw, | |
183 | unsigned long parent_rate) | |
184 | { | |
185 | struct samsung_clk_pll *pll = to_clk_pll(hw); | |
186 | u32 pll_con, mdiv, pdiv, sdiv; | |
187 | u64 fvco = parent_rate; | |
188 | ||
4de10339 | 189 | pll_con = readl_relaxed(pll->con_reg); |
a951b1d9 HS |
190 | mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK; |
191 | pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK; | |
192 | sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK; | |
193 | ||
194 | fvco *= (2 * (mdiv + 8)); | |
195 | do_div(fvco, pdiv << sdiv); | |
196 | ||
197 | return (unsigned long)fvco; | |
198 | } | |
199 | ||
200 | static const struct clk_ops samsung_pll3000_clk_ops = { | |
201 | .recalc_rate = samsung_pll3000_recalc_rate, | |
202 | }; | |
203 | ||
1c4c5fe0 TA |
204 | /* |
205 | * PLL35xx Clock Type | |
206 | */ | |
dfa89319 YSB |
207 | /* Maximum lock time can be 270 * PDIV cycles */ |
208 | #define PLL35XX_LOCK_FACTOR (270) | |
1c4c5fe0 TA |
209 | |
210 | #define PLL35XX_MDIV_MASK (0x3FF) | |
211 | #define PLL35XX_PDIV_MASK (0x3F) | |
212 | #define PLL35XX_SDIV_MASK (0x7) | |
213 | #define PLL35XX_MDIV_SHIFT (16) | |
214 | #define PLL35XX_PDIV_SHIFT (8) | |
215 | #define PLL35XX_SDIV_SHIFT (0) | |
dfa89319 | 216 | #define PLL35XX_LOCK_STAT_SHIFT (29) |
96a8d753 MS |
217 | #define PLL35XX_ENABLE_SHIFT (31) |
218 | ||
1c4c5fe0 TA |
219 | static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, |
220 | unsigned long parent_rate) | |
221 | { | |
079dbead | 222 | struct samsung_clk_pll *pll = to_clk_pll(hw); |
1c4c5fe0 TA |
223 | u32 mdiv, pdiv, sdiv, pll_con; |
224 | u64 fvco = parent_rate; | |
225 | ||
4de10339 | 226 | pll_con = readl_relaxed(pll->con_reg); |
1c4c5fe0 TA |
227 | mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; |
228 | pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; | |
229 | sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK; | |
230 | ||
231 | fvco *= mdiv; | |
232 | do_div(fvco, (pdiv << sdiv)); | |
233 | ||
234 | return (unsigned long)fvco; | |
235 | } | |
236 | ||
dfa89319 YSB |
237 | static inline bool samsung_pll35xx_mp_change( |
238 | const struct samsung_pll_rate_table *rate, u32 pll_con) | |
239 | { | |
240 | u32 old_mdiv, old_pdiv; | |
241 | ||
242 | old_mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; | |
243 | old_pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; | |
244 | ||
245 | return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); | |
246 | } | |
247 | ||
248 | static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, | |
249 | unsigned long prate) | |
250 | { | |
251 | struct samsung_clk_pll *pll = to_clk_pll(hw); | |
252 | const struct samsung_pll_rate_table *rate; | |
253 | u32 tmp; | |
254 | ||
255 | /* Get required rate settings from table */ | |
256 | rate = samsung_get_pll_settings(pll, drate); | |
257 | if (!rate) { | |
258 | pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, | |
836ee0f7 | 259 | drate, clk_hw_get_name(hw)); |
dfa89319 YSB |
260 | return -EINVAL; |
261 | } | |
262 | ||
4de10339 | 263 | tmp = readl_relaxed(pll->con_reg); |
dfa89319 YSB |
264 | |
265 | if (!(samsung_pll35xx_mp_change(rate, tmp))) { | |
266 | /* If only s change, change just s value only*/ | |
267 | tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT); | |
268 | tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT; | |
4de10339 | 269 | writel_relaxed(tmp, pll->con_reg); |
dfa89319 YSB |
270 | |
271 | return 0; | |
272 | } | |
273 | ||
274 | /* Set PLL lock time. */ | |
4de10339 | 275 | writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR, |
dfa89319 YSB |
276 | pll->lock_reg); |
277 | ||
278 | /* Change PLL PMS values */ | |
279 | tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) | | |
280 | (PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) | | |
281 | (PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT)); | |
282 | tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) | | |
283 | (rate->pdiv << PLL35XX_PDIV_SHIFT) | | |
284 | (rate->sdiv << PLL35XX_SDIV_SHIFT); | |
4de10339 | 285 | writel_relaxed(tmp, pll->con_reg); |
dfa89319 | 286 | |
44a9e78f SN |
287 | /* Wait for PLL lock if the PLL is enabled */ |
288 | if (tmp & BIT(pll->enable_offs)) | |
289 | return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); | |
290 | ||
dfa89319 YSB |
291 | return 0; |
292 | } | |
293 | ||
1c4c5fe0 TA |
294 | static const struct clk_ops samsung_pll35xx_clk_ops = { |
295 | .recalc_rate = samsung_pll35xx_recalc_rate, | |
dfa89319 YSB |
296 | .round_rate = samsung_pll_round_rate, |
297 | .set_rate = samsung_pll35xx_set_rate, | |
6edfa11c SN |
298 | .enable = samsung_pll3xxx_enable, |
299 | .disable = samsung_pll3xxx_disable, | |
dfa89319 YSB |
300 | }; |
301 | ||
302 | static const struct clk_ops samsung_pll35xx_clk_min_ops = { | |
303 | .recalc_rate = samsung_pll35xx_recalc_rate, | |
1c4c5fe0 TA |
304 | }; |
305 | ||
1c4c5fe0 TA |
306 | /* |
307 | * PLL36xx Clock Type | |
308 | */ | |
bb4278dc VS |
309 | /* Maximum lock time can be 3000 * PDIV cycles */ |
310 | #define PLL36XX_LOCK_FACTOR (3000) | |
1c4c5fe0 TA |
311 | |
312 | #define PLL36XX_KDIV_MASK (0xFFFF) | |
313 | #define PLL36XX_MDIV_MASK (0x1FF) | |
314 | #define PLL36XX_PDIV_MASK (0x3F) | |
315 | #define PLL36XX_SDIV_MASK (0x7) | |
316 | #define PLL36XX_MDIV_SHIFT (16) | |
317 | #define PLL36XX_PDIV_SHIFT (8) | |
318 | #define PLL36XX_SDIV_SHIFT (0) | |
bb4278dc VS |
319 | #define PLL36XX_KDIV_SHIFT (0) |
320 | #define PLL36XX_LOCK_STAT_SHIFT (29) | |
6edfa11c | 321 | #define PLL36XX_ENABLE_SHIFT (31) |
1c4c5fe0 | 322 | |
1c4c5fe0 TA |
323 | static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, |
324 | unsigned long parent_rate) | |
325 | { | |
079dbead | 326 | struct samsung_clk_pll *pll = to_clk_pll(hw); |
071ff9a3 DA |
327 | u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; |
328 | s16 kdiv; | |
1c4c5fe0 TA |
329 | u64 fvco = parent_rate; |
330 | ||
4de10339 ML |
331 | pll_con0 = readl_relaxed(pll->con_reg); |
332 | pll_con1 = readl_relaxed(pll->con_reg + 4); | |
1c4c5fe0 TA |
333 | mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; |
334 | pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; | |
335 | sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK; | |
071ff9a3 | 336 | kdiv = (s16)(pll_con1 & PLL36XX_KDIV_MASK); |
1c4c5fe0 TA |
337 | |
338 | fvco *= (mdiv << 16) + kdiv; | |
339 | do_div(fvco, (pdiv << sdiv)); | |
340 | fvco >>= 16; | |
341 | ||
342 | return (unsigned long)fvco; | |
343 | } | |
344 | ||
bb4278dc VS |
345 | static inline bool samsung_pll36xx_mpk_change( |
346 | const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1) | |
347 | { | |
348 | u32 old_mdiv, old_pdiv, old_kdiv; | |
349 | ||
350 | old_mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; | |
351 | old_pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; | |
352 | old_kdiv = (pll_con1 >> PLL36XX_KDIV_SHIFT) & PLL36XX_KDIV_MASK; | |
353 | ||
354 | return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv || | |
355 | rate->kdiv != old_kdiv); | |
356 | } | |
357 | ||
358 | static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, | |
359 | unsigned long parent_rate) | |
360 | { | |
361 | struct samsung_clk_pll *pll = to_clk_pll(hw); | |
44a9e78f | 362 | u32 pll_con0, pll_con1; |
bb4278dc VS |
363 | const struct samsung_pll_rate_table *rate; |
364 | ||
365 | rate = samsung_get_pll_settings(pll, drate); | |
366 | if (!rate) { | |
367 | pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, | |
836ee0f7 | 368 | drate, clk_hw_get_name(hw)); |
bb4278dc VS |
369 | return -EINVAL; |
370 | } | |
371 | ||
4de10339 ML |
372 | pll_con0 = readl_relaxed(pll->con_reg); |
373 | pll_con1 = readl_relaxed(pll->con_reg + 4); | |
bb4278dc VS |
374 | |
375 | if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) { | |
376 | /* If only s change, change just s value only*/ | |
377 | pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT); | |
378 | pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT); | |
4de10339 | 379 | writel_relaxed(pll_con0, pll->con_reg); |
bb4278dc VS |
380 | |
381 | return 0; | |
382 | } | |
383 | ||
384 | /* Set PLL lock time. */ | |
4de10339 | 385 | writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); |
bb4278dc VS |
386 | |
387 | /* Change PLL PMS values */ | |
388 | pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) | | |
389 | (PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT) | | |
390 | (PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT)); | |
391 | pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) | | |
392 | (rate->pdiv << PLL36XX_PDIV_SHIFT) | | |
393 | (rate->sdiv << PLL36XX_SDIV_SHIFT); | |
4de10339 | 394 | writel_relaxed(pll_con0, pll->con_reg); |
bb4278dc VS |
395 | |
396 | pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT); | |
397 | pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT; | |
4de10339 | 398 | writel_relaxed(pll_con1, pll->con_reg + 4); |
bb4278dc | 399 | |
44a9e78f SN |
400 | if (pll_con0 & BIT(pll->enable_offs)) |
401 | return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); | |
bb4278dc VS |
402 | |
403 | return 0; | |
404 | } | |
405 | ||
1c4c5fe0 TA |
406 | static const struct clk_ops samsung_pll36xx_clk_ops = { |
407 | .recalc_rate = samsung_pll36xx_recalc_rate, | |
bb4278dc VS |
408 | .set_rate = samsung_pll36xx_set_rate, |
409 | .round_rate = samsung_pll_round_rate, | |
6edfa11c SN |
410 | .enable = samsung_pll3xxx_enable, |
411 | .disable = samsung_pll3xxx_disable, | |
bb4278dc VS |
412 | }; |
413 | ||
414 | static const struct clk_ops samsung_pll36xx_clk_min_ops = { | |
415 | .recalc_rate = samsung_pll36xx_recalc_rate, | |
1c4c5fe0 TA |
416 | }; |
417 | ||
8f90f43a SP |
418 | /* |
419 | * PLL0822x Clock Type | |
420 | */ | |
421 | /* Maximum lock time can be 150 * PDIV cycles */ | |
422 | #define PLL0822X_LOCK_FACTOR (150) | |
423 | ||
424 | #define PLL0822X_MDIV_MASK (0x3FF) | |
425 | #define PLL0822X_PDIV_MASK (0x3F) | |
426 | #define PLL0822X_SDIV_MASK (0x7) | |
427 | #define PLL0822X_MDIV_SHIFT (16) | |
428 | #define PLL0822X_PDIV_SHIFT (8) | |
429 | #define PLL0822X_SDIV_SHIFT (0) | |
430 | #define PLL0822X_LOCK_STAT_SHIFT (29) | |
431 | #define PLL0822X_ENABLE_SHIFT (31) | |
432 | ||
433 | static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw, | |
434 | unsigned long parent_rate) | |
435 | { | |
436 | struct samsung_clk_pll *pll = to_clk_pll(hw); | |
437 | u32 mdiv, pdiv, sdiv, pll_con3; | |
438 | u64 fvco = parent_rate; | |
439 | ||
440 | pll_con3 = readl_relaxed(pll->con_reg); | |
441 | mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK; | |
442 | pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK; | |
443 | sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK; | |
444 | ||
445 | fvco *= mdiv; | |
446 | do_div(fvco, (pdiv << sdiv)); | |
447 | ||
448 | return (unsigned long)fvco; | |
449 | } | |
450 | ||
451 | static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate, | |
452 | unsigned long prate) | |
453 | { | |
454 | const struct samsung_pll_rate_table *rate; | |
455 | struct samsung_clk_pll *pll = to_clk_pll(hw); | |
456 | u32 pll_con3; | |
457 | ||
458 | /* Get required rate settings from table */ | |
459 | rate = samsung_get_pll_settings(pll, drate); | |
460 | if (!rate) { | |
461 | pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, | |
462 | drate, clk_hw_get_name(hw)); | |
463 | return -EINVAL; | |
464 | } | |
465 | ||
466 | /* Change PLL PMS values */ | |
467 | pll_con3 = readl_relaxed(pll->con_reg); | |
468 | pll_con3 &= ~((PLL0822X_MDIV_MASK << PLL0822X_MDIV_SHIFT) | | |
469 | (PLL0822X_PDIV_MASK << PLL0822X_PDIV_SHIFT) | | |
470 | (PLL0822X_SDIV_MASK << PLL0822X_SDIV_SHIFT)); | |
471 | pll_con3 |= (rate->mdiv << PLL0822X_MDIV_SHIFT) | | |
472 | (rate->pdiv << PLL0822X_PDIV_SHIFT) | | |
473 | (rate->sdiv << PLL0822X_SDIV_SHIFT); | |
474 | ||
475 | /* Set PLL lock time */ | |
476 | writel_relaxed(rate->pdiv * PLL0822X_LOCK_FACTOR, | |
477 | pll->lock_reg); | |
478 | ||
479 | /* Write PMS values */ | |
480 | writel_relaxed(pll_con3, pll->con_reg); | |
481 | ||
482 | /* Wait for PLL lock if the PLL is enabled */ | |
483 | if (pll_con3 & BIT(pll->enable_offs)) | |
484 | return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); | |
485 | ||
486 | return 0; | |
487 | } | |
488 | ||
489 | static const struct clk_ops samsung_pll0822x_clk_ops = { | |
490 | .recalc_rate = samsung_pll0822x_recalc_rate, | |
491 | .round_rate = samsung_pll_round_rate, | |
492 | .set_rate = samsung_pll0822x_set_rate, | |
493 | .enable = samsung_pll3xxx_enable, | |
494 | .disable = samsung_pll3xxx_disable, | |
495 | }; | |
496 | ||
497 | static const struct clk_ops samsung_pll0822x_clk_min_ops = { | |
498 | .recalc_rate = samsung_pll0822x_recalc_rate, | |
499 | }; | |
500 | ||
6a734b37 SP |
501 | /* |
502 | * PLL0831x Clock Type | |
503 | */ | |
504 | /* Maximum lock time can be 500 * PDIV cycles */ | |
505 | #define PLL0831X_LOCK_FACTOR (500) | |
506 | ||
507 | #define PLL0831X_KDIV_MASK (0xFFFF) | |
508 | #define PLL0831X_MDIV_MASK (0x1FF) | |
509 | #define PLL0831X_PDIV_MASK (0x3F) | |
510 | #define PLL0831X_SDIV_MASK (0x7) | |
511 | #define PLL0831X_MDIV_SHIFT (16) | |
512 | #define PLL0831X_PDIV_SHIFT (8) | |
513 | #define PLL0831X_SDIV_SHIFT (0) | |
514 | #define PLL0831X_KDIV_SHIFT (0) | |
515 | #define PLL0831X_LOCK_STAT_SHIFT (29) | |
516 | #define PLL0831X_ENABLE_SHIFT (31) | |
517 | ||
518 | static unsigned long samsung_pll0831x_recalc_rate(struct clk_hw *hw, | |
519 | unsigned long parent_rate) | |
520 | { | |
521 | struct samsung_clk_pll *pll = to_clk_pll(hw); | |
522 | u32 mdiv, pdiv, sdiv, pll_con3, pll_con5; | |
523 | s16 kdiv; | |
524 | u64 fvco = parent_rate; | |
525 | ||
526 | pll_con3 = readl_relaxed(pll->con_reg); | |
527 | pll_con5 = readl_relaxed(pll->con_reg + 8); | |
528 | mdiv = (pll_con3 >> PLL0831X_MDIV_SHIFT) & PLL0831X_MDIV_MASK; | |
529 | pdiv = (pll_con3 >> PLL0831X_PDIV_SHIFT) & PLL0831X_PDIV_MASK; | |
530 | sdiv = (pll_con3 >> PLL0831X_SDIV_SHIFT) & PLL0831X_SDIV_MASK; | |
531 | kdiv = (s16)((pll_con5 >> PLL0831X_KDIV_SHIFT) & PLL0831X_KDIV_MASK); | |
532 | ||
533 | fvco *= (mdiv << 16) + kdiv; | |
534 | do_div(fvco, (pdiv << sdiv)); | |
535 | fvco >>= 16; | |
536 | ||
537 | return (unsigned long)fvco; | |
538 | } | |
539 | ||
540 | static int samsung_pll0831x_set_rate(struct clk_hw *hw, unsigned long drate, | |
541 | unsigned long parent_rate) | |
542 | { | |
543 | const struct samsung_pll_rate_table *rate; | |
544 | struct samsung_clk_pll *pll = to_clk_pll(hw); | |
545 | u32 pll_con3, pll_con5; | |
546 | ||
547 | /* Get required rate settings from table */ | |
548 | rate = samsung_get_pll_settings(pll, drate); | |
549 | if (!rate) { | |
550 | pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, | |
551 | drate, clk_hw_get_name(hw)); | |
552 | return -EINVAL; | |
553 | } | |
554 | ||
555 | pll_con3 = readl_relaxed(pll->con_reg); | |
556 | pll_con5 = readl_relaxed(pll->con_reg + 8); | |
557 | ||
558 | /* Change PLL PMSK values */ | |
559 | pll_con3 &= ~((PLL0831X_MDIV_MASK << PLL0831X_MDIV_SHIFT) | | |
560 | (PLL0831X_PDIV_MASK << PLL0831X_PDIV_SHIFT) | | |
561 | (PLL0831X_SDIV_MASK << PLL0831X_SDIV_SHIFT)); | |
562 | pll_con3 |= (rate->mdiv << PLL0831X_MDIV_SHIFT) | | |
563 | (rate->pdiv << PLL0831X_PDIV_SHIFT) | | |
564 | (rate->sdiv << PLL0831X_SDIV_SHIFT); | |
565 | pll_con5 &= ~(PLL0831X_KDIV_MASK << PLL0831X_KDIV_SHIFT); | |
566 | /* | |
567 | * kdiv is 16-bit 2's complement (s16), but stored as unsigned int. | |
568 | * Cast it to u16 to avoid leading 0xffff's in case of negative value. | |
569 | */ | |
570 | pll_con5 |= ((u16)rate->kdiv << PLL0831X_KDIV_SHIFT); | |
571 | ||
572 | /* Set PLL lock time */ | |
573 | writel_relaxed(rate->pdiv * PLL0831X_LOCK_FACTOR, pll->lock_reg); | |
574 | ||
575 | /* Write PMSK values */ | |
576 | writel_relaxed(pll_con3, pll->con_reg); | |
577 | writel_relaxed(pll_con5, pll->con_reg + 8); | |
578 | ||
579 | /* Wait for PLL lock if the PLL is enabled */ | |
580 | if (pll_con3 & BIT(pll->enable_offs)) | |
581 | return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); | |
582 | ||
583 | return 0; | |
584 | } | |
585 | ||
586 | static const struct clk_ops samsung_pll0831x_clk_ops = { | |
587 | .recalc_rate = samsung_pll0831x_recalc_rate, | |
588 | .set_rate = samsung_pll0831x_set_rate, | |
589 | .round_rate = samsung_pll_round_rate, | |
590 | .enable = samsung_pll3xxx_enable, | |
591 | .disable = samsung_pll3xxx_disable, | |
592 | }; | |
593 | ||
594 | static const struct clk_ops samsung_pll0831x_clk_min_ops = { | |
595 | .recalc_rate = samsung_pll0831x_recalc_rate, | |
596 | }; | |
597 | ||
1c4c5fe0 TA |
598 | /* |
599 | * PLL45xx Clock Type | |
600 | */ | |
b4054ac6 TF |
601 | #define PLL4502_LOCK_FACTOR 400 |
602 | #define PLL4508_LOCK_FACTOR 240 | |
1c4c5fe0 TA |
603 | |
604 | #define PLL45XX_MDIV_MASK (0x3FF) | |
605 | #define PLL45XX_PDIV_MASK (0x3F) | |
606 | #define PLL45XX_SDIV_MASK (0x7) | |
b4054ac6 | 607 | #define PLL45XX_AFC_MASK (0x1F) |
1c4c5fe0 TA |
608 | #define PLL45XX_MDIV_SHIFT (16) |
609 | #define PLL45XX_PDIV_SHIFT (8) | |
610 | #define PLL45XX_SDIV_SHIFT (0) | |
b4054ac6 TF |
611 | #define PLL45XX_AFC_SHIFT (0) |
612 | ||
613 | #define PLL45XX_ENABLE BIT(31) | |
614 | #define PLL45XX_LOCKED BIT(29) | |
1c4c5fe0 | 615 | |
1c4c5fe0 TA |
616 | static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw, |
617 | unsigned long parent_rate) | |
618 | { | |
52b06016 | 619 | struct samsung_clk_pll *pll = to_clk_pll(hw); |
1c4c5fe0 TA |
620 | u32 mdiv, pdiv, sdiv, pll_con; |
621 | u64 fvco = parent_rate; | |
622 | ||
4de10339 | 623 | pll_con = readl_relaxed(pll->con_reg); |
1c4c5fe0 TA |
624 | mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK; |
625 | pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK; | |
626 | sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK; | |
627 | ||
628 | if (pll->type == pll_4508) | |
629 | sdiv = sdiv - 1; | |
630 | ||
631 | fvco *= mdiv; | |
632 | do_div(fvco, (pdiv << sdiv)); | |
633 | ||
634 | return (unsigned long)fvco; | |
635 | } | |
636 | ||
b4054ac6 TF |
637 | static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1, |
638 | const struct samsung_pll_rate_table *rate) | |
639 | { | |
640 | u32 old_mdiv, old_pdiv, old_afc; | |
641 | ||
642 | old_mdiv = (pll_con0 >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK; | |
643 | old_pdiv = (pll_con0 >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK; | |
644 | old_afc = (pll_con1 >> PLL45XX_AFC_SHIFT) & PLL45XX_AFC_MASK; | |
645 | ||
646 | return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv | |
647 | || old_afc != rate->afc); | |
648 | } | |
649 | ||
650 | static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate, | |
651 | unsigned long prate) | |
652 | { | |
653 | struct samsung_clk_pll *pll = to_clk_pll(hw); | |
654 | const struct samsung_pll_rate_table *rate; | |
655 | u32 con0, con1; | |
b4054ac6 TF |
656 | |
657 | /* Get required rate settings from table */ | |
658 | rate = samsung_get_pll_settings(pll, drate); | |
659 | if (!rate) { | |
660 | pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, | |
836ee0f7 | 661 | drate, clk_hw_get_name(hw)); |
b4054ac6 TF |
662 | return -EINVAL; |
663 | } | |
664 | ||
4de10339 ML |
665 | con0 = readl_relaxed(pll->con_reg); |
666 | con1 = readl_relaxed(pll->con_reg + 0x4); | |
b4054ac6 TF |
667 | |
668 | if (!(samsung_pll45xx_mp_change(con0, con1, rate))) { | |
669 | /* If only s change, change just s value only*/ | |
670 | con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT); | |
671 | con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; | |
4de10339 | 672 | writel_relaxed(con0, pll->con_reg); |
b4054ac6 TF |
673 | |
674 | return 0; | |
675 | } | |
676 | ||
677 | /* Set PLL PMS values. */ | |
678 | con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) | | |
679 | (PLL45XX_PDIV_MASK << PLL45XX_PDIV_SHIFT) | | |
680 | (PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT)); | |
681 | con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) | | |
682 | (rate->pdiv << PLL45XX_PDIV_SHIFT) | | |
683 | (rate->sdiv << PLL45XX_SDIV_SHIFT); | |
684 | ||
685 | /* Set PLL AFC value. */ | |
4de10339 | 686 | con1 = readl_relaxed(pll->con_reg + 0x4); |
b4054ac6 TF |
687 | con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT); |
688 | con1 |= (rate->afc << PLL45XX_AFC_SHIFT); | |
689 | ||
690 | /* Set PLL lock time. */ | |
691 | switch (pll->type) { | |
692 | case pll_4502: | |
4de10339 | 693 | writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); |
b4054ac6 TF |
694 | break; |
695 | case pll_4508: | |
4de10339 | 696 | writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); |
b4054ac6 TF |
697 | break; |
698 | default: | |
699 | break; | |
8e31d19b | 700 | } |
b4054ac6 TF |
701 | |
702 | /* Set new configuration. */ | |
4de10339 ML |
703 | writel_relaxed(con1, pll->con_reg + 0x4); |
704 | writel_relaxed(con0, pll->con_reg); | |
b4054ac6 | 705 | |
44a9e78f SN |
706 | /* Wait for PLL lock */ |
707 | return samsung_pll_lock_wait(pll, PLL45XX_LOCKED); | |
b4054ac6 TF |
708 | } |
709 | ||
1c4c5fe0 TA |
710 | static const struct clk_ops samsung_pll45xx_clk_ops = { |
711 | .recalc_rate = samsung_pll45xx_recalc_rate, | |
b4054ac6 TF |
712 | .round_rate = samsung_pll_round_rate, |
713 | .set_rate = samsung_pll45xx_set_rate, | |
714 | }; | |
715 | ||
716 | static const struct clk_ops samsung_pll45xx_clk_min_ops = { | |
717 | .recalc_rate = samsung_pll45xx_recalc_rate, | |
1c4c5fe0 TA |
718 | }; |
719 | ||
1c4c5fe0 TA |
720 | /* |
721 | * PLL46xx Clock Type | |
722 | */ | |
5c89658a | 723 | #define PLL46XX_LOCK_FACTOR 3000 |
1c4c5fe0 | 724 | |
5c89658a | 725 | #define PLL46XX_VSEL_MASK (1) |
1c4c5fe0 | 726 | #define PLL46XX_MDIV_MASK (0x1FF) |
0c23e2af NKC |
727 | #define PLL1460X_MDIV_MASK (0x3FF) |
728 | ||
1c4c5fe0 TA |
729 | #define PLL46XX_PDIV_MASK (0x3F) |
730 | #define PLL46XX_SDIV_MASK (0x7) | |
5c89658a | 731 | #define PLL46XX_VSEL_SHIFT (27) |
1c4c5fe0 TA |
732 | #define PLL46XX_MDIV_SHIFT (16) |
733 | #define PLL46XX_PDIV_SHIFT (8) | |
734 | #define PLL46XX_SDIV_SHIFT (0) | |
735 | ||
736 | #define PLL46XX_KDIV_MASK (0xFFFF) | |
737 | #define PLL4650C_KDIV_MASK (0xFFF) | |
738 | #define PLL46XX_KDIV_SHIFT (0) | |
5c89658a TF |
739 | #define PLL46XX_MFR_MASK (0x3F) |
740 | #define PLL46XX_MRR_MASK (0x1F) | |
741 | #define PLL46XX_KDIV_SHIFT (0) | |
742 | #define PLL46XX_MFR_SHIFT (16) | |
743 | #define PLL46XX_MRR_SHIFT (24) | |
744 | ||
745 | #define PLL46XX_ENABLE BIT(31) | |
746 | #define PLL46XX_LOCKED BIT(29) | |
747 | #define PLL46XX_VSEL BIT(27) | |
1c4c5fe0 | 748 | |
1c4c5fe0 TA |
749 | static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, |
750 | unsigned long parent_rate) | |
751 | { | |
c50d11f3 | 752 | struct samsung_clk_pll *pll = to_clk_pll(hw); |
1c4c5fe0 TA |
753 | u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift; |
754 | u64 fvco = parent_rate; | |
755 | ||
4de10339 ML |
756 | pll_con0 = readl_relaxed(pll->con_reg); |
757 | pll_con1 = readl_relaxed(pll->con_reg + 4); | |
0c23e2af NKC |
758 | mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? |
759 | PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK); | |
1c4c5fe0 TA |
760 | pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; |
761 | sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; | |
762 | kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK : | |
763 | pll_con1 & PLL46XX_KDIV_MASK; | |
764 | ||
0c23e2af NKC |
765 | shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10; |
766 | ||
1c4c5fe0 TA |
767 | fvco *= (mdiv << shift) + kdiv; |
768 | do_div(fvco, (pdiv << sdiv)); | |
769 | fvco >>= shift; | |
770 | ||
771 | return (unsigned long)fvco; | |
772 | } | |
773 | ||
5c89658a TF |
774 | static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1, |
775 | const struct samsung_pll_rate_table *rate) | |
776 | { | |
777 | u32 old_mdiv, old_pdiv, old_kdiv; | |
778 | ||
779 | old_mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; | |
780 | old_pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; | |
781 | old_kdiv = (pll_con1 >> PLL46XX_KDIV_SHIFT) & PLL46XX_KDIV_MASK; | |
782 | ||
783 | return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv | |
784 | || old_kdiv != rate->kdiv); | |
785 | } | |
786 | ||
787 | static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, | |
788 | unsigned long prate) | |
789 | { | |
790 | struct samsung_clk_pll *pll = to_clk_pll(hw); | |
791 | const struct samsung_pll_rate_table *rate; | |
792 | u32 con0, con1, lock; | |
5c89658a TF |
793 | |
794 | /* Get required rate settings from table */ | |
795 | rate = samsung_get_pll_settings(pll, drate); | |
796 | if (!rate) { | |
797 | pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, | |
836ee0f7 | 798 | drate, clk_hw_get_name(hw)); |
5c89658a TF |
799 | return -EINVAL; |
800 | } | |
801 | ||
4de10339 ML |
802 | con0 = readl_relaxed(pll->con_reg); |
803 | con1 = readl_relaxed(pll->con_reg + 0x4); | |
5c89658a TF |
804 | |
805 | if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) { | |
806 | /* If only s change, change just s value only*/ | |
807 | con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); | |
808 | con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT; | |
4de10339 | 809 | writel_relaxed(con0, pll->con_reg); |
5c89658a TF |
810 | |
811 | return 0; | |
812 | } | |
813 | ||
814 | /* Set PLL lock time. */ | |
815 | lock = rate->pdiv * PLL46XX_LOCK_FACTOR; | |
816 | if (lock > 0xffff) | |
817 | /* Maximum lock time bitfield is 16-bit. */ | |
818 | lock = 0xffff; | |
819 | ||
820 | /* Set PLL PMS and VSEL values. */ | |
0c23e2af NKC |
821 | if (pll->type == pll_1460x) { |
822 | con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) | | |
823 | (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | | |
824 | (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT)); | |
825 | } else { | |
826 | con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) | | |
5c89658a TF |
827 | (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | |
828 | (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) | | |
829 | (PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT)); | |
0c23e2af NKC |
830 | con0 |= rate->vsel << PLL46XX_VSEL_SHIFT; |
831 | } | |
832 | ||
5c89658a TF |
833 | con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) | |
834 | (rate->pdiv << PLL46XX_PDIV_SHIFT) | | |
0c23e2af | 835 | (rate->sdiv << PLL46XX_SDIV_SHIFT); |
5c89658a TF |
836 | |
837 | /* Set PLL K, MFR and MRR values. */ | |
4de10339 | 838 | con1 = readl_relaxed(pll->con_reg + 0x4); |
5c89658a TF |
839 | con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) | |
840 | (PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) | | |
841 | (PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT)); | |
842 | con1 |= (rate->kdiv << PLL46XX_KDIV_SHIFT) | | |
843 | (rate->mfr << PLL46XX_MFR_SHIFT) | | |
844 | (rate->mrr << PLL46XX_MRR_SHIFT); | |
845 | ||
846 | /* Write configuration to PLL */ | |
4de10339 ML |
847 | writel_relaxed(lock, pll->lock_reg); |
848 | writel_relaxed(con0, pll->con_reg); | |
849 | writel_relaxed(con1, pll->con_reg + 0x4); | |
5c89658a | 850 | |
44a9e78f SN |
851 | /* Wait for PLL lock */ |
852 | return samsung_pll_lock_wait(pll, PLL46XX_LOCKED); | |
5c89658a TF |
853 | } |
854 | ||
1c4c5fe0 TA |
855 | static const struct clk_ops samsung_pll46xx_clk_ops = { |
856 | .recalc_rate = samsung_pll46xx_recalc_rate, | |
5c89658a TF |
857 | .round_rate = samsung_pll_round_rate, |
858 | .set_rate = samsung_pll46xx_set_rate, | |
859 | }; | |
860 | ||
861 | static const struct clk_ops samsung_pll46xx_clk_min_ops = { | |
862 | .recalc_rate = samsung_pll46xx_recalc_rate, | |
1c4c5fe0 TA |
863 | }; |
864 | ||
eb527121 TF |
865 | /* |
866 | * PLL6552 Clock Type | |
867 | */ | |
868 | ||
eb527121 TF |
869 | #define PLL6552_MDIV_MASK 0x3ff |
870 | #define PLL6552_PDIV_MASK 0x3f | |
871 | #define PLL6552_SDIV_MASK 0x7 | |
872 | #define PLL6552_MDIV_SHIFT 16 | |
06654acb | 873 | #define PLL6552_MDIV_SHIFT_2416 14 |
eb527121 | 874 | #define PLL6552_PDIV_SHIFT 8 |
06654acb | 875 | #define PLL6552_PDIV_SHIFT_2416 5 |
eb527121 TF |
876 | #define PLL6552_SDIV_SHIFT 0 |
877 | ||
eb527121 TF |
878 | static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw, |
879 | unsigned long parent_rate) | |
880 | { | |
40ef723c | 881 | struct samsung_clk_pll *pll = to_clk_pll(hw); |
eb527121 TF |
882 | u32 mdiv, pdiv, sdiv, pll_con; |
883 | u64 fvco = parent_rate; | |
884 | ||
4de10339 | 885 | pll_con = readl_relaxed(pll->con_reg); |
06654acb HS |
886 | if (pll->type == pll_6552_s3c2416) { |
887 | mdiv = (pll_con >> PLL6552_MDIV_SHIFT_2416) & PLL6552_MDIV_MASK; | |
888 | pdiv = (pll_con >> PLL6552_PDIV_SHIFT_2416) & PLL6552_PDIV_MASK; | |
889 | } else { | |
890 | mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK; | |
891 | pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK; | |
892 | } | |
eb527121 TF |
893 | sdiv = (pll_con >> PLL6552_SDIV_SHIFT) & PLL6552_SDIV_MASK; |
894 | ||
895 | fvco *= mdiv; | |
896 | do_div(fvco, (pdiv << sdiv)); | |
897 | ||
898 | return (unsigned long)fvco; | |
899 | } | |
900 | ||
901 | static const struct clk_ops samsung_pll6552_clk_ops = { | |
902 | .recalc_rate = samsung_pll6552_recalc_rate, | |
903 | }; | |
904 | ||
eb527121 TF |
905 | /* |
906 | * PLL6553 Clock Type | |
907 | */ | |
908 | ||
eb527121 TF |
909 | #define PLL6553_MDIV_MASK 0xff |
910 | #define PLL6553_PDIV_MASK 0x3f | |
911 | #define PLL6553_SDIV_MASK 0x7 | |
912 | #define PLL6553_KDIV_MASK 0xffff | |
913 | #define PLL6553_MDIV_SHIFT 16 | |
914 | #define PLL6553_PDIV_SHIFT 8 | |
915 | #define PLL6553_SDIV_SHIFT 0 | |
916 | #define PLL6553_KDIV_SHIFT 0 | |
917 | ||
eb527121 TF |
918 | static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw, |
919 | unsigned long parent_rate) | |
920 | { | |
40ef723c | 921 | struct samsung_clk_pll *pll = to_clk_pll(hw); |
eb527121 TF |
922 | u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1; |
923 | u64 fvco = parent_rate; | |
924 | ||
4de10339 ML |
925 | pll_con0 = readl_relaxed(pll->con_reg); |
926 | pll_con1 = readl_relaxed(pll->con_reg + 0x4); | |
eb527121 TF |
927 | mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK; |
928 | pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK; | |
929 | sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK; | |
930 | kdiv = (pll_con1 >> PLL6553_KDIV_SHIFT) & PLL6553_KDIV_MASK; | |
931 | ||
932 | fvco *= (mdiv << 16) + kdiv; | |
933 | do_div(fvco, (pdiv << sdiv)); | |
934 | fvco >>= 16; | |
935 | ||
936 | return (unsigned long)fvco; | |
937 | } | |
938 | ||
939 | static const struct clk_ops samsung_pll6553_clk_ops = { | |
940 | .recalc_rate = samsung_pll6553_recalc_rate, | |
941 | }; | |
942 | ||
1c4c5fe0 TA |
943 | /* |
944 | * PLL2550x Clock Type | |
945 | */ | |
946 | ||
947 | #define PLL2550X_R_MASK (0x1) | |
948 | #define PLL2550X_P_MASK (0x3F) | |
949 | #define PLL2550X_M_MASK (0x3FF) | |
950 | #define PLL2550X_S_MASK (0x7) | |
951 | #define PLL2550X_R_SHIFT (20) | |
952 | #define PLL2550X_P_SHIFT (14) | |
953 | #define PLL2550X_M_SHIFT (4) | |
954 | #define PLL2550X_S_SHIFT (0) | |
955 | ||
1c4c5fe0 TA |
956 | static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw, |
957 | unsigned long parent_rate) | |
958 | { | |
1d9aa64c | 959 | struct samsung_clk_pll *pll = to_clk_pll(hw); |
1c4c5fe0 TA |
960 | u32 r, p, m, s, pll_stat; |
961 | u64 fvco = parent_rate; | |
962 | ||
1d9aa64c | 963 | pll_stat = readl_relaxed(pll->con_reg); |
1c4c5fe0 TA |
964 | r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK; |
965 | if (!r) | |
966 | return 0; | |
967 | p = (pll_stat >> PLL2550X_P_SHIFT) & PLL2550X_P_MASK; | |
968 | m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK; | |
969 | s = (pll_stat >> PLL2550X_S_SHIFT) & PLL2550X_S_MASK; | |
970 | ||
971 | fvco *= m; | |
972 | do_div(fvco, (p << s)); | |
973 | ||
974 | return (unsigned long)fvco; | |
975 | } | |
976 | ||
1c4c5fe0 TA |
977 | static const struct clk_ops samsung_pll2550x_clk_ops = { |
978 | .recalc_rate = samsung_pll2550x_recalc_rate, | |
1c4c5fe0 TA |
979 | }; |
980 | ||
84329847 PD |
981 | /* |
982 | * PLL2550xx Clock Type | |
983 | */ | |
984 | ||
985 | /* Maximum lock time can be 270 * PDIV cycles */ | |
986 | #define PLL2550XX_LOCK_FACTOR 270 | |
987 | ||
988 | #define PLL2550XX_M_MASK 0x3FF | |
989 | #define PLL2550XX_P_MASK 0x3F | |
990 | #define PLL2550XX_S_MASK 0x7 | |
991 | #define PLL2550XX_LOCK_STAT_MASK 0x1 | |
992 | #define PLL2550XX_M_SHIFT 9 | |
993 | #define PLL2550XX_P_SHIFT 3 | |
994 | #define PLL2550XX_S_SHIFT 0 | |
995 | #define PLL2550XX_LOCK_STAT_SHIFT 21 | |
996 | ||
997 | static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, | |
998 | unsigned long parent_rate) | |
999 | { | |
1000 | struct samsung_clk_pll *pll = to_clk_pll(hw); | |
1001 | u32 mdiv, pdiv, sdiv, pll_con; | |
1002 | u64 fvco = parent_rate; | |
1003 | ||
4de10339 | 1004 | pll_con = readl_relaxed(pll->con_reg); |
84329847 PD |
1005 | mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK; |
1006 | pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK; | |
1007 | sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK; | |
1008 | ||
1009 | fvco *= mdiv; | |
1010 | do_div(fvco, (pdiv << sdiv)); | |
1011 | ||
1012 | return (unsigned long)fvco; | |
1013 | } | |
1014 | ||
1015 | static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) | |
1016 | { | |
1017 | u32 old_mdiv, old_pdiv; | |
1018 | ||
1019 | old_mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK; | |
1020 | old_pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK; | |
1021 | ||
1022 | return mdiv != old_mdiv || pdiv != old_pdiv; | |
1023 | } | |
1024 | ||
1025 | static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, | |
1026 | unsigned long prate) | |
1027 | { | |
1028 | struct samsung_clk_pll *pll = to_clk_pll(hw); | |
1029 | const struct samsung_pll_rate_table *rate; | |
1030 | u32 tmp; | |
1031 | ||
1032 | /* Get required rate settings from table */ | |
1033 | rate = samsung_get_pll_settings(pll, drate); | |
1034 | if (!rate) { | |
1035 | pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, | |
836ee0f7 | 1036 | drate, clk_hw_get_name(hw)); |
84329847 PD |
1037 | return -EINVAL; |
1038 | } | |
1039 | ||
4de10339 | 1040 | tmp = readl_relaxed(pll->con_reg); |
84329847 PD |
1041 | |
1042 | if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { | |
1043 | /* If only s change, change just s value only*/ | |
1044 | tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT); | |
1045 | tmp |= rate->sdiv << PLL2550XX_S_SHIFT; | |
4de10339 | 1046 | writel_relaxed(tmp, pll->con_reg); |
84329847 PD |
1047 | |
1048 | return 0; | |
1049 | } | |
1050 | ||
1051 | /* Set PLL lock time. */ | |
4de10339 | 1052 | writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); |
84329847 PD |
1053 | |
1054 | /* Change PLL PMS values */ | |
1055 | tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) | | |
1056 | (PLL2550XX_P_MASK << PLL2550XX_P_SHIFT) | | |
1057 | (PLL2550XX_S_MASK << PLL2550XX_S_SHIFT)); | |
1058 | tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) | | |
1059 | (rate->pdiv << PLL2550XX_P_SHIFT) | | |
1060 | (rate->sdiv << PLL2550XX_S_SHIFT); | |
4de10339 | 1061 | writel_relaxed(tmp, pll->con_reg); |
84329847 | 1062 | |
44a9e78f SN |
1063 | /* Wait for PLL lock */ |
1064 | return samsung_pll_lock_wait(pll, | |
1065 | PLL2550XX_LOCK_STAT_MASK << PLL2550XX_LOCK_STAT_SHIFT); | |
84329847 PD |
1066 | } |
1067 | ||
1068 | static const struct clk_ops samsung_pll2550xx_clk_ops = { | |
1069 | .recalc_rate = samsung_pll2550xx_recalc_rate, | |
1070 | .round_rate = samsung_pll_round_rate, | |
1071 | .set_rate = samsung_pll2550xx_set_rate, | |
1072 | }; | |
1073 | ||
1074 | static const struct clk_ops samsung_pll2550xx_clk_min_ops = { | |
1075 | .recalc_rate = samsung_pll2550xx_recalc_rate, | |
1076 | }; | |
1077 | ||
be95d2c7 SN |
1078 | /* |
1079 | * PLL2650x Clock Type | |
1080 | */ | |
1081 | ||
1082 | /* Maximum lock time can be 3000 * PDIV cycles */ | |
1083 | #define PLL2650X_LOCK_FACTOR 3000 | |
1084 | ||
1085 | #define PLL2650X_M_MASK 0x1ff | |
1086 | #define PLL2650X_P_MASK 0x3f | |
1087 | #define PLL2650X_S_MASK 0x7 | |
1088 | #define PLL2650X_K_MASK 0xffff | |
1089 | #define PLL2650X_LOCK_STAT_MASK 0x1 | |
1090 | #define PLL2650X_M_SHIFT 16 | |
1091 | #define PLL2650X_P_SHIFT 8 | |
1092 | #define PLL2650X_S_SHIFT 0 | |
1093 | #define PLL2650X_K_SHIFT 0 | |
1094 | #define PLL2650X_LOCK_STAT_SHIFT 29 | |
1095 | #define PLL2650X_PLL_ENABLE_SHIFT 31 | |
1096 | ||
1097 | static unsigned long samsung_pll2650x_recalc_rate(struct clk_hw *hw, | |
1098 | unsigned long parent_rate) | |
1099 | { | |
1100 | struct samsung_clk_pll *pll = to_clk_pll(hw); | |
1101 | u64 fout = parent_rate; | |
1102 | u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; | |
1103 | s16 kdiv; | |
1104 | ||
1105 | pll_con0 = readl_relaxed(pll->con_reg); | |
1106 | mdiv = (pll_con0 >> PLL2650X_M_SHIFT) & PLL2650X_M_MASK; | |
1107 | pdiv = (pll_con0 >> PLL2650X_P_SHIFT) & PLL2650X_P_MASK; | |
1108 | sdiv = (pll_con0 >> PLL2650X_S_SHIFT) & PLL2650X_S_MASK; | |
1109 | ||
1110 | pll_con1 = readl_relaxed(pll->con_reg + 4); | |
1111 | kdiv = (s16)((pll_con1 >> PLL2650X_K_SHIFT) & PLL2650X_K_MASK); | |
1112 | ||
1113 | fout *= (mdiv << 16) + kdiv; | |
1114 | do_div(fout, (pdiv << sdiv)); | |
1115 | fout >>= 16; | |
1116 | ||
1117 | return (unsigned long)fout; | |
1118 | } | |
1119 | ||
1120 | static int samsung_pll2650x_set_rate(struct clk_hw *hw, unsigned long drate, | |
1121 | unsigned long prate) | |
1122 | { | |
1123 | struct samsung_clk_pll *pll = to_clk_pll(hw); | |
1124 | const struct samsung_pll_rate_table *rate; | |
1125 | u32 con0, con1; | |
1126 | ||
1127 | /* Get required rate settings from table */ | |
1128 | rate = samsung_get_pll_settings(pll, drate); | |
1129 | if (!rate) { | |
1130 | pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, | |
1131 | drate, clk_hw_get_name(hw)); | |
1132 | return -EINVAL; | |
1133 | } | |
1134 | ||
1135 | con0 = readl_relaxed(pll->con_reg); | |
1136 | con1 = readl_relaxed(pll->con_reg + 4); | |
1137 | ||
1138 | /* Set PLL lock time. */ | |
1139 | writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg); | |
1140 | ||
1141 | /* Change PLL PMS values */ | |
1142 | con0 &= ~((PLL2650X_M_MASK << PLL2650X_M_SHIFT) | | |
1143 | (PLL2650X_P_MASK << PLL2650X_P_SHIFT) | | |
1144 | (PLL2650X_S_MASK << PLL2650X_S_SHIFT)); | |
1145 | con0 |= (rate->mdiv << PLL2650X_M_SHIFT) | | |
1146 | (rate->pdiv << PLL2650X_P_SHIFT) | | |
1147 | (rate->sdiv << PLL2650X_S_SHIFT); | |
1148 | con0 |= (1 << PLL2650X_PLL_ENABLE_SHIFT); | |
1149 | writel_relaxed(con0, pll->con_reg); | |
1150 | ||
1151 | con1 &= ~(PLL2650X_K_MASK << PLL2650X_K_SHIFT); | |
1152 | con1 |= ((rate->kdiv & PLL2650X_K_MASK) << PLL2650X_K_SHIFT); | |
1153 | writel_relaxed(con1, pll->con_reg + 4); | |
1154 | ||
44a9e78f SN |
1155 | /* Wait for PLL lock */ |
1156 | return samsung_pll_lock_wait(pll, | |
1157 | PLL2650X_LOCK_STAT_MASK << PLL2650X_LOCK_STAT_SHIFT); | |
be95d2c7 SN |
1158 | } |
1159 | ||
1160 | static const struct clk_ops samsung_pll2650x_clk_ops = { | |
1161 | .recalc_rate = samsung_pll2650x_recalc_rate, | |
1162 | .round_rate = samsung_pll_round_rate, | |
1163 | .set_rate = samsung_pll2650x_set_rate, | |
1164 | }; | |
1165 | ||
1166 | static const struct clk_ops samsung_pll2650x_clk_min_ops = { | |
1167 | .recalc_rate = samsung_pll2650x_recalc_rate, | |
1168 | }; | |
1169 | ||
eefe119b RS |
1170 | /* |
1171 | * PLL2650XX Clock Type | |
1172 | */ | |
1173 | ||
1174 | /* Maximum lock time can be 3000 * PDIV cycles */ | |
1175 | #define PLL2650XX_LOCK_FACTOR 3000 | |
1176 | ||
1177 | #define PLL2650XX_MDIV_SHIFT 9 | |
1178 | #define PLL2650XX_PDIV_SHIFT 3 | |
1179 | #define PLL2650XX_SDIV_SHIFT 0 | |
1180 | #define PLL2650XX_KDIV_SHIFT 0 | |
1181 | #define PLL2650XX_MDIV_MASK 0x1ff | |
1182 | #define PLL2650XX_PDIV_MASK 0x3f | |
1183 | #define PLL2650XX_SDIV_MASK 0x7 | |
1184 | #define PLL2650XX_KDIV_MASK 0xffff | |
1185 | #define PLL2650XX_PLL_ENABLE_SHIFT 23 | |
1186 | #define PLL2650XX_PLL_LOCKTIME_SHIFT 21 | |
1187 | #define PLL2650XX_PLL_FOUTMASK_SHIFT 31 | |
1188 | ||
1189 | static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw, | |
1190 | unsigned long parent_rate) | |
1191 | { | |
1192 | struct samsung_clk_pll *pll = to_clk_pll(hw); | |
1193 | u32 mdiv, pdiv, sdiv, pll_con0, pll_con2; | |
1194 | s16 kdiv; | |
1195 | u64 fvco = parent_rate; | |
1196 | ||
4de10339 ML |
1197 | pll_con0 = readl_relaxed(pll->con_reg); |
1198 | pll_con2 = readl_relaxed(pll->con_reg + 8); | |
eefe119b RS |
1199 | mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK; |
1200 | pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK; | |
1201 | sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK; | |
1202 | kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK); | |
1203 | ||
1204 | fvco *= (mdiv << 16) + kdiv; | |
1205 | do_div(fvco, (pdiv << sdiv)); | |
1206 | fvco >>= 16; | |
1207 | ||
1208 | return (unsigned long)fvco; | |
1209 | } | |
1210 | ||
1211 | static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate, | |
1212 | unsigned long parent_rate) | |
1213 | { | |
1214 | struct samsung_clk_pll *pll = to_clk_pll(hw); | |
44a9e78f | 1215 | u32 pll_con0, pll_con2; |
eefe119b RS |
1216 | const struct samsung_pll_rate_table *rate; |
1217 | ||
1218 | rate = samsung_get_pll_settings(pll, drate); | |
1219 | if (!rate) { | |
1220 | pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, | |
836ee0f7 | 1221 | drate, clk_hw_get_name(hw)); |
eefe119b RS |
1222 | return -EINVAL; |
1223 | } | |
1224 | ||
4de10339 ML |
1225 | pll_con0 = readl_relaxed(pll->con_reg); |
1226 | pll_con2 = readl_relaxed(pll->con_reg + 8); | |
eefe119b RS |
1227 | |
1228 | /* Change PLL PMS values */ | |
1229 | pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT | | |
1230 | PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT | | |
1231 | PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT); | |
1232 | pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT; | |
1233 | pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT; | |
1234 | pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT; | |
1235 | pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT; | |
1236 | pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT; | |
1237 | ||
1238 | pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT); | |
1239 | pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK) | |
1240 | << PLL2650XX_KDIV_SHIFT; | |
1241 | ||
1242 | /* Set PLL lock time. */ | |
4de10339 | 1243 | writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); |
eefe119b | 1244 | |
4de10339 ML |
1245 | writel_relaxed(pll_con0, pll->con_reg); |
1246 | writel_relaxed(pll_con2, pll->con_reg + 8); | |
eefe119b | 1247 | |
44a9e78f | 1248 | return samsung_pll_lock_wait(pll, 0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT); |
eefe119b RS |
1249 | } |
1250 | ||
1251 | static const struct clk_ops samsung_pll2650xx_clk_ops = { | |
1252 | .recalc_rate = samsung_pll2650xx_recalc_rate, | |
1253 | .set_rate = samsung_pll2650xx_set_rate, | |
1254 | .round_rate = samsung_pll_round_rate, | |
1255 | }; | |
1256 | ||
1257 | static const struct clk_ops samsung_pll2650xx_clk_min_ops = { | |
1258 | .recalc_rate = samsung_pll2650xx_recalc_rate, | |
1259 | }; | |
1260 | ||
976face4 | 1261 | static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, |
65bf1fbe | 1262 | const struct samsung_pll_clock *pll_clk) |
07dc76fa YSB |
1263 | { |
1264 | struct samsung_clk_pll *pll; | |
07dc76fa | 1265 | struct clk_init_data init; |
3ff6e0d8 | 1266 | int ret, len; |
07dc76fa YSB |
1267 | |
1268 | pll = kzalloc(sizeof(*pll), GFP_KERNEL); | |
1269 | if (!pll) { | |
1270 | pr_err("%s: could not allocate pll clk %s\n", | |
1271 | __func__, pll_clk->name); | |
1272 | return; | |
1273 | } | |
1274 | ||
1275 | init.name = pll_clk->name; | |
1276 | init.flags = pll_clk->flags; | |
1277 | init.parent_names = &pll_clk->parent_name; | |
1278 | init.num_parents = 1; | |
1279 | ||
3ff6e0d8 YSB |
1280 | if (pll_clk->rate_table) { |
1281 | /* find count of rates in rate_table */ | |
1282 | for (len = 0; pll_clk->rate_table[len].rate != 0; ) | |
1283 | len++; | |
1284 | ||
1285 | pll->rate_count = len; | |
1286 | pll->rate_table = kmemdup(pll_clk->rate_table, | |
1287 | pll->rate_count * | |
1288 | sizeof(struct samsung_pll_rate_table), | |
1289 | GFP_KERNEL); | |
1290 | WARN(!pll->rate_table, | |
1291 | "%s: could not allocate rate table for %s\n", | |
1292 | __func__, pll_clk->name); | |
1293 | } | |
1294 | ||
07dc76fa | 1295 | switch (pll_clk->type) { |
a951b1d9 HS |
1296 | case pll_2126: |
1297 | init.ops = &samsung_pll2126_clk_ops; | |
1298 | break; | |
1299 | case pll_3000: | |
1300 | init.ops = &samsung_pll3000_clk_ops; | |
1301 | break; | |
07dc76fa YSB |
1302 | /* clk_ops for 35xx and 2550 are similar */ |
1303 | case pll_35xx: | |
1304 | case pll_2550: | |
0c23e2af NKC |
1305 | case pll_1450x: |
1306 | case pll_1451x: | |
1307 | case pll_1452x: | |
4f346005 | 1308 | case pll_142xx: |
6edfa11c SN |
1309 | pll->enable_offs = PLL35XX_ENABLE_SHIFT; |
1310 | pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; | |
dfa89319 YSB |
1311 | if (!pll->rate_table) |
1312 | init.ops = &samsung_pll35xx_clk_min_ops; | |
1313 | else | |
1314 | init.ops = &samsung_pll35xx_clk_ops; | |
07dc76fa | 1315 | break; |
c703a2f4 | 1316 | case pll_1417x: |
f2819ea1 | 1317 | case pll_0818x: |
8f90f43a SP |
1318 | case pll_0822x: |
1319 | pll->enable_offs = PLL0822X_ENABLE_SHIFT; | |
1320 | pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; | |
1321 | if (!pll->rate_table) | |
1322 | init.ops = &samsung_pll0822x_clk_min_ops; | |
1323 | else | |
1324 | init.ops = &samsung_pll0822x_clk_ops; | |
1325 | break; | |
52b06016 | 1326 | case pll_4500: |
b4054ac6 TF |
1327 | init.ops = &samsung_pll45xx_clk_min_ops; |
1328 | break; | |
52b06016 TF |
1329 | case pll_4502: |
1330 | case pll_4508: | |
b4054ac6 TF |
1331 | if (!pll->rate_table) |
1332 | init.ops = &samsung_pll45xx_clk_min_ops; | |
1333 | else | |
1334 | init.ops = &samsung_pll45xx_clk_ops; | |
52b06016 | 1335 | break; |
07dc76fa YSB |
1336 | /* clk_ops for 36xx and 2650 are similar */ |
1337 | case pll_36xx: | |
1338 | case pll_2650: | |
6edfa11c SN |
1339 | pll->enable_offs = PLL36XX_ENABLE_SHIFT; |
1340 | pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT; | |
bb4278dc VS |
1341 | if (!pll->rate_table) |
1342 | init.ops = &samsung_pll36xx_clk_min_ops; | |
1343 | else | |
1344 | init.ops = &samsung_pll36xx_clk_ops; | |
07dc76fa | 1345 | break; |
6a734b37 SP |
1346 | case pll_0831x: |
1347 | pll->enable_offs = PLL0831X_ENABLE_SHIFT; | |
1348 | pll->lock_offs = PLL0831X_LOCK_STAT_SHIFT; | |
1349 | if (!pll->rate_table) | |
1350 | init.ops = &samsung_pll0831x_clk_min_ops; | |
1351 | else | |
1352 | init.ops = &samsung_pll0831x_clk_ops; | |
1353 | break; | |
40ef723c | 1354 | case pll_6552: |
06654acb | 1355 | case pll_6552_s3c2416: |
40ef723c TF |
1356 | init.ops = &samsung_pll6552_clk_ops; |
1357 | break; | |
1358 | case pll_6553: | |
1359 | init.ops = &samsung_pll6553_clk_ops; | |
1360 | break; | |
c50d11f3 TF |
1361 | case pll_4600: |
1362 | case pll_4650: | |
1363 | case pll_4650c: | |
0c23e2af | 1364 | case pll_1460x: |
5c89658a TF |
1365 | if (!pll->rate_table) |
1366 | init.ops = &samsung_pll46xx_clk_min_ops; | |
1367 | else | |
1368 | init.ops = &samsung_pll46xx_clk_ops; | |
c50d11f3 | 1369 | break; |
1d9aa64c SN |
1370 | case pll_2550x: |
1371 | init.ops = &samsung_pll2550x_clk_ops; | |
1372 | break; | |
84329847 PD |
1373 | case pll_2550xx: |
1374 | if (!pll->rate_table) | |
1375 | init.ops = &samsung_pll2550xx_clk_min_ops; | |
1376 | else | |
1377 | init.ops = &samsung_pll2550xx_clk_ops; | |
1378 | break; | |
be95d2c7 SN |
1379 | case pll_2650x: |
1380 | if (!pll->rate_table) | |
1381 | init.ops = &samsung_pll2650x_clk_min_ops; | |
1382 | else | |
1383 | init.ops = &samsung_pll2650x_clk_ops; | |
1384 | break; | |
eefe119b RS |
1385 | case pll_2650xx: |
1386 | if (!pll->rate_table) | |
1387 | init.ops = &samsung_pll2650xx_clk_min_ops; | |
1388 | else | |
1389 | init.ops = &samsung_pll2650xx_clk_ops; | |
1390 | break; | |
07dc76fa YSB |
1391 | default: |
1392 | pr_warn("%s: Unknown pll type for pll clk %s\n", | |
1393 | __func__, pll_clk->name); | |
1394 | } | |
1395 | ||
1396 | pll->hw.init = &init; | |
1397 | pll->type = pll_clk->type; | |
65bf1fbe SP |
1398 | pll->lock_reg = ctx->reg_base + pll_clk->lock_offset; |
1399 | pll->con_reg = ctx->reg_base + pll_clk->con_offset; | |
07dc76fa | 1400 | |
d2f18d7e | 1401 | ret = clk_hw_register(ctx->dev, &pll->hw); |
ecb1f1f7 MS |
1402 | if (ret) { |
1403 | pr_err("%s: failed to register pll clock %s : %d\n", | |
1404 | __func__, pll_clk->name, ret); | |
5174e5b0 | 1405 | kfree(pll->rate_table); |
07dc76fa YSB |
1406 | kfree(pll); |
1407 | return; | |
1408 | } | |
1409 | ||
ecb1f1f7 | 1410 | samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id); |
07dc76fa YSB |
1411 | } |
1412 | ||
976face4 | 1413 | void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, |
4a1caed3 | 1414 | const struct samsung_pll_clock *pll_list, |
65bf1fbe | 1415 | unsigned int nr_pll) |
07dc76fa YSB |
1416 | { |
1417 | int cnt; | |
1418 | ||
1419 | for (cnt = 0; cnt < nr_pll; cnt++) | |
65bf1fbe | 1420 | _samsung_clk_register_pll(ctx, &pll_list[cnt]); |
07dc76fa | 1421 | } |