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clk: samsung: exynos7: add clocks for SPI block
[linux-block.git] / drivers / clk / samsung / clk-exynos7.c
CommitLineData
532abc3a
NKC		 1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9*/
10
11#include <linux/clk.h>
12#include <linux/clkdev.h>
13#include <linux/clk-provider.h>
14#include <linux/of.h>
15
16#include "clk.h"
17#include <dt-bindings/clock/exynos7-clk.h>
18
19/* Register Offset definitions for CMU_TOPC (0x10570000) */
20#define CC_PLL_LOCK 0x0000
21#define BUS0_PLL_LOCK 0x0004
22#define BUS1_DPLL_LOCK 0x0008
23#define MFC_PLL_LOCK 0x000C
24#define AUD_PLL_LOCK 0x0010
25#define CC_PLL_CON0 0x0100
26#define BUS0_PLL_CON0 0x0110
27#define BUS1_DPLL_CON0 0x0120
28#define MFC_PLL_CON0 0x0130
29#define AUD_PLL_CON0 0x0140
30#define MUX_SEL_TOPC0 0x0200
31#define MUX_SEL_TOPC1 0x0204
f5e127cd 32#define MUX_SEL_TOPC2 0x0208
532abc3a 33#define MUX_SEL_TOPC3 0x020C
f5e127cd 34#define DIV_TOPC0 0x0600
532abc3a
NKC		 35#define DIV_TOPC1 0x0604
36#define DIV_TOPC3 0x060C
49cab82c 37#define ENABLE_ACLK_TOPC1 0x0804
532abc3a
NKC		 38
39static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
40 FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0),
41 FFACTOR(0, "ffac_topc_bus0_pll_div4",
42 "ffac_topc_bus0_pll_div2", 1, 2, 0),
43 FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0),
44 FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0),
45 FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0),
46};
47
48/* List of parent clocks for Muxes in CMU_TOPC */
49PNAME(mout_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
50PNAME(mout_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
51PNAME(mout_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
52PNAME(mout_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" };
53
54PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc",
55 "mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc",
56 "mout_sclk_mfc_pll_cmuc" };
57
58PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl",
59 "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
60PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl",
61 "ffac_topc_bus1_pll_div2"};
62PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl",
63 "ffac_topc_cc_pll_div2"};
64PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl",
65 "ffac_topc_mfc_pll_div2"};
66
67
68PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl",
69 "ffac_topc_bus0_pll_div2"};
70
71static unsigned long topc_clk_regs[] __initdata = {
72 CC_PLL_LOCK,
73 BUS0_PLL_LOCK,
74 BUS1_DPLL_LOCK,
75 MFC_PLL_LOCK,
76 AUD_PLL_LOCK,
77 CC_PLL_CON0,
78 BUS0_PLL_CON0,
79 BUS1_DPLL_CON0,
80 MFC_PLL_CON0,
81 AUD_PLL_CON0,
82 MUX_SEL_TOPC0,
83 MUX_SEL_TOPC1,
f5e127cd 84 MUX_SEL_TOPC2,
532abc3a 85 MUX_SEL_TOPC3,
f5e127cd 86 DIV_TOPC0,
532abc3a
NKC		 87 DIV_TOPC1,
88 DIV_TOPC3,
89};
90
91static struct samsung_mux_clock topc_mux_clks[] __initdata = {
92 MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1),
93 MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1),
94 MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1),
95 MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1),
96
97 MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p,
98 MUX_SEL_TOPC0, 16, 2),
99 MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p,
100 MUX_SEL_TOPC0, 20, 1),
101 MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p,
102 MUX_SEL_TOPC0, 24, 1),
103 MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p,
104 MUX_SEL_TOPC0, 28, 1),
105
106 MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
107 MUX_SEL_TOPC1, 16, 1),
108
f5e127cd
NKC		 109 MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
110
49cab82c 111 MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2),
532abc3a
NKC		 112 MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
113};
114
115static struct samsung_div_clock topc_div_clks[] __initdata = {
f5e127cd
NKC		 116 DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
117 DIV_TOPC0, 4, 4),
118
49cab82c
TN		 119 DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532",
120 DIV_TOPC1, 20, 4),
532abc3a
NKC		 121 DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
122 DIV_TOPC1, 24, 4),
123
124 DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out",
125 DIV_TOPC3, 0, 3),
126 DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl",
127 DIV_TOPC3, 8, 3),
128 DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl",
129 DIV_TOPC3, 12, 3),
130 DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
131 DIV_TOPC3, 16, 3),
132};
133
49cab82c
TN		 134static struct samsung_gate_clock topc_gate_clks[] __initdata = {
135 GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
136 ENABLE_ACLK_TOPC1, 20, 0, 0),
137};
138
532abc3a
NKC		 139static struct samsung_pll_clock topc_pll_clks[] __initdata = {
140 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
141 BUS0_PLL_CON0, NULL),
142 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
143 CC_PLL_CON0, NULL),
144 PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
145 BUS1_DPLL_CON0, NULL),
146 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
147 MFC_PLL_CON0, NULL),
148 PLL(pll_1460x, 0, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
149 AUD_PLL_CON0, NULL),
150};
151
152static struct samsung_cmu_info topc_cmu_info __initdata = {
153 .pll_clks = topc_pll_clks,
154 .nr_pll_clks = ARRAY_SIZE(topc_pll_clks),
155 .mux_clks = topc_mux_clks,
156 .nr_mux_clks = ARRAY_SIZE(topc_mux_clks),
157 .div_clks = topc_div_clks,
158 .nr_div_clks = ARRAY_SIZE(topc_div_clks),
49cab82c
TN		 159 .gate_clks = topc_gate_clks,
160 .nr_gate_clks = ARRAY_SIZE(topc_gate_clks),
532abc3a
NKC		 161 .fixed_factor_clks = topc_fixed_factor_clks,
162 .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks),
163 .nr_clk_ids = TOPC_NR_CLK,
164 .clk_regs = topc_clk_regs,
165 .nr_clk_regs = ARRAY_SIZE(topc_clk_regs),
166};
167
168static void __init exynos7_clk_topc_init(struct device_node *np)
169{
170 samsung_cmu_register_one(np, &topc_cmu_info);
171}
172
173CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
174 exynos7_clk_topc_init);
175
176/* Register Offset definitions for CMU_TOP0 (0x105D0000) */
177#define MUX_SEL_TOP00 0x0200
178#define MUX_SEL_TOP01 0x0204
179#define MUX_SEL_TOP03 0x020C
ee74b56a
PV		 180#define MUX_SEL_TOP0_PERIC1 0x0234
181#define MUX_SEL_TOP0_PERIC2 0x0238
532abc3a
NKC		 182#define MUX_SEL_TOP0_PERIC3 0x023C
183#define DIV_TOP03 0x060C
ee74b56a
PV		 184#define DIV_TOP0_PERIC1 0x0634
185#define DIV_TOP0_PERIC2 0x0638
532abc3a 186#define DIV_TOP0_PERIC3 0x063C
ee74b56a
PV		 187#define ENABLE_SCLK_TOP0_PERIC1 0x0A34
188#define ENABLE_SCLK_TOP0_PERIC2 0x0A38
532abc3a
NKC		 189#define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
190
191/* List of parent clocks for Muxes in CMU_TOP0 */
192PNAME(mout_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" };
193PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" };
194PNAME(mout_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll" };
195PNAME(mout_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll" };
196
197PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll",
198 "ffac_top0_bus0_pll_div2"};
199PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll",
200 "ffac_top0_bus1_pll_div2"};
201PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll",
202 "ffac_top0_cc_pll_div2"};
203PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll",
204 "ffac_top0_mfc_pll_div2"};
205
206PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll",
207 "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll",
208 "mout_top0_half_mfc_pll"};
209
210static unsigned long top0_clk_regs[] __initdata = {
211 MUX_SEL_TOP00,
212 MUX_SEL_TOP01,
213 MUX_SEL_TOP03,
ee74b56a
PV		 214 MUX_SEL_TOP0_PERIC1,
215 MUX_SEL_TOP0_PERIC2,
532abc3a
NKC		 216 MUX_SEL_TOP0_PERIC3,
217 DIV_TOP03,
ee74b56a
PV		 218 DIV_TOP0_PERIC1,
219 DIV_TOP0_PERIC2,
532abc3a 220 DIV_TOP0_PERIC3,
ee74b56a
PV		 221 ENABLE_SCLK_TOP0_PERIC1,
222 ENABLE_SCLK_TOP0_PERIC2,
532abc3a
NKC		 223 ENABLE_SCLK_TOP0_PERIC3,
224};
225
226static struct samsung_mux_clock top0_mux_clks[] __initdata = {
227 MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1),
228 MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1),
229 MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1),
230 MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1),
231
232 MUX(0, "mout_top0_half_mfc_pll", mout_top0_half_mfc_pll_p,
233 MUX_SEL_TOP01, 4, 1),
234 MUX(0, "mout_top0_half_cc_pll", mout_top0_half_cc_pll_p,
235 MUX_SEL_TOP01, 8, 1),
236 MUX(0, "mout_top0_half_bus1_pll", mout_top0_half_bus1_pll_p,
237 MUX_SEL_TOP01, 12, 1),
238 MUX(0, "mout_top0_half_bus0_pll", mout_top0_half_bus0_pll_p,
239 MUX_SEL_TOP01, 16, 1),
240
241 MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
242 MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
243
ee74b56a
PV		 244 MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
245 MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
246
247 MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
248 MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
532abc3a
NKC		 249 MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
250 MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
251 MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
252 MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
ee74b56a 253 MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
532abc3a
NKC		 254};
255
256static struct samsung_div_clock top0_div_clks[] __initdata = {
257 DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66",
258 DIV_TOP03, 12, 6),
259 DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
260 DIV_TOP03, 20, 6),
261
ee74b56a
PV		 262 DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
263 DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
264
265 DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12),
266 DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12),
267
532abc3a
NKC		 268 DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
269 DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
270 DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
271 DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
ee74b56a 272 DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
532abc3a
NKC		 273};
274
275static struct samsung_gate_clock top0_gate_clks[] __initdata = {
ee74b56a
PV		 276 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1",
277 ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
278 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
279 ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
280
281 GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3",
282 ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
283 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2",
284 ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
532abc3a
NKC		 285 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
286 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
287 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
288 ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0),
289 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
290 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
291 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
292 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
ee74b56a
PV		 293 GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4",
294 ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
532abc3a
NKC		 295};
296
297static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
298 FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0),
299 FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0),
300 FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0),
301 FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0),
302};
303
304static struct samsung_cmu_info top0_cmu_info __initdata = {
305 .mux_clks = top0_mux_clks,
306 .nr_mux_clks = ARRAY_SIZE(top0_mux_clks),
307 .div_clks = top0_div_clks,
308 .nr_div_clks = ARRAY_SIZE(top0_div_clks),
309 .gate_clks = top0_gate_clks,
310 .nr_gate_clks = ARRAY_SIZE(top0_gate_clks),
311 .fixed_factor_clks = top0_fixed_factor_clks,
312 .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks),
313 .nr_clk_ids = TOP0_NR_CLK,
314 .clk_regs = top0_clk_regs,
315 .nr_clk_regs = ARRAY_SIZE(top0_clk_regs),
316};
317
318static void __init exynos7_clk_top0_init(struct device_node *np)
319{
320 samsung_cmu_register_one(np, &top0_cmu_info);
321}
322
323CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
324 exynos7_clk_top0_init);
325
6d0c8c72
NKC		 326/* Register Offset definitions for CMU_TOP1 (0x105E0000) */
327#define MUX_SEL_TOP10 0x0200
328#define MUX_SEL_TOP11 0x0204
329#define MUX_SEL_TOP13 0x020C
330#define MUX_SEL_TOP1_FSYS0 0x0224
331#define MUX_SEL_TOP1_FSYS1 0x0228
332#define DIV_TOP13 0x060C
333#define DIV_TOP1_FSYS0 0x0624
334#define DIV_TOP1_FSYS1 0x0628
335#define ENABLE_ACLK_TOP13 0x080C
336#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
337#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
338
339/* List of parent clocks for Muxes in CMU_TOP1 */
340PNAME(mout_top1_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" };
341PNAME(mout_top1_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll_b" };
342PNAME(mout_top1_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll_b" };
343PNAME(mout_top1_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll_b" };
344
345PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
346 "ffac_top1_bus0_pll_div2"};
347PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
348 "ffac_top1_bus1_pll_div2"};
349PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
350 "ffac_top1_cc_pll_div2"};
351PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
352 "ffac_top1_mfc_pll_div2"};
353
354PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
355 "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
356 "mout_top1_half_mfc_pll"};
357
358static unsigned long top1_clk_regs[] __initdata = {
359 MUX_SEL_TOP10,
360 MUX_SEL_TOP11,
361 MUX_SEL_TOP13,
362 MUX_SEL_TOP1_FSYS0,
363 MUX_SEL_TOP1_FSYS1,
364 DIV_TOP13,
365 DIV_TOP1_FSYS0,
366 DIV_TOP1_FSYS1,
367 ENABLE_ACLK_TOP13,
368 ENABLE_SCLK_TOP1_FSYS0,
369 ENABLE_SCLK_TOP1_FSYS1,
370};
371
372static struct samsung_mux_clock top1_mux_clks[] __initdata = {
373 MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
374 MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
375 MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
376 MUX_SEL_TOP10, 12, 1),
377 MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
378 MUX_SEL_TOP10, 16, 1),
379
380 MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
381 MUX_SEL_TOP11, 4, 1),
382 MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p,
383 MUX_SEL_TOP11, 8, 1),
384 MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p,
385 MUX_SEL_TOP11, 12, 1),
386 MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p,
387 MUX_SEL_TOP11, 16, 1),
388
389 MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
390 MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
391
392 MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
83f191a7
VG		 393 MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
394 MUX_SEL_TOP1_FSYS0, 28, 2),
6d0c8c72
NKC		 395
396 MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
397 MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
398};
399
400static struct samsung_div_clock top1_div_clks[] __initdata = {
401 DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
402 DIV_TOP13, 24, 4),
403 DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
404 DIV_TOP13, 28, 4),
405
406 DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
407 DIV_TOP1_FSYS0, 24, 4),
83f191a7
VG		 408 DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
409 DIV_TOP1_FSYS0, 28, 4),
6d0c8c72
NKC		 410
411 DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
412 DIV_TOP1_FSYS1, 24, 4),
413 DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
414 DIV_TOP1_FSYS1, 28, 4),
415};
416
417static struct samsung_gate_clock top1_gate_clks[] __initdata = {
418 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
419 ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
83f191a7
VG		 420 GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
421 ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
6d0c8c72
NKC		 422
423 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
424 ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
425 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
426 ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),
427};
428
429static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
430 FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0),
431 FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0),
432 FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0),
433 FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0),
434};
435
436static struct samsung_cmu_info top1_cmu_info __initdata = {
437 .mux_clks = top1_mux_clks,
438 .nr_mux_clks = ARRAY_SIZE(top1_mux_clks),
439 .div_clks = top1_div_clks,
440 .nr_div_clks = ARRAY_SIZE(top1_div_clks),
441 .gate_clks = top1_gate_clks,
442 .nr_gate_clks = ARRAY_SIZE(top1_gate_clks),
443 .fixed_factor_clks = top1_fixed_factor_clks,
444 .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks),
445 .nr_clk_ids = TOP1_NR_CLK,
446 .clk_regs = top1_clk_regs,
447 .nr_clk_regs = ARRAY_SIZE(top1_clk_regs),
448};
449
450static void __init exynos7_clk_top1_init(struct device_node *np)
451{
452 samsung_cmu_register_one(np, &top1_cmu_info);
453}
454
455CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
456 exynos7_clk_top1_init);
457
f5e127cd
NKC		 458/* Register Offset definitions for CMU_CCORE (0x105B0000) */
459#define MUX_SEL_CCORE 0x0200
460#define DIV_CCORE 0x0600
461#define ENABLE_ACLK_CCORE0 0x0800
462#define ENABLE_ACLK_CCORE1 0x0804
463#define ENABLE_PCLK_CCORE 0x0900
464
465/*
466 * List of parent clocks for Muxes in CMU_CCORE
467 */
468PNAME(mout_aclk_ccore_133_p) = { "fin_pll", "dout_aclk_ccore_133" };
469
470static unsigned long ccore_clk_regs[] __initdata = {
471 MUX_SEL_CCORE,
472 ENABLE_PCLK_CCORE,
473};
474
475static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
476 MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p,
477 MUX_SEL_CCORE, 1, 1),
478};
479
480static struct samsung_gate_clock ccore_gate_clks[] __initdata = {
481 GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
482 ENABLE_PCLK_CCORE, 8, 0, 0),
483};
484
485static struct samsung_cmu_info ccore_cmu_info __initdata = {
486 .mux_clks = ccore_mux_clks,
487 .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks),
488 .gate_clks = ccore_gate_clks,
489 .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks),
490 .nr_clk_ids = CCORE_NR_CLK,
491 .clk_regs = ccore_clk_regs,
492 .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs),
493};
494
495static void __init exynos7_clk_ccore_init(struct device_node *np)
496{
497 samsung_cmu_register_one(np, &ccore_cmu_info);
498}
499
500CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
501 exynos7_clk_ccore_init);
502
532abc3a
NKC		 503/* Register Offset definitions for CMU_PERIC0 (0x13610000) */
504#define MUX_SEL_PERIC0 0x0200
505#define ENABLE_PCLK_PERIC0 0x0900
506#define ENABLE_SCLK_PERIC0 0x0A00
507
508/* List of parent clocks for Muxes in CMU_PERIC0 */
509PNAME(mout_aclk_peric0_66_p) = { "fin_pll", "dout_aclk_peric0_66" };
510PNAME(mout_sclk_uart0_p) = { "fin_pll", "sclk_uart0" };
511
512static unsigned long peric0_clk_regs[] __initdata = {
513 MUX_SEL_PERIC0,
514 ENABLE_PCLK_PERIC0,
515 ENABLE_SCLK_PERIC0,
516};
517
518static struct samsung_mux_clock peric0_mux_clks[] __initdata = {
519 MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p,
520 MUX_SEL_PERIC0, 0, 1),
521 MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p,
522 MUX_SEL_PERIC0, 16, 1),
523};
524
525static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
57a2b485
NKC		 526 GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
527 ENABLE_PCLK_PERIC0, 8, 0, 0),
528 GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
529 ENABLE_PCLK_PERIC0, 9, 0, 0),
530 GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
531 ENABLE_PCLK_PERIC0, 10, 0, 0),
532 GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
533 ENABLE_PCLK_PERIC0, 11, 0, 0),
534 GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
535 ENABLE_PCLK_PERIC0, 12, 0, 0),
536 GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
537 ENABLE_PCLK_PERIC0, 13, 0, 0),
538 GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
539 ENABLE_PCLK_PERIC0, 14, 0, 0),
532abc3a
NKC		 540 GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
541 ENABLE_PCLK_PERIC0, 16, 0, 0),
932e9822
AK		 542 GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user",
543 ENABLE_PCLK_PERIC0, 20, 0, 0),
2ab2dfe5
NKC		 544 GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
545 ENABLE_PCLK_PERIC0, 21, 0, 0),
532abc3a
NKC		 546
547 GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
548 ENABLE_SCLK_PERIC0, 16, 0, 0),
2ab2dfe5 549 GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
532abc3a
NKC		 550};
551
552static struct samsung_cmu_info peric0_cmu_info __initdata = {
553 .mux_clks = peric0_mux_clks,
554 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
555 .gate_clks = peric0_gate_clks,
556 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
557 .nr_clk_ids = PERIC0_NR_CLK,
558 .clk_regs = peric0_clk_regs,
559 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
560};
561
562static void __init exynos7_clk_peric0_init(struct device_node *np)
563{
564 samsung_cmu_register_one(np, &peric0_cmu_info);
565}
566
567/* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
568#define MUX_SEL_PERIC10 0x0200
569#define MUX_SEL_PERIC11 0x0204
ee74b56a 570#define MUX_SEL_PERIC12 0x0208
532abc3a
NKC		 571#define ENABLE_PCLK_PERIC1 0x0900
572#define ENABLE_SCLK_PERIC10 0x0A00
573
574CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
575 exynos7_clk_peric0_init);
576
577/* List of parent clocks for Muxes in CMU_PERIC1 */
578PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" };
579PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" };
580PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" };
581PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" };
ee74b56a
PV		 582PNAME(mout_sclk_spi0_p) = { "fin_pll", "sclk_spi0" };
583PNAME(mout_sclk_spi1_p) = { "fin_pll", "sclk_spi1" };
584PNAME(mout_sclk_spi2_p) = { "fin_pll", "sclk_spi2" };
585PNAME(mout_sclk_spi3_p) = { "fin_pll", "sclk_spi3" };
586PNAME(mout_sclk_spi4_p) = { "fin_pll", "sclk_spi4" };
532abc3a
NKC		 587
588static unsigned long peric1_clk_regs[] __initdata = {
589 MUX_SEL_PERIC10,
590 MUX_SEL_PERIC11,
ee74b56a 591 MUX_SEL_PERIC12,
532abc3a
NKC		 592 ENABLE_PCLK_PERIC1,
593 ENABLE_SCLK_PERIC10,
594};
595
596static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
597 MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
598 MUX_SEL_PERIC10, 0, 1),
599
ee74b56a
PV		 600 MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p,
601 MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
602 MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p,
603 MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
604 MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p,
605 MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
606 MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p,
607 MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
608 MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p,
609 MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
532abc3a
NKC		 610 MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
611 MUX_SEL_PERIC11, 20, 1),
612 MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
613 MUX_SEL_PERIC11, 24, 1),
614 MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p,
615 MUX_SEL_PERIC11, 28, 1),
616};
617
618static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
57a2b485
NKC		 619 GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
620 ENABLE_PCLK_PERIC1, 4, 0, 0),
621 GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
622 ENABLE_PCLK_PERIC1, 5, 0, 0),
623 GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
624 ENABLE_PCLK_PERIC1, 6, 0, 0),
625 GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
626 ENABLE_PCLK_PERIC1, 7, 0, 0),
627 GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
628 ENABLE_PCLK_PERIC1, 8, 0, 0),
532abc3a
NKC		 629 GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
630 ENABLE_PCLK_PERIC1, 9, 0, 0),
631 GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
632 ENABLE_PCLK_PERIC1, 10, 0, 0),
633 GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
634 ENABLE_PCLK_PERIC1, 11, 0, 0),
ee74b56a
PV		 635 GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user",
636 ENABLE_PCLK_PERIC1, 12, 0, 0),
637 GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user",
638 ENABLE_PCLK_PERIC1, 13, 0, 0),
639 GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user",
640 ENABLE_PCLK_PERIC1, 14, 0, 0),
641 GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user",
642 ENABLE_PCLK_PERIC1, 15, 0, 0),
643 GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user",
644 ENABLE_PCLK_PERIC1, 16, 0, 0),
532abc3a
NKC		 645
646 GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
647 ENABLE_SCLK_PERIC10, 9, 0, 0),
648 GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user",
649 ENABLE_SCLK_PERIC10, 10, 0, 0),
650 GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
651 ENABLE_SCLK_PERIC10, 11, 0, 0),
ee74b56a
PV		 652 GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
653 ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0),
654 GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user",
655 ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0),
656 GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user",
657 ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0),
658 GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user",
659 ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
660 GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user",
661 ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
532abc3a
NKC		 662};
663
664static struct samsung_cmu_info peric1_cmu_info __initdata = {
665 .mux_clks = peric1_mux_clks,
666 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
667 .gate_clks = peric1_gate_clks,
668 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
669 .nr_clk_ids = PERIC1_NR_CLK,
670 .clk_regs = peric1_clk_regs,
671 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
672};
673
674static void __init exynos7_clk_peric1_init(struct device_node *np)
675{
676 samsung_cmu_register_one(np, &peric1_cmu_info);
677}
678
679CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
680 exynos7_clk_peric1_init);
681
682/* Register Offset definitions for CMU_PERIS (0x10040000) */
683#define MUX_SEL_PERIS 0x0200
2ab2dfe5 684#define ENABLE_PCLK_PERIS 0x0900
532abc3a 685#define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910
2ab2dfe5 686#define ENABLE_SCLK_PERIS 0x0A00
532abc3a
NKC		 687#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10
688
689/* List of parent clocks for Muxes in CMU_PERIS */
690PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" };
691
692static unsigned long peris_clk_regs[] __initdata = {
693 MUX_SEL_PERIS,
2ab2dfe5 694 ENABLE_PCLK_PERIS,
532abc3a 695 ENABLE_PCLK_PERIS_SECURE_CHIPID,
2ab2dfe5 696 ENABLE_SCLK_PERIS,
532abc3a
NKC		 697 ENABLE_SCLK_PERIS_SECURE_CHIPID,
698};
699
700static struct samsung_mux_clock peris_mux_clks[] __initdata = {
701 MUX(0, "mout_aclk_peris_66_user",
702 mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1),
703};
704
705static struct samsung_gate_clock peris_gate_clks[] __initdata = {
2ab2dfe5
NKC		 706 GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
707 ENABLE_PCLK_PERIS, 6, 0, 0),
708 GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
709 ENABLE_PCLK_PERIS, 10, 0, 0),
710
532abc3a
NKC		 711 GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
712 ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
713 GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
714 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
2ab2dfe5
NKC		 715
716 GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
532abc3a
NKC		 717};
718
719static struct samsung_cmu_info peris_cmu_info __initdata = {
720 .mux_clks = peris_mux_clks,
721 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
722 .gate_clks = peris_gate_clks,
723 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
724 .nr_clk_ids = PERIS_NR_CLK,
725 .clk_regs = peris_clk_regs,
726 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
727};
728
729static void __init exynos7_clk_peris_init(struct device_node *np)
730{
731 samsung_cmu_register_one(np, &peris_cmu_info);
732}
733
734CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
735 exynos7_clk_peris_init);
6d0c8c72
NKC		 736
737/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
738#define MUX_SEL_FSYS00 0x0200
739#define MUX_SEL_FSYS01 0x0204
83f191a7
VG		 740#define MUX_SEL_FSYS02 0x0208
741#define ENABLE_ACLK_FSYS00 0x0800
6d0c8c72 742#define ENABLE_ACLK_FSYS01 0x0804
83f191a7
VG		 743#define ENABLE_SCLK_FSYS01 0x0A04
744#define ENABLE_SCLK_FSYS02 0x0A08
745#define ENABLE_SCLK_FSYS04 0x0A10
6d0c8c72
NKC		 746
747/*
748 * List of parent clocks for Muxes in CMU_FSYS0
749 */
750PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" };
751PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" };
752
83f191a7
VG		 753PNAME(mout_sclk_usbdrd300_p) = { "fin_pll", "sclk_usbdrd300" };
754PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_p) = { "fin_pll",
755 "phyclk_usbdrd300_udrd30_phyclock" };
756PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_p) = { "fin_pll",
757 "phyclk_usbdrd300_udrd30_pipe_pclk" };
758
759/* fixed rate clocks used in the FSYS0 block */
760struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = {
761 FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL,
762 CLK_IS_ROOT, 60000000),
763 FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL,
764 CLK_IS_ROOT, 125000000),
765};
766
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NKC		 767static unsigned long fsys0_clk_regs[] __initdata = {
768 MUX_SEL_FSYS00,
769 MUX_SEL_FSYS01,
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VG		 770 MUX_SEL_FSYS02,
771 ENABLE_ACLK_FSYS00,
6d0c8c72 772 ENABLE_ACLK_FSYS01,
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VG		 773 ENABLE_SCLK_FSYS01,
774 ENABLE_SCLK_FSYS02,
775 ENABLE_SCLK_FSYS04,
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NKC		 776};
777
778static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
779 MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
780 MUX_SEL_FSYS00, 24, 1),
781
782 MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
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VG		 783 MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_p,
784 MUX_SEL_FSYS01, 28, 1),
785
786 MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
787 mout_phyclk_usbdrd300_udrd30_pipe_pclk_p,
788 MUX_SEL_FSYS02, 24, 1),
789 MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
790 mout_phyclk_usbdrd300_udrd30_phyclk_p,
791 MUX_SEL_FSYS02, 28, 1),
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NKC		 792};
793
794static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
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VG		 795 GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
796 "mout_aclk_fsys0_200_user",
797 ENABLE_ACLK_FSYS00, 19, 0, 0),
9cc2a0c9
PV		 798 GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",
799 ENABLE_ACLK_FSYS00, 3, 0, 0),
800 GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",
801 ENABLE_ACLK_FSYS00, 4, 0, 0),
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VG		 802
803 GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
804 ENABLE_ACLK_FSYS01, 29, 0, 0),
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NKC		 805 GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
806 ENABLE_ACLK_FSYS01, 31, 0, 0),
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VG		 807
808 GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk",
809 "mout_sclk_usbdrd300_user",
810 ENABLE_SCLK_FSYS01, 4, 0, 0),
811 GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll",
812 ENABLE_SCLK_FSYS01, 8, 0, 0),
813
814 GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER,
815 "phyclk_usbdrd300_udrd30_pipe_pclk_user",
816 "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
817 ENABLE_SCLK_FSYS02, 24, 0, 0),
818 GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER,
819 "phyclk_usbdrd300_udrd30_phyclk_user",
820 "mout_phyclk_usbdrd300_udrd30_phyclk_user",
821 ENABLE_SCLK_FSYS02, 28, 0, 0),
822
823 GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy",
824 "fin_pll",
825 ENABLE_SCLK_FSYS04, 28, 0, 0),
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NKC		 826};
827
828static struct samsung_cmu_info fsys0_cmu_info __initdata = {
829 .mux_clks = fsys0_mux_clks,
830 .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
831 .gate_clks = fsys0_gate_clks,
832 .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
833 .nr_clk_ids = TOP1_NR_CLK,
834 .clk_regs = fsys0_clk_regs,
835 .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
836};
837
838static void __init exynos7_clk_fsys0_init(struct device_node *np)
839{
840 samsung_cmu_register_one(np, &fsys0_cmu_info);
841}
842
843CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
844 exynos7_clk_fsys0_init);
845
846/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
847#define MUX_SEL_FSYS10 0x0200
848#define MUX_SEL_FSYS11 0x0204
849#define ENABLE_ACLK_FSYS1 0x0800
850
851/*
852 * List of parent clocks for Muxes in CMU_FSYS1
853 */
854PNAME(mout_aclk_fsys1_200_p) = { "fin_pll", "dout_aclk_fsys1_200" };
855PNAME(mout_sclk_mmc0_p) = { "fin_pll", "sclk_mmc0" };
856PNAME(mout_sclk_mmc1_p) = { "fin_pll", "sclk_mmc1" };
857
858static unsigned long fsys1_clk_regs[] __initdata = {
859 MUX_SEL_FSYS10,
860 MUX_SEL_FSYS11,
861 ENABLE_ACLK_FSYS1,
862};
863
864static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
865 MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
866 MUX_SEL_FSYS10, 28, 1),
867
868 MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1),
869 MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1),
870};
871
872static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
873 GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
874 ENABLE_ACLK_FSYS1, 29, 0, 0),
875 GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
876 ENABLE_ACLK_FSYS1, 30, 0, 0),
877};
878
879static struct samsung_cmu_info fsys1_cmu_info __initdata = {
880 .mux_clks = fsys1_mux_clks,
881 .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
882 .gate_clks = fsys1_gate_clks,
883 .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
884 .nr_clk_ids = TOP1_NR_CLK,
885 .clk_regs = fsys1_clk_regs,
886 .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
887};
888
889static void __init exynos7_clk_fsys1_init(struct device_node *np)
890{
891 samsung_cmu_register_one(np, &fsys1_cmu_info);
892}
893
894CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
895 exynos7_clk_fsys1_init);
49cab82c
TN		 896
897#define MUX_SEL_MSCL 0x0200
898#define DIV_MSCL 0x0600
899#define ENABLE_ACLK_MSCL 0x0800
900#define ENABLE_PCLK_MSCL 0x0900
901
902/* List of parent clocks for Muxes in CMU_MSCL */
903PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" };
904
905static unsigned long mscl_clk_regs[] __initdata = {
906 MUX_SEL_MSCL,
907 DIV_MSCL,
908 ENABLE_ACLK_MSCL,
909 ENABLE_PCLK_MSCL,
910};
911
912static struct samsung_mux_clock mscl_mux_clks[] __initdata = {
913 MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532",
914 mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1),
915};
916static struct samsung_div_clock mscl_div_clks[] __initdata = {
917 DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532",
918 DIV_MSCL, 0, 3),
919};
920static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
921
922 GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532",
923 ENABLE_ACLK_MSCL, 31, 0, 0),
924 GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532",
925 ENABLE_ACLK_MSCL, 30, 0, 0),
926 GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532",
927 ENABLE_ACLK_MSCL, 29, 0, 0),
928 GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532",
929 ENABLE_ACLK_MSCL, 28, 0, 0),
930 GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0",
931 "usermux_aclk_mscl_532",
932 ENABLE_ACLK_MSCL, 27, 0, 0),
933 GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1",
934 "usermux_aclk_mscl_532",
935 ENABLE_ACLK_MSCL, 26, 0, 0),
936 GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532",
937 ENABLE_ACLK_MSCL, 25, 0, 0),
938 GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532",
939 ENABLE_ACLK_MSCL, 24, 0, 0),
940 GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge",
941 "usermux_aclk_mscl_532",
942 ENABLE_ACLK_MSCL, 23, 0, 0),
943 GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532",
944 ENABLE_ACLK_MSCL, 22, 0, 0),
945 GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532",
946 ENABLE_ACLK_MSCL, 21, 0, 0),
947 GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532",
948 ENABLE_ACLK_MSCL, 20, 0, 0),
949 GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532",
950 ENABLE_ACLK_MSCL, 19, 0, 0),
951 GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532",
952 ENABLE_ACLK_MSCL, 18, 0, 0),
953 GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532",
954 ENABLE_ACLK_MSCL, 17, 0, 0),
955 GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532",
956 ENABLE_ACLK_MSCL, 16, 0, 0),
957 GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p",
958 "usermux_aclk_mscl_532",
959 ENABLE_ACLK_MSCL, 15, 0, 0),
960 GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p",
961 "usermux_aclk_mscl_532",
962 ENABLE_ACLK_MSCL, 14, 0, 0),
963
964 GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl",
965 ENABLE_PCLK_MSCL, 31, 0, 0),
966 GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl",
967 ENABLE_PCLK_MSCL, 30, 0, 0),
968 GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl",
969 ENABLE_PCLK_MSCL, 29, 0, 0),
970 GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl",
971 ENABLE_PCLK_MSCL, 28, 0, 0),
972 GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl",
973 ENABLE_PCLK_MSCL, 27, 0, 0),
974 GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl",
975 ENABLE_PCLK_MSCL, 26, 0, 0),
976 GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl",
977 ENABLE_PCLK_MSCL, 25, 0, 0),
978 GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl",
979 ENABLE_PCLK_MSCL, 24, 0, 0),
980 GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl",
981 ENABLE_PCLK_MSCL, 23, 0, 0),
982 GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl",
983 ENABLE_PCLK_MSCL, 22, 0, 0),
984 GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl",
985 ENABLE_PCLK_MSCL, 21, 0, 0),
986 GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl",
987 ENABLE_PCLK_MSCL, 20, 0, 0),
988};
989
990static struct samsung_cmu_info mscl_cmu_info __initdata = {
991 .mux_clks = mscl_mux_clks,
992 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
993 .div_clks = mscl_div_clks,
994 .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
995 .gate_clks = mscl_gate_clks,
996 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
997 .nr_clk_ids = MSCL_NR_CLK,
998 .clk_regs = mscl_clk_regs,
999 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
1000};
1001
1002static void __init exynos7_clk_mscl_init(struct device_node *np)
1003{
1004 samsung_cmu_register_one(np, &mscl_cmu_info);
1005}
1006
1007CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl",
1008 exynos7_clk_mscl_init);
Linux 6.x block layer and io_uring tree(s)