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Linux 4.3-rc1
[linux-block.git] / drivers / clk / samsung / clk-exynos7.c
CommitLineData
532abc3a
NKC		 1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9*/
10
532abc3a
NKC		 11#include <linux/clk-provider.h>
12#include <linux/of.h>
13
14#include "clk.h"
15#include <dt-bindings/clock/exynos7-clk.h>
16
17/* Register Offset definitions for CMU_TOPC (0x10570000) */
18#define CC_PLL_LOCK 0x0000
19#define BUS0_PLL_LOCK 0x0004
20#define BUS1_DPLL_LOCK 0x0008
21#define MFC_PLL_LOCK 0x000C
22#define AUD_PLL_LOCK 0x0010
23#define CC_PLL_CON0 0x0100
24#define BUS0_PLL_CON0 0x0110
25#define BUS1_DPLL_CON0 0x0120
26#define MFC_PLL_CON0 0x0130
27#define AUD_PLL_CON0 0x0140
28#define MUX_SEL_TOPC0 0x0200
29#define MUX_SEL_TOPC1 0x0204
f5e127cd 30#define MUX_SEL_TOPC2 0x0208
532abc3a 31#define MUX_SEL_TOPC3 0x020C
f5e127cd 32#define DIV_TOPC0 0x0600
532abc3a
NKC		 33#define DIV_TOPC1 0x0604
34#define DIV_TOPC3 0x060C
49cab82c 35#define ENABLE_ACLK_TOPC1 0x0804
532abc3a
NKC		 36
37static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
38 FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0),
39 FFACTOR(0, "ffac_topc_bus0_pll_div4",
40 "ffac_topc_bus0_pll_div2", 1, 2, 0),
41 FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0),
42 FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0),
43 FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0),
44};
45
46/* List of parent clocks for Muxes in CMU_TOPC */
9f930a39 47PNAME(mout_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" };
532abc3a
NKC		 48PNAME(mout_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
49PNAME(mout_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
50PNAME(mout_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
51PNAME(mout_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" };
52
53PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc",
54 "mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc",
55 "mout_sclk_mfc_pll_cmuc" };
56
57PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl",
58 "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
59PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl",
60 "ffac_topc_bus1_pll_div2"};
61PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl",
62 "ffac_topc_cc_pll_div2"};
63PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl",
64 "ffac_topc_mfc_pll_div2"};
65
66
67PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl",
68 "ffac_topc_bus0_pll_div2"};
69
70static unsigned long topc_clk_regs[] __initdata = {
71 CC_PLL_LOCK,
72 BUS0_PLL_LOCK,
73 BUS1_DPLL_LOCK,
74 MFC_PLL_LOCK,
75 AUD_PLL_LOCK,
76 CC_PLL_CON0,
77 BUS0_PLL_CON0,
78 BUS1_DPLL_CON0,
79 MFC_PLL_CON0,
80 AUD_PLL_CON0,
81 MUX_SEL_TOPC0,
82 MUX_SEL_TOPC1,
f5e127cd 83 MUX_SEL_TOPC2,
532abc3a 84 MUX_SEL_TOPC3,
f5e127cd 85 DIV_TOPC0,
532abc3a
NKC		 86 DIV_TOPC1,
87 DIV_TOPC3,
88};
89
90static struct samsung_mux_clock topc_mux_clks[] __initdata = {
91 MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1),
92 MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1),
93 MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1),
94 MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1),
95
96 MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p,
97 MUX_SEL_TOPC0, 16, 2),
98 MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p,
99 MUX_SEL_TOPC0, 20, 1),
100 MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p,
101 MUX_SEL_TOPC0, 24, 1),
102 MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p,
103 MUX_SEL_TOPC0, 28, 1),
104
105 MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
106 MUX_SEL_TOPC1, 16, 1),
9f930a39 107 MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
532abc3a 108
f5e127cd
NKC		 109 MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
110
49cab82c 111 MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2),
532abc3a
NKC		 112 MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
113};
114
115static struct samsung_div_clock topc_div_clks[] __initdata = {
f5e127cd
NKC		 116 DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
117 DIV_TOPC0, 4, 4),
118
49cab82c
TN		 119 DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532",
120 DIV_TOPC1, 20, 4),
532abc3a
NKC		 121 DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
122 DIV_TOPC1, 24, 4),
123
124 DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out",
125 DIV_TOPC3, 0, 3),
126 DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl",
127 DIV_TOPC3, 8, 3),
128 DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl",
129 DIV_TOPC3, 12, 3),
130 DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
131 DIV_TOPC3, 16, 3),
9f930a39
PV		 132 DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_aud_pll_ctrl",
133 DIV_TOPC3, 28, 3),
134};
135
136static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
137 PLL_36XX_RATE(491520000, 20, 1, 0, 31457),
138 {},
532abc3a
NKC		 139};
140
49cab82c
TN		 141static struct samsung_gate_clock topc_gate_clks[] __initdata = {
142 GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
143 ENABLE_ACLK_TOPC1, 20, 0, 0),
144};
145
532abc3a
NKC		 146static struct samsung_pll_clock topc_pll_clks[] __initdata = {
147 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
148 BUS0_PLL_CON0, NULL),
149 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
150 CC_PLL_CON0, NULL),
151 PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
152 BUS1_DPLL_CON0, NULL),
153 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
154 MFC_PLL_CON0, NULL),
9f930a39
PV		 155 PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
156 AUD_PLL_CON0, pll1460x_24mhz_tbl),
532abc3a
NKC		 157};
158
159static struct samsung_cmu_info topc_cmu_info __initdata = {
160 .pll_clks = topc_pll_clks,
161 .nr_pll_clks = ARRAY_SIZE(topc_pll_clks),
162 .mux_clks = topc_mux_clks,
163 .nr_mux_clks = ARRAY_SIZE(topc_mux_clks),
164 .div_clks = topc_div_clks,
165 .nr_div_clks = ARRAY_SIZE(topc_div_clks),
49cab82c
TN		 166 .gate_clks = topc_gate_clks,
167 .nr_gate_clks = ARRAY_SIZE(topc_gate_clks),
532abc3a
NKC		 168 .fixed_factor_clks = topc_fixed_factor_clks,
169 .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks),
170 .nr_clk_ids = TOPC_NR_CLK,
171 .clk_regs = topc_clk_regs,
172 .nr_clk_regs = ARRAY_SIZE(topc_clk_regs),
173};
174
175static void __init exynos7_clk_topc_init(struct device_node *np)
176{
177 samsung_cmu_register_one(np, &topc_cmu_info);
178}
179
180CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
181 exynos7_clk_topc_init);
182
183/* Register Offset definitions for CMU_TOP0 (0x105D0000) */
184#define MUX_SEL_TOP00 0x0200
185#define MUX_SEL_TOP01 0x0204
186#define MUX_SEL_TOP03 0x020C
9f930a39 187#define MUX_SEL_TOP0_PERIC0 0x0230
ee74b56a
PV		 188#define MUX_SEL_TOP0_PERIC1 0x0234
189#define MUX_SEL_TOP0_PERIC2 0x0238
532abc3a
NKC		 190#define MUX_SEL_TOP0_PERIC3 0x023C
191#define DIV_TOP03 0x060C
9f930a39 192#define DIV_TOP0_PERIC0 0x0630
ee74b56a
PV		 193#define DIV_TOP0_PERIC1 0x0634
194#define DIV_TOP0_PERIC2 0x0638
532abc3a 195#define DIV_TOP0_PERIC3 0x063C
9f930a39 196#define ENABLE_SCLK_TOP0_PERIC0 0x0A30
ee74b56a
PV		 197#define ENABLE_SCLK_TOP0_PERIC1 0x0A34
198#define ENABLE_SCLK_TOP0_PERIC2 0x0A38
532abc3a
NKC		 199#define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
200
201/* List of parent clocks for Muxes in CMU_TOP0 */
202PNAME(mout_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" };
203PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" };
204PNAME(mout_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll" };
205PNAME(mout_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll" };
9f930a39 206PNAME(mout_aud_pll_p) = { "fin_pll", "dout_sclk_aud_pll" };
532abc3a
NKC		 207
208PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll",
209 "ffac_top0_bus0_pll_div2"};
210PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll",
211 "ffac_top0_bus1_pll_div2"};
212PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll",
213 "ffac_top0_cc_pll_div2"};
214PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll",
215 "ffac_top0_mfc_pll_div2"};
216
217PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll",
218 "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll",
219 "mout_top0_half_mfc_pll"};
9f930a39
PV		 220PNAME(mout_top0_group3) = {"ioclk_audiocdclk0",
221 "ioclk_audiocdclk1", "ioclk_spdif_extclk",
222 "mout_top0_aud_pll", "mout_top0_half_bus0_pll",
223 "mout_top0_half_bus1_pll"};
224PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll",
225 "mout_top0_half_bus0_pll", "mout_top0_half_bus1_pll"};
532abc3a
NKC		 226
227static unsigned long top0_clk_regs[] __initdata = {
228 MUX_SEL_TOP00,
229 MUX_SEL_TOP01,
230 MUX_SEL_TOP03,
9f930a39 231 MUX_SEL_TOP0_PERIC0,
ee74b56a
PV		 232 MUX_SEL_TOP0_PERIC1,
233 MUX_SEL_TOP0_PERIC2,
532abc3a
NKC		 234 MUX_SEL_TOP0_PERIC3,
235 DIV_TOP03,
9f930a39 236 DIV_TOP0_PERIC0,
ee74b56a
PV		 237 DIV_TOP0_PERIC1,
238 DIV_TOP0_PERIC2,
532abc3a 239 DIV_TOP0_PERIC3,
9f930a39 240 ENABLE_SCLK_TOP0_PERIC0,
ee74b56a
PV		 241 ENABLE_SCLK_TOP0_PERIC1,
242 ENABLE_SCLK_TOP0_PERIC2,
532abc3a
NKC		 243 ENABLE_SCLK_TOP0_PERIC3,
244};
245
246static struct samsung_mux_clock top0_mux_clks[] __initdata = {
9f930a39 247 MUX(0, "mout_top0_aud_pll", mout_aud_pll_p, MUX_SEL_TOP00, 0, 1),
532abc3a
NKC		 248 MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1),
249 MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1),
250 MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1),
251 MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1),
252
253 MUX(0, "mout_top0_half_mfc_pll", mout_top0_half_mfc_pll_p,
254 MUX_SEL_TOP01, 4, 1),
255 MUX(0, "mout_top0_half_cc_pll", mout_top0_half_cc_pll_p,
256 MUX_SEL_TOP01, 8, 1),
257 MUX(0, "mout_top0_half_bus1_pll", mout_top0_half_bus1_pll_p,
258 MUX_SEL_TOP01, 12, 1),
259 MUX(0, "mout_top0_half_bus0_pll", mout_top0_half_bus0_pll_p,
260 MUX_SEL_TOP01, 16, 1),
261
262 MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
263 MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
264
9f930a39
PV		 265 MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3),
266 MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2),
267 MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2),
268
ee74b56a
PV		 269 MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
270 MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
271
272 MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
273 MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
532abc3a
NKC		 274 MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
275 MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
276 MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
277 MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
ee74b56a 278 MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
532abc3a
NKC		 279};
280
281static struct samsung_div_clock top0_div_clks[] __initdata = {
282 DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66",
283 DIV_TOP03, 12, 6),
284 DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
285 DIV_TOP03, 20, 6),
286
9f930a39
PV		 287 DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4),
288 DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12),
289 DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10),
290
ee74b56a
PV		 291 DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
292 DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
293
294 DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12),
295 DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12),
296
532abc3a
NKC		 297 DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
298 DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
299 DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
300 DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
ee74b56a 301 DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
532abc3a
NKC		 302};
303
304static struct samsung_gate_clock top0_gate_clks[] __initdata = {
9f930a39
PV		 305 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
306 ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
307 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1",
308 ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
309 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1",
310 ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0),
311
ee74b56a
PV		 312 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1",
313 ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
314 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
315 ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
316
317 GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3",
318 ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
319 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2",
320 ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
532abc3a
NKC		 321 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
322 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
323 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
324 ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0),
325 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
326 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
327 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
328 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
ee74b56a
PV		 329 GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4",
330 ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
532abc3a
NKC		 331};
332
333static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
334 FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0),
335 FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0),
336 FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0),
337 FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0),
338};
339
340static struct samsung_cmu_info top0_cmu_info __initdata = {
341 .mux_clks = top0_mux_clks,
342 .nr_mux_clks = ARRAY_SIZE(top0_mux_clks),
343 .div_clks = top0_div_clks,
344 .nr_div_clks = ARRAY_SIZE(top0_div_clks),
345 .gate_clks = top0_gate_clks,
346 .nr_gate_clks = ARRAY_SIZE(top0_gate_clks),
347 .fixed_factor_clks = top0_fixed_factor_clks,
348 .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks),
349 .nr_clk_ids = TOP0_NR_CLK,
350 .clk_regs = top0_clk_regs,
351 .nr_clk_regs = ARRAY_SIZE(top0_clk_regs),
352};
353
354static void __init exynos7_clk_top0_init(struct device_node *np)
355{
356 samsung_cmu_register_one(np, &top0_cmu_info);
357}
358
359CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
360 exynos7_clk_top0_init);
361
6d0c8c72
NKC		 362/* Register Offset definitions for CMU_TOP1 (0x105E0000) */
363#define MUX_SEL_TOP10 0x0200
364#define MUX_SEL_TOP11 0x0204
365#define MUX_SEL_TOP13 0x020C
366#define MUX_SEL_TOP1_FSYS0 0x0224
367#define MUX_SEL_TOP1_FSYS1 0x0228
368#define DIV_TOP13 0x060C
369#define DIV_TOP1_FSYS0 0x0624
370#define DIV_TOP1_FSYS1 0x0628
371#define ENABLE_ACLK_TOP13 0x080C
372#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
373#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
374
375/* List of parent clocks for Muxes in CMU_TOP1 */
376PNAME(mout_top1_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" };
377PNAME(mout_top1_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll_b" };
378PNAME(mout_top1_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll_b" };
379PNAME(mout_top1_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll_b" };
380
381PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
382 "ffac_top1_bus0_pll_div2"};
383PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
384 "ffac_top1_bus1_pll_div2"};
385PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
386 "ffac_top1_cc_pll_div2"};
387PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
388 "ffac_top1_mfc_pll_div2"};
389
390PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
391 "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
392 "mout_top1_half_mfc_pll"};
393
394static unsigned long top1_clk_regs[] __initdata = {
395 MUX_SEL_TOP10,
396 MUX_SEL_TOP11,
397 MUX_SEL_TOP13,
398 MUX_SEL_TOP1_FSYS0,
399 MUX_SEL_TOP1_FSYS1,
400 DIV_TOP13,
401 DIV_TOP1_FSYS0,
402 DIV_TOP1_FSYS1,
403 ENABLE_ACLK_TOP13,
404 ENABLE_SCLK_TOP1_FSYS0,
405 ENABLE_SCLK_TOP1_FSYS1,
406};
407
408static struct samsung_mux_clock top1_mux_clks[] __initdata = {
409 MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
410 MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
411 MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
412 MUX_SEL_TOP10, 12, 1),
413 MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
414 MUX_SEL_TOP10, 16, 1),
415
416 MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
417 MUX_SEL_TOP11, 4, 1),
418 MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p,
419 MUX_SEL_TOP11, 8, 1),
420 MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p,
421 MUX_SEL_TOP11, 12, 1),
422 MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p,
423 MUX_SEL_TOP11, 16, 1),
424
425 MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
426 MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
427
428 MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
83f191a7
VG		 429 MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
430 MUX_SEL_TOP1_FSYS0, 28, 2),
6d0c8c72
NKC		 431
432 MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
433 MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
434};
435
436static struct samsung_div_clock top1_div_clks[] __initdata = {
437 DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
438 DIV_TOP13, 24, 4),
439 DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
440 DIV_TOP13, 28, 4),
441
442 DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
443 DIV_TOP1_FSYS0, 24, 4),
83f191a7
VG		 444 DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
445 DIV_TOP1_FSYS0, 28, 4),
6d0c8c72
NKC		 446
447 DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
448 DIV_TOP1_FSYS1, 24, 4),
449 DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
450 DIV_TOP1_FSYS1, 28, 4),
451};
452
453static struct samsung_gate_clock top1_gate_clks[] __initdata = {
454 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
455 ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
83f191a7
VG		 456 GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
457 ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
6d0c8c72
NKC		 458
459 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
460 ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
461 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
462 ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),
463};
464
465static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
466 FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0),
467 FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0),
468 FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0),
469 FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0),
470};
471
472static struct samsung_cmu_info top1_cmu_info __initdata = {
473 .mux_clks = top1_mux_clks,
474 .nr_mux_clks = ARRAY_SIZE(top1_mux_clks),
475 .div_clks = top1_div_clks,
476 .nr_div_clks = ARRAY_SIZE(top1_div_clks),
477 .gate_clks = top1_gate_clks,
478 .nr_gate_clks = ARRAY_SIZE(top1_gate_clks),
479 .fixed_factor_clks = top1_fixed_factor_clks,
480 .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks),
481 .nr_clk_ids = TOP1_NR_CLK,
482 .clk_regs = top1_clk_regs,
483 .nr_clk_regs = ARRAY_SIZE(top1_clk_regs),
484};
485
486static void __init exynos7_clk_top1_init(struct device_node *np)
487{
488 samsung_cmu_register_one(np, &top1_cmu_info);
489}
490
491CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
492 exynos7_clk_top1_init);
493
f5e127cd
NKC		 494/* Register Offset definitions for CMU_CCORE (0x105B0000) */
495#define MUX_SEL_CCORE 0x0200
496#define DIV_CCORE 0x0600
497#define ENABLE_ACLK_CCORE0 0x0800
498#define ENABLE_ACLK_CCORE1 0x0804
499#define ENABLE_PCLK_CCORE 0x0900
500
501/*
502 * List of parent clocks for Muxes in CMU_CCORE
503 */
504PNAME(mout_aclk_ccore_133_p) = { "fin_pll", "dout_aclk_ccore_133" };
505
506static unsigned long ccore_clk_regs[] __initdata = {
507 MUX_SEL_CCORE,
508 ENABLE_PCLK_CCORE,
509};
510
511static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
512 MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p,
513 MUX_SEL_CCORE, 1, 1),
514};
515
516static struct samsung_gate_clock ccore_gate_clks[] __initdata = {
517 GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
518 ENABLE_PCLK_CCORE, 8, 0, 0),
519};
520
521static struct samsung_cmu_info ccore_cmu_info __initdata = {
522 .mux_clks = ccore_mux_clks,
523 .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks),
524 .gate_clks = ccore_gate_clks,
525 .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks),
526 .nr_clk_ids = CCORE_NR_CLK,
527 .clk_regs = ccore_clk_regs,
528 .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs),
529};
530
531static void __init exynos7_clk_ccore_init(struct device_node *np)
532{
533 samsung_cmu_register_one(np, &ccore_cmu_info);
534}
535
536CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
537 exynos7_clk_ccore_init);
538
532abc3a
NKC		 539/* Register Offset definitions for CMU_PERIC0 (0x13610000) */
540#define MUX_SEL_PERIC0 0x0200
541#define ENABLE_PCLK_PERIC0 0x0900
542#define ENABLE_SCLK_PERIC0 0x0A00
543
544/* List of parent clocks for Muxes in CMU_PERIC0 */
545PNAME(mout_aclk_peric0_66_p) = { "fin_pll", "dout_aclk_peric0_66" };
546PNAME(mout_sclk_uart0_p) = { "fin_pll", "sclk_uart0" };
547
548static unsigned long peric0_clk_regs[] __initdata = {
549 MUX_SEL_PERIC0,
550 ENABLE_PCLK_PERIC0,
551 ENABLE_SCLK_PERIC0,
552};
553
554static struct samsung_mux_clock peric0_mux_clks[] __initdata = {
555 MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p,
556 MUX_SEL_PERIC0, 0, 1),
557 MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p,
558 MUX_SEL_PERIC0, 16, 1),
559};
560
561static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
57a2b485
NKC		 562 GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
563 ENABLE_PCLK_PERIC0, 8, 0, 0),
564 GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
565 ENABLE_PCLK_PERIC0, 9, 0, 0),
566 GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
567 ENABLE_PCLK_PERIC0, 10, 0, 0),
568 GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
569 ENABLE_PCLK_PERIC0, 11, 0, 0),
570 GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
571 ENABLE_PCLK_PERIC0, 12, 0, 0),
572 GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
573 ENABLE_PCLK_PERIC0, 13, 0, 0),
574 GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
575 ENABLE_PCLK_PERIC0, 14, 0, 0),
532abc3a
NKC		 576 GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
577 ENABLE_PCLK_PERIC0, 16, 0, 0),
932e9822
AK		 578 GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user",
579 ENABLE_PCLK_PERIC0, 20, 0, 0),
2ab2dfe5
NKC		 580 GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
581 ENABLE_PCLK_PERIC0, 21, 0, 0),
532abc3a
NKC		 582
583 GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
584 ENABLE_SCLK_PERIC0, 16, 0, 0),
2ab2dfe5 585 GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
532abc3a
NKC		 586};
587
588static struct samsung_cmu_info peric0_cmu_info __initdata = {
589 .mux_clks = peric0_mux_clks,
590 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
591 .gate_clks = peric0_gate_clks,
592 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
593 .nr_clk_ids = PERIC0_NR_CLK,
594 .clk_regs = peric0_clk_regs,
595 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
596};
597
598static void __init exynos7_clk_peric0_init(struct device_node *np)
599{
600 samsung_cmu_register_one(np, &peric0_cmu_info);
601}
602
603/* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
604#define MUX_SEL_PERIC10 0x0200
605#define MUX_SEL_PERIC11 0x0204
ee74b56a 606#define MUX_SEL_PERIC12 0x0208
532abc3a
NKC		 607#define ENABLE_PCLK_PERIC1 0x0900
608#define ENABLE_SCLK_PERIC10 0x0A00
609
610CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
611 exynos7_clk_peric0_init);
612
613/* List of parent clocks for Muxes in CMU_PERIC1 */
614PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" };
615PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" };
616PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" };
617PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" };
ee74b56a
PV		 618PNAME(mout_sclk_spi0_p) = { "fin_pll", "sclk_spi0" };
619PNAME(mout_sclk_spi1_p) = { "fin_pll", "sclk_spi1" };
620PNAME(mout_sclk_spi2_p) = { "fin_pll", "sclk_spi2" };
621PNAME(mout_sclk_spi3_p) = { "fin_pll", "sclk_spi3" };
622PNAME(mout_sclk_spi4_p) = { "fin_pll", "sclk_spi4" };
532abc3a
NKC		 623
624static unsigned long peric1_clk_regs[] __initdata = {
625 MUX_SEL_PERIC10,
626 MUX_SEL_PERIC11,
ee74b56a 627 MUX_SEL_PERIC12,
532abc3a
NKC		 628 ENABLE_PCLK_PERIC1,
629 ENABLE_SCLK_PERIC10,
630};
631
632static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
633 MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
634 MUX_SEL_PERIC10, 0, 1),
635
ee74b56a
PV		 636 MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p,
637 MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
638 MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p,
639 MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
640 MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p,
641 MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
642 MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p,
643 MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
644 MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p,
645 MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
532abc3a
NKC		 646 MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
647 MUX_SEL_PERIC11, 20, 1),
648 MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
649 MUX_SEL_PERIC11, 24, 1),
650 MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p,
651 MUX_SEL_PERIC11, 28, 1),
652};
653
654static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
57a2b485
NKC		 655 GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
656 ENABLE_PCLK_PERIC1, 4, 0, 0),
657 GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
658 ENABLE_PCLK_PERIC1, 5, 0, 0),
659 GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
660 ENABLE_PCLK_PERIC1, 6, 0, 0),
661 GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
662 ENABLE_PCLK_PERIC1, 7, 0, 0),
663 GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
664 ENABLE_PCLK_PERIC1, 8, 0, 0),
532abc3a
NKC		 665 GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
666 ENABLE_PCLK_PERIC1, 9, 0, 0),
667 GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
668 ENABLE_PCLK_PERIC1, 10, 0, 0),
669 GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
670 ENABLE_PCLK_PERIC1, 11, 0, 0),
ee74b56a
PV		 671 GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user",
672 ENABLE_PCLK_PERIC1, 12, 0, 0),
673 GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user",
674 ENABLE_PCLK_PERIC1, 13, 0, 0),
675 GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user",
676 ENABLE_PCLK_PERIC1, 14, 0, 0),
677 GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user",
678 ENABLE_PCLK_PERIC1, 15, 0, 0),
679 GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user",
680 ENABLE_PCLK_PERIC1, 16, 0, 0),
9f930a39
PV		 681 GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user",
682 ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0),
683 GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user",
684 ENABLE_PCLK_PERIC1, 18, 0, 0),
685 GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user",
686 ENABLE_PCLK_PERIC1, 19, 0, 0),
532abc3a
NKC		 687
688 GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
689 ENABLE_SCLK_PERIC10, 9, 0, 0),
690 GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user",
691 ENABLE_SCLK_PERIC10, 10, 0, 0),
692 GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
693 ENABLE_SCLK_PERIC10, 11, 0, 0),
ee74b56a
PV		 694 GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
695 ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0),
696 GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user",
697 ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0),
698 GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user",
699 ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0),
700 GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user",
701 ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
702 GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user",
703 ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
9f930a39
PV		 704 GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1",
705 ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0),
706 GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1",
707 ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0),
708 GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif",
709 ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0),
532abc3a
NKC		 710};
711
712static struct samsung_cmu_info peric1_cmu_info __initdata = {
713 .mux_clks = peric1_mux_clks,
714 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
715 .gate_clks = peric1_gate_clks,
716 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
717 .nr_clk_ids = PERIC1_NR_CLK,
718 .clk_regs = peric1_clk_regs,
719 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
720};
721
722static void __init exynos7_clk_peric1_init(struct device_node *np)
723{
724 samsung_cmu_register_one(np, &peric1_cmu_info);
725}
726
727CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
728 exynos7_clk_peric1_init);
729
730/* Register Offset definitions for CMU_PERIS (0x10040000) */
731#define MUX_SEL_PERIS 0x0200
2ab2dfe5 732#define ENABLE_PCLK_PERIS 0x0900
532abc3a 733#define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910
2ab2dfe5 734#define ENABLE_SCLK_PERIS 0x0A00
532abc3a
NKC		 735#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10
736
737/* List of parent clocks for Muxes in CMU_PERIS */
738PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" };
739
740static unsigned long peris_clk_regs[] __initdata = {
741 MUX_SEL_PERIS,
2ab2dfe5 742 ENABLE_PCLK_PERIS,
532abc3a 743 ENABLE_PCLK_PERIS_SECURE_CHIPID,
2ab2dfe5 744 ENABLE_SCLK_PERIS,
532abc3a
NKC		 745 ENABLE_SCLK_PERIS_SECURE_CHIPID,
746};
747
748static struct samsung_mux_clock peris_mux_clks[] __initdata = {
749 MUX(0, "mout_aclk_peris_66_user",
750 mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1),
751};
752
753static struct samsung_gate_clock peris_gate_clks[] __initdata = {
2ab2dfe5
NKC		 754 GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
755 ENABLE_PCLK_PERIS, 6, 0, 0),
756 GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
757 ENABLE_PCLK_PERIS, 10, 0, 0),
758
532abc3a
NKC		 759 GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
760 ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
761 GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
762 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
2ab2dfe5
NKC		 763
764 GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
532abc3a
NKC		 765};
766
767static struct samsung_cmu_info peris_cmu_info __initdata = {
768 .mux_clks = peris_mux_clks,
769 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
770 .gate_clks = peris_gate_clks,
771 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
772 .nr_clk_ids = PERIS_NR_CLK,
773 .clk_regs = peris_clk_regs,
774 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
775};
776
777static void __init exynos7_clk_peris_init(struct device_node *np)
778{
779 samsung_cmu_register_one(np, &peris_cmu_info);
780}
781
782CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
783 exynos7_clk_peris_init);
6d0c8c72
NKC		 784
785/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
786#define MUX_SEL_FSYS00 0x0200
787#define MUX_SEL_FSYS01 0x0204
83f191a7
VG		 788#define MUX_SEL_FSYS02 0x0208
789#define ENABLE_ACLK_FSYS00 0x0800
6d0c8c72 790#define ENABLE_ACLK_FSYS01 0x0804
83f191a7
VG		 791#define ENABLE_SCLK_FSYS01 0x0A04
792#define ENABLE_SCLK_FSYS02 0x0A08
793#define ENABLE_SCLK_FSYS04 0x0A10
6d0c8c72
NKC		 794
795/*
796 * List of parent clocks for Muxes in CMU_FSYS0
797 */
798PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" };
799PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" };
800
83f191a7
VG		 801PNAME(mout_sclk_usbdrd300_p) = { "fin_pll", "sclk_usbdrd300" };
802PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_p) = { "fin_pll",
803 "phyclk_usbdrd300_udrd30_phyclock" };
804PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_p) = { "fin_pll",
805 "phyclk_usbdrd300_udrd30_pipe_pclk" };
806
807/* fixed rate clocks used in the FSYS0 block */
808struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = {
809 FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL,
810 CLK_IS_ROOT, 60000000),
811 FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL,
812 CLK_IS_ROOT, 125000000),
813};
814
6d0c8c72
NKC		 815static unsigned long fsys0_clk_regs[] __initdata = {
816 MUX_SEL_FSYS00,
817 MUX_SEL_FSYS01,
83f191a7
VG		 818 MUX_SEL_FSYS02,
819 ENABLE_ACLK_FSYS00,
6d0c8c72 820 ENABLE_ACLK_FSYS01,
83f191a7
VG		 821 ENABLE_SCLK_FSYS01,
822 ENABLE_SCLK_FSYS02,
823 ENABLE_SCLK_FSYS04,
6d0c8c72
NKC		 824};
825
826static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
827 MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
828 MUX_SEL_FSYS00, 24, 1),
829
830 MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
83f191a7
VG		 831 MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_p,
832 MUX_SEL_FSYS01, 28, 1),
833
834 MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
835 mout_phyclk_usbdrd300_udrd30_pipe_pclk_p,
836 MUX_SEL_FSYS02, 24, 1),
837 MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
838 mout_phyclk_usbdrd300_udrd30_phyclk_p,
839 MUX_SEL_FSYS02, 28, 1),
6d0c8c72
NKC		 840};
841
842static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
83f191a7
VG		 843 GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
844 "mout_aclk_fsys0_200_user",
845 ENABLE_ACLK_FSYS00, 19, 0, 0),
9cc2a0c9
PV		 846 GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",
847 ENABLE_ACLK_FSYS00, 3, 0, 0),
848 GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",
849 ENABLE_ACLK_FSYS00, 4, 0, 0),
83f191a7
VG		 850
851 GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
852 ENABLE_ACLK_FSYS01, 29, 0, 0),
6d0c8c72
NKC		 853 GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
854 ENABLE_ACLK_FSYS01, 31, 0, 0),
83f191a7
VG		 855
856 GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk",
857 "mout_sclk_usbdrd300_user",
858 ENABLE_SCLK_FSYS01, 4, 0, 0),
859 GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll",
860 ENABLE_SCLK_FSYS01, 8, 0, 0),
861
862 GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER,
863 "phyclk_usbdrd300_udrd30_pipe_pclk_user",
864 "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
865 ENABLE_SCLK_FSYS02, 24, 0, 0),
866 GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER,
867 "phyclk_usbdrd300_udrd30_phyclk_user",
868 "mout_phyclk_usbdrd300_udrd30_phyclk_user",
869 ENABLE_SCLK_FSYS02, 28, 0, 0),
870
871 GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy",
872 "fin_pll",
873 ENABLE_SCLK_FSYS04, 28, 0, 0),
6d0c8c72
NKC		 874};
875
876static struct samsung_cmu_info fsys0_cmu_info __initdata = {
877 .mux_clks = fsys0_mux_clks,
878 .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
879 .gate_clks = fsys0_gate_clks,
880 .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
881 .nr_clk_ids = TOP1_NR_CLK,
882 .clk_regs = fsys0_clk_regs,
883 .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
884};
885
886static void __init exynos7_clk_fsys0_init(struct device_node *np)
887{
888 samsung_cmu_register_one(np, &fsys0_cmu_info);
889}
890
891CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
892 exynos7_clk_fsys0_init);
893
894/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
895#define MUX_SEL_FSYS10 0x0200
896#define MUX_SEL_FSYS11 0x0204
897#define ENABLE_ACLK_FSYS1 0x0800
898
899/*
900 * List of parent clocks for Muxes in CMU_FSYS1
901 */
902PNAME(mout_aclk_fsys1_200_p) = { "fin_pll", "dout_aclk_fsys1_200" };
903PNAME(mout_sclk_mmc0_p) = { "fin_pll", "sclk_mmc0" };
904PNAME(mout_sclk_mmc1_p) = { "fin_pll", "sclk_mmc1" };
905
906static unsigned long fsys1_clk_regs[] __initdata = {
907 MUX_SEL_FSYS10,
908 MUX_SEL_FSYS11,
909 ENABLE_ACLK_FSYS1,
910};
911
912static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
913 MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
914 MUX_SEL_FSYS10, 28, 1),
915
916 MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1),
917 MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1),
918};
919
920static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
921 GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
922 ENABLE_ACLK_FSYS1, 29, 0, 0),
923 GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
924 ENABLE_ACLK_FSYS1, 30, 0, 0),
925};
926
927static struct samsung_cmu_info fsys1_cmu_info __initdata = {
928 .mux_clks = fsys1_mux_clks,
929 .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
930 .gate_clks = fsys1_gate_clks,
931 .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
932 .nr_clk_ids = TOP1_NR_CLK,
933 .clk_regs = fsys1_clk_regs,
934 .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
935};
936
937static void __init exynos7_clk_fsys1_init(struct device_node *np)
938{
939 samsung_cmu_register_one(np, &fsys1_cmu_info);
940}
941
942CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
943 exynos7_clk_fsys1_init);
49cab82c
TN		 944
945#define MUX_SEL_MSCL 0x0200
946#define DIV_MSCL 0x0600
947#define ENABLE_ACLK_MSCL 0x0800
948#define ENABLE_PCLK_MSCL 0x0900
949
950/* List of parent clocks for Muxes in CMU_MSCL */
951PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" };
952
953static unsigned long mscl_clk_regs[] __initdata = {
954 MUX_SEL_MSCL,
955 DIV_MSCL,
956 ENABLE_ACLK_MSCL,
957 ENABLE_PCLK_MSCL,
958};
959
960static struct samsung_mux_clock mscl_mux_clks[] __initdata = {
961 MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532",
962 mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1),
963};
964static struct samsung_div_clock mscl_div_clks[] __initdata = {
965 DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532",
966 DIV_MSCL, 0, 3),
967};
968static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
969
970 GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532",
971 ENABLE_ACLK_MSCL, 31, 0, 0),
972 GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532",
973 ENABLE_ACLK_MSCL, 30, 0, 0),
974 GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532",
975 ENABLE_ACLK_MSCL, 29, 0, 0),
976 GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532",
977 ENABLE_ACLK_MSCL, 28, 0, 0),
978 GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0",
979 "usermux_aclk_mscl_532",
980 ENABLE_ACLK_MSCL, 27, 0, 0),
981 GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1",
982 "usermux_aclk_mscl_532",
983 ENABLE_ACLK_MSCL, 26, 0, 0),
984 GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532",
985 ENABLE_ACLK_MSCL, 25, 0, 0),
986 GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532",
987 ENABLE_ACLK_MSCL, 24, 0, 0),
988 GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge",
989 "usermux_aclk_mscl_532",
990 ENABLE_ACLK_MSCL, 23, 0, 0),
991 GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532",
992 ENABLE_ACLK_MSCL, 22, 0, 0),
993 GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532",
994 ENABLE_ACLK_MSCL, 21, 0, 0),
995 GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532",
996 ENABLE_ACLK_MSCL, 20, 0, 0),
997 GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532",
998 ENABLE_ACLK_MSCL, 19, 0, 0),
999 GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532",
1000 ENABLE_ACLK_MSCL, 18, 0, 0),
1001 GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532",
1002 ENABLE_ACLK_MSCL, 17, 0, 0),
1003 GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532",
1004 ENABLE_ACLK_MSCL, 16, 0, 0),
1005 GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p",
1006 "usermux_aclk_mscl_532",
1007 ENABLE_ACLK_MSCL, 15, 0, 0),
1008 GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p",
1009 "usermux_aclk_mscl_532",
1010 ENABLE_ACLK_MSCL, 14, 0, 0),
1011
1012 GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl",
1013 ENABLE_PCLK_MSCL, 31, 0, 0),
1014 GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl",
1015 ENABLE_PCLK_MSCL, 30, 0, 0),
1016 GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl",
1017 ENABLE_PCLK_MSCL, 29, 0, 0),
1018 GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl",
1019 ENABLE_PCLK_MSCL, 28, 0, 0),
1020 GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl",
1021 ENABLE_PCLK_MSCL, 27, 0, 0),
1022 GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl",
1023 ENABLE_PCLK_MSCL, 26, 0, 0),
1024 GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl",
1025 ENABLE_PCLK_MSCL, 25, 0, 0),
1026 GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl",
1027 ENABLE_PCLK_MSCL, 24, 0, 0),
1028 GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl",
1029 ENABLE_PCLK_MSCL, 23, 0, 0),
1030 GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl",
1031 ENABLE_PCLK_MSCL, 22, 0, 0),
1032 GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl",
1033 ENABLE_PCLK_MSCL, 21, 0, 0),
1034 GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl",
1035 ENABLE_PCLK_MSCL, 20, 0, 0),
1036};
1037
1038static struct samsung_cmu_info mscl_cmu_info __initdata = {
1039 .mux_clks = mscl_mux_clks,
1040 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
1041 .div_clks = mscl_div_clks,
1042 .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
1043 .gate_clks = mscl_gate_clks,
1044 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
1045 .nr_clk_ids = MSCL_NR_CLK,
1046 .clk_regs = mscl_clk_regs,
1047 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
1048};
1049
1050static void __init exynos7_clk_mscl_init(struct device_node *np)
1051{
1052 samsung_cmu_register_one(np, &mscl_cmu_info);
1053}
1054
1055CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl",
1056 exynos7_clk_mscl_init);
9f930a39
PV		 1057
1058/* Register Offset definitions for CMU_AUD (0x114C0000) */
1059#define MUX_SEL_AUD 0x0200
1060#define DIV_AUD0 0x0600
1061#define DIV_AUD1 0x0604
1062#define ENABLE_ACLK_AUD 0x0800
1063#define ENABLE_PCLK_AUD 0x0900
1064#define ENABLE_SCLK_AUD 0x0A00
1065
1066/*
1067 * List of parent clocks for Muxes in CMU_AUD
1068 */
1069PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" };
1070PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" };
1071
1072static unsigned long aud_clk_regs[] __initdata = {
1073 MUX_SEL_AUD,
1074 DIV_AUD0,
1075 DIV_AUD1,
1076 ENABLE_ACLK_AUD,
1077 ENABLE_PCLK_AUD,
1078 ENABLE_SCLK_AUD,
1079};
1080
1081static struct samsung_mux_clock aud_mux_clks[] __initdata = {
1082 MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1),
1083 MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1),
1084 MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1),
1085};
1086
1087static struct samsung_div_clock aud_div_clks[] __initdata = {
1088 DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4),
1089 DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4),
1090 DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4),
1091
1092 DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4),
1093 DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8),
1094 DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4),
1095 DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5),
1096 DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4),
1097};
1098
1099static struct samsung_gate_clock aud_gate_clks[] __initdata = {
1100 GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm",
1101 ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
1102 GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s",
1103 ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0),
1104 GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0),
1105 GATE(0, "sclk_slimbus", "dout_sclk_slimbus",
1106 ENABLE_SCLK_AUD, 30, 0, 0),
1107
1108 GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0),
1109 GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0),
1110 GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0),
1111 GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0),
1112 GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0),
1113 GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0),
1114 GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud",
1115 ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0),
1116 GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud",
1117 ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
1118 GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0),
1119 GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0),
1120
1121 GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0),
1122 GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud",
1123 ENABLE_ACLK_AUD, 28, 0, 0),
1124 GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0),
1125};
1126
1127static struct samsung_cmu_info aud_cmu_info __initdata = {
1128 .mux_clks = aud_mux_clks,
1129 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
1130 .div_clks = aud_div_clks,
1131 .nr_div_clks = ARRAY_SIZE(aud_div_clks),
1132 .gate_clks = aud_gate_clks,
1133 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
1134 .nr_clk_ids = AUD_NR_CLK,
1135 .clk_regs = aud_clk_regs,
1136 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
1137};
1138
1139static void __init exynos7_clk_aud_init(struct device_node *np)
1140{
1141 samsung_cmu_register_one(np, &aud_cmu_info);
1142}
1143
1144CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud",
1145 exynos7_clk_aud_init);
Linux 6.x block layer and io_uring tree(s)