[linux-2.6-block.git] / drivers / clk / samsung / clk-exynos5440.c

/*
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 * Author: Thomas Abraham <thomas.ab@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Common Clock Framework support for Exynos5440 SoC.
*/

#include <dt-bindings/clock/exynos5440.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/notifier.h>
#include <linux/reboot.h>

#include "clk.h"
#include "clk-pll.h"

#define CLKEN_OV_VAL		0xf8
#define CPU_CLK_STATUS		0xfc
#define MISC_DOUT1		0x558

static void __iomem *reg_base;

/* parent clock name list */
PNAME(mout_armclk_p)	= { "cplla", "cpllb" };
PNAME(mout_spi_p)	= { "div125", "div200" };

/* fixed rate clocks generated outside the soc */
static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
	FRATE(0, "xtal", NULL, 0, 0),
};

/* fixed rate clocks */
static const struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initconst = {
	FRATE(0, "ppll", NULL, 0, 1000000000),
	FRATE(0, "usb_phy0", NULL, 0, 60000000),
	FRATE(0, "usb_phy1", NULL, 0, 60000000),
	FRATE(0, "usb_ohci12", NULL, 0, 12000000),
	FRATE(0, "usb_ohci48", NULL, 0, 48000000),
};

/* fixed factor clocks */
static const struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initconst = {
	FFACTOR(0, "div250", "ppll", 1, 4, 0),
	FFACTOR(0, "div200", "ppll", 1, 5, 0),
	FFACTOR(0, "div125", "div250", 1, 2, 0),
};

/* mux clocks */
static const struct samsung_mux_clock exynos5440_mux_clks[] __initconst = {
	MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
	MUX(CLK_ARM_CLK, "arm_clk", mout_armclk_p, CPU_CLK_STATUS, 0, 1),
};

/* divider clocks */
static const struct samsung_div_clock exynos5440_div_clks[] __initconst = {
	DIV(CLK_SPI_BAUD, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
};

/* gate clocks */
static const struct samsung_gate_clock exynos5440_gate_clks[] __initconst = {
	GATE(CLK_PB0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
	GATE(CLK_PR0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
	GATE(CLK_PR1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
	GATE(CLK_B_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
	GATE(CLK_B_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0),
	GATE(CLK_B_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0),
	GATE(CLK_SATA, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0),
	GATE(CLK_USB, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0),
	GATE(CLK_GMAC0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0),
	GATE(CLK_CS250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0),
	GATE(CLK_PB0_250_O, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0),
	GATE(CLK_PR0_250_O, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0),
	GATE(CLK_PR1_250_O, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0),
	GATE(CLK_B_250_O, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0),
	GATE(CLK_B_125_O, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0),
	GATE(CLK_B_200_O, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0),
	GATE(CLK_SATA_O, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0),
	GATE(CLK_USB_O, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0),
	GATE(CLK_GMAC0_O, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0),
	GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
};

static const struct of_device_id ext_clk_match[] __initconst = {
	{ .compatible = "samsung,clock-xtal", .data = (void *)0, },
	{},
};

static int exynos5440_clk_restart_notify(struct notifier_block *this,
		unsigned long code, void *unused)
{
	u32 val, status;

	status = readl_relaxed(reg_base + 0xbc);
	val = readl_relaxed(reg_base + 0xcc);
	val = (val & 0xffff0000) | (status & 0xffff);
	writel_relaxed(val, reg_base + 0xcc);

	return NOTIFY_DONE;
}

/*
 * Exynos5440 Clock restart notifier, handles restart functionality
 */
static struct notifier_block exynos5440_clk_restart_handler = {
	.notifier_call = exynos5440_clk_restart_notify,
	.priority = 128,
};

static const struct samsung_pll_clock exynos5440_plls[] __initconst = {
	PLL(pll_2550x, CLK_CPLLA, "cplla", "xtal", 0, 0x4c, NULL),
	PLL(pll_2550x, CLK_CPLLB, "cpllb", "xtal", 0, 0x50, NULL),
};

/*
 * Clock aliases for legacy clkdev look-up.
 */
static const struct samsung_clock_alias exynos5440_aliases[] __initconst = {
	ALIAS(CLK_ARM_CLK, NULL, "armclk"),
};

/* register exynos5440 clocks */
static void __init exynos5440_clk_init(struct device_node *np)
{
	struct samsung_clk_provider *ctx;

	reg_base = of_iomap(np, 0);
	if (!reg_base) {
		pr_err("%s: failed to map clock controller registers,"
			" aborting clock initialization\n", __func__);
		return;
	}

	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);

	samsung_clk_of_register_fixed_ext(ctx, exynos5440_fixed_rate_ext_clks,
		ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);

	samsung_clk_register_pll(ctx, exynos5440_plls,
			ARRAY_SIZE(exynos5440_plls), ctx->reg_base);

	samsung_clk_register_fixed_rate(ctx, exynos5440_fixed_rate_clks,
			ARRAY_SIZE(exynos5440_fixed_rate_clks));
	samsung_clk_register_fixed_factor(ctx, exynos5440_fixed_factor_clks,
			ARRAY_SIZE(exynos5440_fixed_factor_clks));
	samsung_clk_register_mux(ctx, exynos5440_mux_clks,
			ARRAY_SIZE(exynos5440_mux_clks));
	samsung_clk_register_div(ctx, exynos5440_div_clks,
			ARRAY_SIZE(exynos5440_div_clks));
	samsung_clk_register_gate(ctx, exynos5440_gate_clks,
			ARRAY_SIZE(exynos5440_gate_clks));
	samsung_clk_register_alias(ctx, exynos5440_aliases,
						ARRAY_SIZE(exynos5440_aliases));

	samsung_clk_of_add_provider(np, ctx);

	if (register_restart_handler(&exynos5440_clk_restart_handler))
		pr_warn("exynos5440 clock can't register restart handler\n");

	pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
	pr_info("exynos5440 clock initialization complete\n");
}
CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock", exynos5440_clk_init);
Commit	Line	Data
f2585b1c TA	1	/*
	2	* Copyright (c) 2013 Samsung Electronics Co., Ltd.
	3	* Author: Thomas Abraham <thomas.ab@samsung.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* Common Clock Framework support for Exynos5440 SoC.
	10	*/
	11
ad3ab455	12	#include <dt-bindings/clock/exynos5440.h>
f2585b1c TA	13	#include <linux/clk-provider.h>
	14	#include <linux/of.h>
	15	#include <linux/of_address.h>
5e6473f4 PD	16	#include <linux/notifier.h>
5e6473f4 PD	17	#include <linux/reboot.h>
f2585b1c	18
f2585b1c TA	19	#include "clk.h"
	20	#include "clk-pll.h"
	21
	22	#define CLKEN_OV_VAL 0xf8
	23	#define CPU_CLK_STATUS 0xfc
	24	#define MISC_DOUT1 0x558
	25
5e6473f4 PD	26	static void __iomem *reg_base;
5e6473f4 PD	27
f2585b1c TA	28	/* parent clock name list */
	29	PNAME(mout_armclk_p) = { "cplla", "cpllb" };
	30	PNAME(mout_spi_p) = { "div125", "div200" };
	31
	32	/* fixed rate clocks generated outside the soc */
901f8576	33	static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
728f288d	34	FRATE(0, "xtal", NULL, 0, 0),
f2585b1c TA	35	};
	36
	37	/* fixed rate clocks */
880c81b3	38	static const struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initconst = {
728f288d SB	39	FRATE(0, "ppll", NULL, 0, 1000000000),
	40	FRATE(0, "usb_phy0", NULL, 0, 60000000),
	41	FRATE(0, "usb_phy1", NULL, 0, 60000000),
	42	FRATE(0, "usb_ohci12", NULL, 0, 12000000),
	43	FRATE(0, "usb_ohci48", NULL, 0, 48000000),
f2585b1c TA	44	};
	45
	46	/* fixed factor clocks */
880c81b3	47	static const struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initconst = {
ad3ab455 AH	48	FFACTOR(0, "div250", "ppll", 1, 4, 0),
	49	FFACTOR(0, "div200", "ppll", 1, 5, 0),
	50	FFACTOR(0, "div125", "div250", 1, 2, 0),
f2585b1c TA	51	};
	52
	53	/* mux clocks */
880c81b3	54	static const struct samsung_mux_clock exynos5440_mux_clks[] __initconst = {
ad3ab455	55	MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
efea8d37	56	MUX(CLK_ARM_CLK, "arm_clk", mout_armclk_p, CPU_CLK_STATUS, 0, 1),
f2585b1c TA	57	};
	58
	59	/* divider clocks */
880c81b3	60	static const struct samsung_div_clock exynos5440_div_clks[] __initconst = {
ad3ab455	61	DIV(CLK_SPI_BAUD, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
f2585b1c TA	62	};
	63
	64	/* gate clocks */
880c81b3	65	static const struct samsung_gate_clock exynos5440_gate_clks[] __initconst = {
ad3ab455 AH	66	GATE(CLK_PB0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
	67	GATE(CLK_PR0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
	68	GATE(CLK_PR1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
	69	GATE(CLK_B_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
	70	GATE(CLK_B_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0),
	71	GATE(CLK_B_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0),
	72	GATE(CLK_SATA, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0),
	73	GATE(CLK_USB, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0),
	74	GATE(CLK_GMAC0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0),
	75	GATE(CLK_CS250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0),
	76	GATE(CLK_PB0_250_O, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0),
	77	GATE(CLK_PR0_250_O, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0),
	78	GATE(CLK_PR1_250_O, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0),
	79	GATE(CLK_B_250_O, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0),
	80	GATE(CLK_B_125_O, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0),
	81	GATE(CLK_B_200_O, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0),
	82	GATE(CLK_SATA_O, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0),
	83	GATE(CLK_USB_O, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0),
	84	GATE(CLK_GMAC0_O, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0),
	85	GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
f2585b1c TA	86	};
f2585b1c TA	87
305cfab0	88	static const struct of_device_id ext_clk_match[] __initconst = {
f2585b1c TA	89	{ .compatible = "samsung,clock-xtal", .data = (void *)0, },
	90	{},
	91	};
	92
5e6473f4 PD	93	static int exynos5440_clk_restart_notify(struct notifier_block *this,
	94	unsigned long code, void *unused)
	95	{
	96	u32 val, status;
	97
	98	status = readl_relaxed(reg_base + 0xbc);
	99	val = readl_relaxed(reg_base + 0xcc);
	100	val = (val & 0xffff0000) \| (status & 0xffff);
	101	writel_relaxed(val, reg_base + 0xcc);
	102
	103	return NOTIFY_DONE;
	104	}
	105
	106	/*
	107	* Exynos5440 Clock restart notifier, handles restart functionality
	108	*/
	109	static struct notifier_block exynos5440_clk_restart_handler = {
	110	.notifier_call = exynos5440_clk_restart_notify,
	111	.priority = 128,
	112	};
	113
1d9aa64c SN	114	static const struct samsung_pll_clock exynos5440_plls[] __initconst = {
	115	PLL(pll_2550x, CLK_CPLLA, "cplla", "xtal", 0, 0x4c, NULL),
	116	PLL(pll_2550x, CLK_CPLLB, "cpllb", "xtal", 0, 0x50, NULL),
	117	};
	118
efea8d37 MS	119	/*
	120	* Clock aliases for legacy clkdev look-up.
	121	*/
	122	static const struct samsung_clock_alias exynos5440_aliases[] __initconst = {
	123	ALIAS(CLK_ARM_CLK, NULL, "armclk"),
	124	};
	125
f2585b1c	126	/* register exynos5440 clocks */
901f8576	127	static void __init exynos5440_clk_init(struct device_node *np)
f2585b1c	128	{
976face4	129	struct samsung_clk_provider *ctx;
f2585b1c TA	130
	131	reg_base = of_iomap(np, 0);
	132	if (!reg_base) {
	133	pr_err("%s: failed to map clock controller registers,"
	134	" aborting clock initialization\n", __func__);
	135	return;
	136	}
	137
976face4	138	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
976face4 RS	139
976face4 RS	140	samsung_clk_of_register_fixed_ext(ctx, exynos5440_fixed_rate_ext_clks,
f2585b1c TA	141	ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
f2585b1c TA	142
1d9aa64c SN	143	samsung_clk_register_pll(ctx, exynos5440_plls,
1d9aa64c SN	144	ARRAY_SIZE(exynos5440_plls), ctx->reg_base);
f2585b1c	145
976face4	146	samsung_clk_register_fixed_rate(ctx, exynos5440_fixed_rate_clks,
f2585b1c	147	ARRAY_SIZE(exynos5440_fixed_rate_clks));
976face4	148	samsung_clk_register_fixed_factor(ctx, exynos5440_fixed_factor_clks,
f2585b1c	149	ARRAY_SIZE(exynos5440_fixed_factor_clks));
976face4	150	samsung_clk_register_mux(ctx, exynos5440_mux_clks,
f2585b1c	151	ARRAY_SIZE(exynos5440_mux_clks));
976face4	152	samsung_clk_register_div(ctx, exynos5440_div_clks,
f2585b1c	153	ARRAY_SIZE(exynos5440_div_clks));
976face4	154	samsung_clk_register_gate(ctx, exynos5440_gate_clks,
f2585b1c	155	ARRAY_SIZE(exynos5440_gate_clks));
efea8d37 MS	156	samsung_clk_register_alias(ctx, exynos5440_aliases,
efea8d37 MS	157	ARRAY_SIZE(exynos5440_aliases));
f2585b1c	158
d5e136a2 SN	159	samsung_clk_of_add_provider(np, ctx);
d5e136a2 SN	160
5e6473f4 PD	161	if (register_restart_handler(&exynos5440_clk_restart_handler))
	162	pr_warn("exynos5440 clock can't register restart handler\n");
	163
3a647895	164	pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
f2585b1c TA	165	pr_info("exynos5440 clock initialization complete\n");
	166	}
	167	CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock", exynos5440_clk_init);