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96bd6224 CC |
1 | /* |
2 | * Copyright (c) 2014 Samsung Electronics Co., Ltd. | |
3 | * Author: Chanwoo Choi <cw00.choi@samsung.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * Common Clock Framework support for Exynos5443 SoC. | |
10 | */ | |
11 | ||
12 | #include <linux/clk.h> | |
13 | #include <linux/clkdev.h> | |
14 | #include <linux/clk-provider.h> | |
15 | #include <linux/of.h> | |
16 | ||
17 | #include <dt-bindings/clock/exynos5433.h> | |
18 | ||
19 | #include "clk.h" | |
20 | #include "clk-pll.h" | |
21 | ||
22 | /* | |
23 | * Register offset definitions for CMU_TOP | |
24 | */ | |
25 | #define ISP_PLL_LOCK 0x0000 | |
26 | #define AUD_PLL_LOCK 0x0004 | |
27 | #define ISP_PLL_CON0 0x0100 | |
28 | #define ISP_PLL_CON1 0x0104 | |
29 | #define ISP_PLL_FREQ_DET 0x0108 | |
30 | #define AUD_PLL_CON0 0x0110 | |
31 | #define AUD_PLL_CON1 0x0114 | |
32 | #define AUD_PLL_CON2 0x0118 | |
33 | #define AUD_PLL_FREQ_DET 0x011c | |
34 | #define MUX_SEL_TOP0 0x0200 | |
35 | #define MUX_SEL_TOP1 0x0204 | |
36 | #define MUX_SEL_TOP2 0x0208 | |
37 | #define MUX_SEL_TOP3 0x020c | |
38 | #define MUX_SEL_TOP4 0x0210 | |
39 | #define MUX_SEL_TOP_MSCL 0x0220 | |
40 | #define MUX_SEL_TOP_CAM1 0x0224 | |
41 | #define MUX_SEL_TOP_DISP 0x0228 | |
42 | #define MUX_SEL_TOP_FSYS0 0x0230 | |
43 | #define MUX_SEL_TOP_FSYS1 0x0234 | |
44 | #define MUX_SEL_TOP_PERIC0 0x0238 | |
45 | #define MUX_SEL_TOP_PERIC1 0x023c | |
46 | #define MUX_ENABLE_TOP0 0x0300 | |
47 | #define MUX_ENABLE_TOP1 0x0304 | |
48 | #define MUX_ENABLE_TOP2 0x0308 | |
49 | #define MUX_ENABLE_TOP3 0x030c | |
50 | #define MUX_ENABLE_TOP4 0x0310 | |
51 | #define MUX_ENABLE_TOP_MSCL 0x0320 | |
52 | #define MUX_ENABLE_TOP_CAM1 0x0324 | |
53 | #define MUX_ENABLE_TOP_DISP 0x0328 | |
54 | #define MUX_ENABLE_TOP_FSYS0 0x0330 | |
55 | #define MUX_ENABLE_TOP_FSYS1 0x0334 | |
56 | #define MUX_ENABLE_TOP_PERIC0 0x0338 | |
57 | #define MUX_ENABLE_TOP_PERIC1 0x033c | |
58 | #define MUX_STAT_TOP0 0x0400 | |
59 | #define MUX_STAT_TOP1 0x0404 | |
60 | #define MUX_STAT_TOP2 0x0408 | |
61 | #define MUX_STAT_TOP3 0x040c | |
62 | #define MUX_STAT_TOP4 0x0410 | |
63 | #define MUX_STAT_TOP_MSCL 0x0420 | |
64 | #define MUX_STAT_TOP_CAM1 0x0424 | |
65 | #define MUX_STAT_TOP_FSYS0 0x0430 | |
66 | #define MUX_STAT_TOP_FSYS1 0x0434 | |
67 | #define MUX_STAT_TOP_PERIC0 0x0438 | |
68 | #define MUX_STAT_TOP_PERIC1 0x043c | |
69 | #define DIV_TOP0 0x0600 | |
70 | #define DIV_TOP1 0x0604 | |
71 | #define DIV_TOP2 0x0608 | |
72 | #define DIV_TOP3 0x060c | |
73 | #define DIV_TOP4 0x0610 | |
74 | #define DIV_TOP_MSCL 0x0618 | |
75 | #define DIV_TOP_CAM10 0x061c | |
76 | #define DIV_TOP_CAM11 0x0620 | |
77 | #define DIV_TOP_FSYS0 0x062c | |
78 | #define DIV_TOP_FSYS1 0x0630 | |
79 | #define DIV_TOP_FSYS2 0x0634 | |
80 | #define DIV_TOP_PERIC0 0x0638 | |
81 | #define DIV_TOP_PERIC1 0x063c | |
82 | #define DIV_TOP_PERIC2 0x0640 | |
83 | #define DIV_TOP_PERIC3 0x0644 | |
84 | #define DIV_TOP_PERIC4 0x0648 | |
85 | #define DIV_TOP_PLL_FREQ_DET 0x064c | |
86 | #define DIV_STAT_TOP0 0x0700 | |
87 | #define DIV_STAT_TOP1 0x0704 | |
88 | #define DIV_STAT_TOP2 0x0708 | |
89 | #define DIV_STAT_TOP3 0x070c | |
90 | #define DIV_STAT_TOP4 0x0710 | |
91 | #define DIV_STAT_TOP_MSCL 0x0718 | |
92 | #define DIV_STAT_TOP_CAM10 0x071c | |
93 | #define DIV_STAT_TOP_CAM11 0x0720 | |
94 | #define DIV_STAT_TOP_FSYS0 0x072c | |
95 | #define DIV_STAT_TOP_FSYS1 0x0730 | |
96 | #define DIV_STAT_TOP_FSYS2 0x0734 | |
97 | #define DIV_STAT_TOP_PERIC0 0x0738 | |
98 | #define DIV_STAT_TOP_PERIC1 0x073c | |
99 | #define DIV_STAT_TOP_PERIC2 0x0740 | |
100 | #define DIV_STAT_TOP_PERIC3 0x0744 | |
101 | #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c | |
102 | #define ENABLE_ACLK_TOP 0x0800 | |
103 | #define ENABLE_SCLK_TOP 0x0a00 | |
104 | #define ENABLE_SCLK_TOP_MSCL 0x0a04 | |
105 | #define ENABLE_SCLK_TOP_CAM1 0x0a08 | |
106 | #define ENABLE_SCLK_TOP_DISP 0x0a0c | |
107 | #define ENABLE_SCLK_TOP_FSYS 0x0a10 | |
108 | #define ENABLE_SCLK_TOP_PERIC 0x0a14 | |
109 | #define ENABLE_IP_TOP 0x0b00 | |
110 | #define ENABLE_CMU_TOP 0x0c00 | |
111 | #define ENABLE_CMU_TOP_DIV_STAT 0x0c04 | |
112 | ||
113 | static unsigned long top_clk_regs[] __initdata = { | |
114 | ISP_PLL_LOCK, | |
115 | AUD_PLL_LOCK, | |
116 | ISP_PLL_CON0, | |
117 | ISP_PLL_CON1, | |
118 | ISP_PLL_FREQ_DET, | |
119 | AUD_PLL_CON0, | |
120 | AUD_PLL_CON1, | |
121 | AUD_PLL_CON2, | |
122 | AUD_PLL_FREQ_DET, | |
123 | MUX_SEL_TOP0, | |
124 | MUX_SEL_TOP1, | |
125 | MUX_SEL_TOP2, | |
126 | MUX_SEL_TOP3, | |
127 | MUX_SEL_TOP4, | |
128 | MUX_SEL_TOP_MSCL, | |
129 | MUX_SEL_TOP_CAM1, | |
130 | MUX_SEL_TOP_DISP, | |
131 | MUX_SEL_TOP_FSYS0, | |
132 | MUX_SEL_TOP_FSYS1, | |
133 | MUX_SEL_TOP_PERIC0, | |
134 | MUX_SEL_TOP_PERIC1, | |
135 | MUX_ENABLE_TOP0, | |
136 | MUX_ENABLE_TOP1, | |
137 | MUX_ENABLE_TOP2, | |
138 | MUX_ENABLE_TOP3, | |
139 | MUX_ENABLE_TOP4, | |
140 | MUX_ENABLE_TOP_MSCL, | |
141 | MUX_ENABLE_TOP_CAM1, | |
142 | MUX_ENABLE_TOP_DISP, | |
143 | MUX_ENABLE_TOP_FSYS0, | |
144 | MUX_ENABLE_TOP_FSYS1, | |
145 | MUX_ENABLE_TOP_PERIC0, | |
146 | MUX_ENABLE_TOP_PERIC1, | |
147 | MUX_STAT_TOP0, | |
148 | MUX_STAT_TOP1, | |
149 | MUX_STAT_TOP2, | |
150 | MUX_STAT_TOP3, | |
151 | MUX_STAT_TOP4, | |
152 | MUX_STAT_TOP_MSCL, | |
153 | MUX_STAT_TOP_CAM1, | |
154 | MUX_STAT_TOP_FSYS0, | |
155 | MUX_STAT_TOP_FSYS1, | |
156 | MUX_STAT_TOP_PERIC0, | |
157 | MUX_STAT_TOP_PERIC1, | |
158 | DIV_TOP0, | |
159 | DIV_TOP1, | |
160 | DIV_TOP2, | |
161 | DIV_TOP3, | |
162 | DIV_TOP4, | |
163 | DIV_TOP_MSCL, | |
164 | DIV_TOP_CAM10, | |
165 | DIV_TOP_CAM11, | |
166 | DIV_TOP_FSYS0, | |
167 | DIV_TOP_FSYS1, | |
168 | DIV_TOP_FSYS2, | |
169 | DIV_TOP_PERIC0, | |
170 | DIV_TOP_PERIC1, | |
171 | DIV_TOP_PERIC2, | |
172 | DIV_TOP_PERIC3, | |
173 | DIV_TOP_PERIC4, | |
174 | DIV_TOP_PLL_FREQ_DET, | |
175 | DIV_STAT_TOP0, | |
176 | DIV_STAT_TOP1, | |
177 | DIV_STAT_TOP2, | |
178 | DIV_STAT_TOP3, | |
179 | DIV_STAT_TOP4, | |
180 | DIV_STAT_TOP_MSCL, | |
181 | DIV_STAT_TOP_CAM10, | |
182 | DIV_STAT_TOP_CAM11, | |
183 | DIV_STAT_TOP_FSYS0, | |
184 | DIV_STAT_TOP_FSYS1, | |
185 | DIV_STAT_TOP_FSYS2, | |
186 | DIV_STAT_TOP_PERIC0, | |
187 | DIV_STAT_TOP_PERIC1, | |
188 | DIV_STAT_TOP_PERIC2, | |
189 | DIV_STAT_TOP_PERIC3, | |
190 | DIV_STAT_TOP_PLL_FREQ_DET, | |
191 | ENABLE_ACLK_TOP, | |
192 | ENABLE_SCLK_TOP, | |
193 | ENABLE_SCLK_TOP_MSCL, | |
194 | ENABLE_SCLK_TOP_CAM1, | |
195 | ENABLE_SCLK_TOP_DISP, | |
196 | ENABLE_SCLK_TOP_FSYS, | |
197 | ENABLE_SCLK_TOP_PERIC, | |
198 | ENABLE_IP_TOP, | |
199 | ENABLE_CMU_TOP, | |
200 | ENABLE_CMU_TOP_DIV_STAT, | |
201 | }; | |
202 | ||
203 | /* list of all parent clock list */ | |
204 | PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", }; | |
205 | PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", }; | |
206 | PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", }; | |
207 | PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", }; | |
208 | PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", }; | |
209 | PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", }; | |
210 | PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", }; | |
23236496 | 211 | PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", }; |
96bd6224 CC |
212 | |
213 | PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",}; | |
214 | PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",}; | |
215 | PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a", | |
216 | "mout_mfc_pll_user", }; | |
217 | PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", }; | |
218 | ||
23236496 CC |
219 | PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b", |
220 | "mout_mphy_pll_user", }; | |
221 | PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a", | |
222 | "mout_bus_pll_user", }; | |
223 | PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", }; | |
224 | ||
96bd6224 CC |
225 | PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user", |
226 | "mout_mphy_pll_user", }; | |
227 | PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a", | |
228 | "mout_mphy_pll_user", }; | |
229 | PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a", | |
230 | "mout_mphy_pll_user", }; | |
231 | ||
232 | PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",}; | |
233 | PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", }; | |
234 | ||
235 | PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",}; | |
236 | PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",}; | |
237 | PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", }; | |
238 | PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",}; | |
239 | PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", }; | |
240 | ||
23236496 CC |
241 | PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1", |
242 | "oscclk", "ioclk_spdif_extclk", }; | |
243 | PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk", | |
244 | "mout_aud_pll_user_t",}; | |
245 | PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk", | |
246 | "mout_aud_pll_user_t",}; | |
247 | ||
2a1808a6 CC |
248 | PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", }; |
249 | ||
56bcf3f3 CC |
250 | static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = { |
251 | FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0), | |
252 | }; | |
253 | ||
23236496 CC |
254 | static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = { |
255 | /* Xi2s{0|1}CDCLK input clock for I2S/PCM */ | |
256 | FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 100000000), | |
257 | FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000), | |
258 | /* Xi2s1SDI input clock for SPDIF */ | |
259 | FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000), | |
d0f5de66 CC |
260 | /* XspiCLK[4:0] input clock for SPI */ |
261 | FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000), | |
262 | FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000), | |
263 | FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000), | |
264 | FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000), | |
265 | FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000), | |
266 | /* Xi2s1SCLK input clock for I2S1_BCLK */ | |
267 | FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000), | |
23236496 CC |
268 | }; |
269 | ||
96bd6224 CC |
270 | static struct samsung_mux_clock top_mux_clks[] __initdata = { |
271 | /* MUX_SEL_TOP0 */ | |
272 | MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0, | |
273 | 4, 1), | |
274 | MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0, | |
275 | 0, 1), | |
276 | ||
277 | /* MUX_SEL_TOP1 */ | |
278 | MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t", | |
279 | mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1), | |
280 | MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p, | |
281 | MUX_SEL_TOP1, 8, 1), | |
282 | MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p, | |
283 | MUX_SEL_TOP1, 4, 1), | |
284 | MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p, | |
285 | MUX_SEL_TOP1, 0, 1), | |
286 | ||
287 | /* MUX_SEL_TOP2 */ | |
288 | MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400", | |
289 | mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1), | |
290 | MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333", | |
291 | mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1), | |
292 | MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b", | |
293 | mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1), | |
294 | MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a", | |
295 | mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1), | |
296 | MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400", | |
297 | mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1), | |
298 | MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400", | |
299 | mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1), | |
300 | ||
301 | /* MUX_SEL_TOP3 */ | |
302 | MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400", | |
303 | mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1), | |
304 | MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b", | |
305 | mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1), | |
306 | MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a", | |
307 | mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1), | |
308 | MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333", | |
309 | mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1), | |
310 | MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b", | |
311 | mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1), | |
312 | MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a", | |
313 | mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1), | |
314 | ||
23236496 CC |
315 | /* MUX_SEL_TOP4 */ |
316 | MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c", | |
317 | mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1), | |
318 | MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b", | |
319 | mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1), | |
320 | MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a", | |
321 | mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1), | |
322 | ||
96bd6224 CC |
323 | /* MUX_SEL_TOP_MSCL */ |
324 | MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p, | |
325 | MUX_SEL_TOP_MSCL, 8, 1), | |
326 | MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p, | |
327 | MUX_SEL_TOP_MSCL, 4, 1), | |
328 | MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p, | |
329 | MUX_SEL_TOP_MSCL, 0, 1), | |
330 | ||
23236496 CC |
331 | /* MUX_SEL_TOP_CAM1 */ |
332 | MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2", | |
333 | mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1), | |
334 | MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1", | |
335 | mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1), | |
336 | MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0", | |
337 | mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1), | |
338 | MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart", | |
339 | mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1), | |
340 | MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1", | |
341 | mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1), | |
342 | MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0", | |
343 | mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1), | |
344 | ||
96bd6224 CC |
345 | /* MUX_SEL_TOP_FSYS0 */ |
346 | MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p, | |
347 | MUX_SEL_TOP_FSYS0, 28, 1), | |
348 | MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p, | |
349 | MUX_SEL_TOP_FSYS0, 24, 1), | |
350 | MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p, | |
351 | MUX_SEL_TOP_FSYS0, 20, 1), | |
352 | MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p, | |
353 | MUX_SEL_TOP_FSYS0, 16, 1), | |
354 | MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p, | |
355 | MUX_SEL_TOP_FSYS0, 12, 1), | |
356 | MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p, | |
357 | MUX_SEL_TOP_FSYS0, 8, 1), | |
358 | MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p, | |
359 | MUX_SEL_TOP_FSYS0, 4, 1), | |
360 | MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p, | |
361 | MUX_SEL_TOP_FSYS0, 0, 1), | |
362 | ||
23236496 CC |
363 | /* MUX_SEL_TOP_FSYS1 */ |
364 | MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p, | |
365 | MUX_SEL_TOP_FSYS1, 12, 1), | |
366 | MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro", | |
367 | mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1), | |
368 | MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30", | |
369 | mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1), | |
370 | MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30", | |
371 | mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1), | |
372 | ||
96bd6224 CC |
373 | /* MUX_SEL_TOP_PERIC0 */ |
374 | MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p, | |
375 | MUX_SEL_TOP_PERIC0, 28, 1), | |
376 | MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p, | |
377 | MUX_SEL_TOP_PERIC0, 24, 1), | |
378 | MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p, | |
379 | MUX_SEL_TOP_PERIC0, 20, 1), | |
380 | MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p, | |
381 | MUX_SEL_TOP_PERIC0, 16, 1), | |
382 | MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p, | |
383 | MUX_SEL_TOP_PERIC0, 12, 1), | |
384 | MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p, | |
385 | MUX_SEL_TOP_PERIC0, 8, 1), | |
386 | MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p, | |
387 | MUX_SEL_TOP_PERIC0, 4, 1), | |
388 | MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p, | |
389 | MUX_SEL_TOP_PERIC0, 0, 1), | |
23236496 CC |
390 | |
391 | /* MUX_SEL_TOP_PERIC1 */ | |
392 | MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p, | |
393 | MUX_SEL_TOP_PERIC1, 16, 1), | |
394 | MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p, | |
395 | MUX_SEL_TOP_PERIC1, 12, 2), | |
396 | MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p, | |
397 | MUX_SEL_TOP_PERIC1, 4, 2), | |
398 | MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p, | |
399 | MUX_SEL_TOP_PERIC1, 0, 2), | |
2a1808a6 CC |
400 | |
401 | /* MUX_SEL_TOP_DISP */ | |
402 | MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif", | |
403 | mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1), | |
96bd6224 CC |
404 | }; |
405 | ||
406 | static struct samsung_div_clock top_div_clks[] __initdata = { | |
8e46c4b8 | 407 | /* DIV_TOP0 */ |
a5958a93 CC |
408 | DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333", |
409 | DIV_TOP0, 28, 3), | |
410 | DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user", | |
411 | DIV_TOP0, 24, 3), | |
412 | DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b", | |
413 | DIV_TOP0, 20, 3), | |
6958f22f CC |
414 | DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user", |
415 | DIV_TOP0, 16, 3), | |
416 | DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user", | |
417 | DIV_TOP0, 12, 3), | |
418 | DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll", | |
419 | DIV_TOP0, 8, 3), | |
8e46c4b8 CC |
420 | DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400", |
421 | "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4), | |
422 | DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400", | |
423 | "mout_aclk_isp_400", DIV_TOP0, 0, 4), | |
424 | ||
a29308da CC |
425 | /* DIV_TOP1 */ |
426 | DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333", | |
427 | DIV_TOP1, 28, 3), | |
428 | DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333", | |
429 | DIV_TOP1, 24, 3), | |
430 | DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400", | |
431 | DIV_TOP1, 20, 3), | |
432 | DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c", | |
433 | DIV_TOP1, 12, 3), | |
434 | DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user", | |
435 | DIV_TOP1, 8, 3), | |
436 | DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b", | |
437 | DIV_TOP1, 0, 3), | |
438 | ||
96bd6224 | 439 | /* DIV_TOP2 */ |
b274bbfd CC |
440 | DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b", |
441 | DIV_TOP2, 4, 3), | |
96bd6224 CC |
442 | DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user", |
443 | DIV_TOP2, 0, 3), | |
444 | ||
445 | /* DIV_TOP3 */ | |
446 | DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266", | |
447 | "mout_bus_pll_user", DIV_TOP3, 24, 3), | |
448 | DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200", | |
449 | "mout_bus_pll_user", DIV_TOP3, 20, 3), | |
450 | DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266", | |
451 | "mout_bus_pll_user", DIV_TOP3, 16, 3), | |
452 | DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b", | |
453 | "div_aclk_peric_66_a", DIV_TOP3, 12, 3), | |
454 | DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a", | |
455 | "mout_bus_pll_user", DIV_TOP3, 8, 3), | |
456 | DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b", | |
457 | "div_aclk_peris_66_a", DIV_TOP3, 4, 3), | |
458 | DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a", | |
459 | "mout_bus_pll_user", DIV_TOP3, 0, 3), | |
460 | ||
5785d6e6 CC |
461 | /* DIV_TOP4 */ |
462 | DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user", | |
463 | DIV_TOP4, 8, 3), | |
464 | DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400", | |
465 | DIV_TOP4, 4, 3), | |
466 | DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user", | |
467 | DIV_TOP4, 0, 3), | |
468 | ||
b274bbfd CC |
469 | /* DIV_TOP_MSCL */ |
470 | DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c", | |
471 | DIV_TOP_MSCL, 0, 4), | |
472 | ||
a5958a93 CC |
473 | /* DIV_TOP_CAM10 */ |
474 | DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart", | |
475 | DIV_TOP_CAM10, 24, 5), | |
476 | DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b", | |
477 | "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8), | |
478 | DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a", | |
479 | "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4), | |
480 | DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b", | |
481 | "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8), | |
482 | DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a", | |
483 | "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4), | |
484 | ||
485 | /* DIV_TOP_CAM11 */ | |
486 | DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b", | |
487 | "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4), | |
488 | DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a", | |
489 | "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4), | |
490 | DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b", | |
491 | "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4), | |
492 | DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a", | |
493 | "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4), | |
494 | DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b", | |
495 | "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 12, 4), | |
496 | DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a", | |
497 | "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 8, 4), | |
498 | ||
96bd6224 CC |
499 | /* DIV_TOP_FSYS0 */ |
500 | DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a", | |
501 | DIV_TOP_FSYS0, 16, 8), | |
502 | DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b", | |
503 | DIV_TOP_FSYS0, 12, 4), | |
504 | DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a", | |
505 | DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0), | |
506 | DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d", | |
507 | DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0), | |
508 | ||
509 | /* DIV_TOP_FSYS1 */ | |
510 | DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a", | |
511 | DIV_TOP_FSYS1, 4, 8), | |
512 | DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b", | |
513 | DIV_TOP_FSYS1, 0, 4), | |
514 | ||
4b801355 CC |
515 | /* DIV_TOP_FSYS2 */ |
516 | DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100", | |
517 | DIV_TOP_FSYS2, 12, 3), | |
518 | DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30", | |
519 | "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4), | |
520 | DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro", | |
521 | "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4), | |
522 | DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30", | |
523 | DIV_TOP_FSYS2, 0, 4), | |
524 | ||
96bd6224 CC |
525 | /* DIV_TOP_PERIC0 */ |
526 | DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a", | |
527 | DIV_TOP_PERIC0, 16, 8), | |
528 | DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1", | |
529 | DIV_TOP_PERIC0, 12, 4), | |
530 | DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a", | |
531 | DIV_TOP_PERIC0, 4, 8), | |
532 | DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0", | |
533 | DIV_TOP_PERIC0, 0, 4), | |
534 | ||
535 | /* DIV_TOP_PERIC1 */ | |
536 | DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a", | |
537 | DIV_TOP_PERIC1, 4, 8), | |
538 | DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2", | |
539 | DIV_TOP_PERIC1, 0, 4), | |
540 | ||
541 | /* DIV_TOP_PERIC2 */ | |
542 | DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2", | |
543 | DIV_TOP_PERIC2, 8, 4), | |
544 | DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0", | |
545 | DIV_TOP_PERIC2, 4, 4), | |
546 | DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1", | |
547 | DIV_TOP_PERIC2, 0, 4), | |
548 | ||
23236496 CC |
549 | /* DIV_TOP_PERIC3 */ |
550 | DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1", | |
551 | DIV_TOP_PERIC3, 16, 6), | |
552 | DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1", | |
553 | DIV_TOP_PERIC3, 8, 8), | |
554 | DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1", | |
555 | DIV_TOP_PERIC3, 4, 4), | |
556 | DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0", | |
557 | DIV_TOP_PERIC3, 0, 4), | |
558 | ||
96bd6224 CC |
559 | /* DIV_TOP_PERIC4 */ |
560 | DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a", | |
561 | DIV_TOP_PERIC4, 16, 8), | |
562 | DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4", | |
563 | DIV_TOP_PERIC4, 12, 4), | |
564 | DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a", | |
565 | DIV_TOP_PERIC4, 4, 8), | |
566 | DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3", | |
567 | DIV_TOP_PERIC4, 0, 4), | |
568 | }; | |
569 | ||
570 | static struct samsung_gate_clock top_gate_clks[] __initdata = { | |
571 | /* ENABLE_ACLK_TOP */ | |
5785d6e6 CC |
572 | GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400", |
573 | ENABLE_ACLK_TOP, 30, 0, 0), | |
574 | GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266", | |
575 | "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP, | |
576 | 29, CLK_IGNORE_UNUSED, 0), | |
577 | GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400", | |
578 | ENABLE_ACLK_TOP, 26, | |
579 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), | |
580 | GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400", | |
581 | ENABLE_ACLK_TOP, 25, | |
582 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), | |
583 | GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266", | |
584 | ENABLE_ACLK_TOP, 24, | |
585 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), | |
586 | GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200", | |
587 | ENABLE_ACLK_TOP, 23, | |
588 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), | |
96bd6224 CC |
589 | GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b", |
590 | ENABLE_ACLK_TOP, 22, | |
591 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
592 | GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b", | |
593 | ENABLE_ACLK_TOP, 21, | |
594 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
b274bbfd CC |
595 | GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400", |
596 | ENABLE_ACLK_TOP, 19, | |
597 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
96bd6224 CC |
598 | GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200", |
599 | ENABLE_ACLK_TOP, 18, | |
600 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
2a2f33e8 CC |
601 | GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111", |
602 | ENABLE_ACLK_TOP, 15, | |
603 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
604 | GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333", | |
605 | ENABLE_ACLK_TOP, 14, | |
606 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
a5958a93 CC |
607 | GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333", |
608 | ENABLE_ACLK_TOP, 13, | |
609 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
610 | GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400", | |
611 | ENABLE_ACLK_TOP, 12, | |
612 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
613 | GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552", | |
614 | ENABLE_ACLK_TOP, 11, | |
615 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
6958f22f CC |
616 | GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333", |
617 | ENABLE_ACLK_TOP, 10, | |
618 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
619 | GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400", | |
620 | ENABLE_ACLK_TOP, 9, | |
621 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
622 | GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552", | |
623 | ENABLE_ACLK_TOP, 8, | |
624 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
8e46c4b8 CC |
625 | GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400", |
626 | ENABLE_ACLK_TOP, 7, | |
627 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
628 | GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400", | |
629 | ENABLE_ACLK_TOP, 6, | |
630 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
45e58aa5 CC |
631 | GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400", |
632 | ENABLE_ACLK_TOP, 5, | |
633 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
9910b6bb CC |
634 | GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400", |
635 | ENABLE_ACLK_TOP, 3, | |
636 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
a29308da CC |
637 | GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266", |
638 | ENABLE_ACLK_TOP, 2, | |
639 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
640 | GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400", | |
641 | ENABLE_ACLK_TOP, 0, | |
642 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
96bd6224 | 643 | |
b274bbfd CC |
644 | /* ENABLE_SCLK_TOP_MSCL */ |
645 | GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg", | |
646 | ENABLE_SCLK_TOP_MSCL, 0, 0, 0), | |
647 | ||
a5958a93 CC |
648 | /* ENABLE_SCLK_TOP_CAM1 */ |
649 | GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b", | |
650 | ENABLE_SCLK_TOP_CAM1, 7, 0, 0), | |
651 | GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b", | |
652 | ENABLE_SCLK_TOP_CAM1, 6, 0, 0), | |
653 | GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b", | |
654 | ENABLE_SCLK_TOP_CAM1, 5, 0, 0), | |
655 | GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk", | |
656 | ENABLE_SCLK_TOP_CAM1, 4, 0, 0), | |
657 | GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart", | |
658 | ENABLE_SCLK_TOP_CAM1, 2, 0, 0), | |
659 | GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b", | |
660 | ENABLE_SCLK_TOP_CAM1, 1, 0, 0), | |
661 | GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b", | |
662 | ENABLE_SCLK_TOP_CAM1, 0, 0, 0), | |
663 | ||
b2f0e5f2 CC |
664 | /* ENABLE_SCLK_TOP_DISP */ |
665 | GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp", | |
666 | "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0, | |
667 | CLK_IGNORE_UNUSED, 0), | |
668 | ||
96bd6224 | 669 | /* ENABLE_SCLK_TOP_FSYS */ |
4b801355 CC |
670 | GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100", |
671 | ENABLE_SCLK_TOP_FSYS, 7, 0, 0), | |
96bd6224 CC |
672 | GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b", |
673 | ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0), | |
674 | GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b", | |
675 | ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0), | |
676 | GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b", | |
677 | ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0), | |
4b801355 CC |
678 | GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys", |
679 | "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS, | |
680 | 3, CLK_SET_RATE_PARENT, 0), | |
681 | GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys", | |
682 | "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS, | |
683 | 1, CLK_SET_RATE_PARENT, 0), | |
684 | GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys", | |
685 | "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS, | |
686 | 0, CLK_SET_RATE_PARENT, 0), | |
96bd6224 CC |
687 | |
688 | /* ENABLE_SCLK_TOP_PERIC */ | |
689 | GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b", | |
690 | ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0), | |
691 | GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b", | |
692 | ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0), | |
23236496 CC |
693 | GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif", |
694 | ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0), | |
695 | GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1", | |
696 | ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0), | |
697 | GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1", | |
698 | ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0), | |
96bd6224 CC |
699 | GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2", |
700 | ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0), | |
701 | GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1", | |
702 | ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0), | |
703 | GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0", | |
704 | ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0), | |
705 | GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b", | |
706 | ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0), | |
707 | GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b", | |
708 | ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0), | |
709 | GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b", | |
710 | ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0), | |
23236496 CC |
711 | |
712 | /* MUX_ENABLE_TOP_PERIC1 */ | |
713 | GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus", | |
714 | MUX_ENABLE_TOP_PERIC1, 16, 0, 0), | |
715 | GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1", | |
716 | MUX_ENABLE_TOP_PERIC1, 4, 0, 0), | |
717 | GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0", | |
718 | MUX_ENABLE_TOP_PERIC1, 0, 0, 0), | |
96bd6224 CC |
719 | }; |
720 | ||
721 | /* | |
722 | * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL | |
723 | * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL | |
724 | */ | |
725 | static struct samsung_pll_rate_table exynos5443_pll_rates[] = { | |
726 | PLL_35XX_RATE(2500000000U, 625, 6, 0), | |
727 | PLL_35XX_RATE(2400000000U, 500, 5, 0), | |
728 | PLL_35XX_RATE(2300000000U, 575, 6, 0), | |
729 | PLL_35XX_RATE(2200000000U, 550, 6, 0), | |
730 | PLL_35XX_RATE(2100000000U, 350, 4, 0), | |
731 | PLL_35XX_RATE(2000000000U, 500, 6, 0), | |
732 | PLL_35XX_RATE(1900000000U, 475, 6, 0), | |
733 | PLL_35XX_RATE(1800000000U, 375, 5, 0), | |
734 | PLL_35XX_RATE(1700000000U, 425, 6, 0), | |
735 | PLL_35XX_RATE(1600000000U, 400, 6, 0), | |
736 | PLL_35XX_RATE(1500000000U, 250, 4, 0), | |
737 | PLL_35XX_RATE(1400000000U, 350, 6, 0), | |
738 | PLL_35XX_RATE(1332000000U, 222, 4, 0), | |
739 | PLL_35XX_RATE(1300000000U, 325, 6, 0), | |
740 | PLL_35XX_RATE(1200000000U, 500, 5, 1), | |
741 | PLL_35XX_RATE(1100000000U, 550, 6, 1), | |
742 | PLL_35XX_RATE(1086000000U, 362, 4, 1), | |
743 | PLL_35XX_RATE(1066000000U, 533, 6, 1), | |
744 | PLL_35XX_RATE(1000000000U, 500, 6, 1), | |
745 | PLL_35XX_RATE(933000000U, 311, 4, 1), | |
746 | PLL_35XX_RATE(921000000U, 307, 4, 1), | |
747 | PLL_35XX_RATE(900000000U, 375, 5, 1), | |
748 | PLL_35XX_RATE(825000000U, 275, 4, 1), | |
749 | PLL_35XX_RATE(800000000U, 400, 6, 1), | |
750 | PLL_35XX_RATE(733000000U, 733, 12, 1), | |
751 | PLL_35XX_RATE(700000000U, 360, 6, 1), | |
752 | PLL_35XX_RATE(667000000U, 222, 4, 1), | |
753 | PLL_35XX_RATE(633000000U, 211, 4, 1), | |
754 | PLL_35XX_RATE(600000000U, 500, 5, 2), | |
755 | PLL_35XX_RATE(552000000U, 460, 5, 2), | |
756 | PLL_35XX_RATE(550000000U, 550, 6, 2), | |
757 | PLL_35XX_RATE(543000000U, 362, 4, 2), | |
758 | PLL_35XX_RATE(533000000U, 533, 6, 2), | |
759 | PLL_35XX_RATE(500000000U, 500, 6, 2), | |
760 | PLL_35XX_RATE(444000000U, 370, 5, 2), | |
761 | PLL_35XX_RATE(420000000U, 350, 5, 2), | |
762 | PLL_35XX_RATE(400000000U, 400, 6, 2), | |
763 | PLL_35XX_RATE(350000000U, 360, 6, 2), | |
764 | PLL_35XX_RATE(333000000U, 222, 4, 2), | |
765 | PLL_35XX_RATE(300000000U, 500, 5, 3), | |
766 | PLL_35XX_RATE(266000000U, 532, 6, 3), | |
767 | PLL_35XX_RATE(200000000U, 400, 6, 3), | |
768 | PLL_35XX_RATE(166000000U, 332, 6, 3), | |
769 | PLL_35XX_RATE(160000000U, 320, 6, 3), | |
770 | PLL_35XX_RATE(133000000U, 552, 6, 4), | |
771 | PLL_35XX_RATE(100000000U, 400, 6, 4), | |
772 | { /* sentinel */ } | |
773 | }; | |
774 | ||
775 | /* AUD_PLL */ | |
776 | static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = { | |
777 | PLL_36XX_RATE(400000000U, 200, 3, 2, 0), | |
778 | PLL_36XX_RATE(393216000U, 197, 3, 2, -25690), | |
779 | PLL_36XX_RATE(384000000U, 128, 2, 2, 0), | |
780 | PLL_36XX_RATE(368640000U, 246, 4, 2, -15729), | |
781 | PLL_36XX_RATE(361507200U, 181, 3, 2, -16148), | |
782 | PLL_36XX_RATE(338688000U, 113, 2, 2, -6816), | |
783 | PLL_36XX_RATE(294912000U, 98, 1, 3, 19923), | |
784 | PLL_36XX_RATE(288000000U, 96, 1, 3, 0), | |
785 | PLL_36XX_RATE(252000000U, 84, 1, 3, 0), | |
786 | { /* sentinel */ } | |
787 | }; | |
788 | ||
789 | static struct samsung_pll_clock top_pll_clks[] __initdata = { | |
790 | PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk", | |
791 | ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates), | |
792 | PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", | |
793 | AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates), | |
794 | }; | |
795 | ||
796 | static struct samsung_cmu_info top_cmu_info __initdata = { | |
797 | .pll_clks = top_pll_clks, | |
798 | .nr_pll_clks = ARRAY_SIZE(top_pll_clks), | |
799 | .mux_clks = top_mux_clks, | |
800 | .nr_mux_clks = ARRAY_SIZE(top_mux_clks), | |
801 | .div_clks = top_div_clks, | |
802 | .nr_div_clks = ARRAY_SIZE(top_div_clks), | |
803 | .gate_clks = top_gate_clks, | |
804 | .nr_gate_clks = ARRAY_SIZE(top_gate_clks), | |
23236496 CC |
805 | .fixed_clks = top_fixed_clks, |
806 | .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks), | |
56bcf3f3 CC |
807 | .fixed_factor_clks = top_fixed_factor_clks, |
808 | .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), | |
96bd6224 CC |
809 | .nr_clk_ids = TOP_NR_CLK, |
810 | .clk_regs = top_clk_regs, | |
811 | .nr_clk_regs = ARRAY_SIZE(top_clk_regs), | |
812 | }; | |
813 | ||
814 | static void __init exynos5433_cmu_top_init(struct device_node *np) | |
815 | { | |
816 | samsung_cmu_register_one(np, &top_cmu_info); | |
817 | } | |
818 | CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top", | |
819 | exynos5433_cmu_top_init); | |
820 | ||
821 | /* | |
822 | * Register offset definitions for CMU_CPIF | |
823 | */ | |
824 | #define MPHY_PLL_LOCK 0x0000 | |
825 | #define MPHY_PLL_CON0 0x0100 | |
826 | #define MPHY_PLL_CON1 0x0104 | |
827 | #define MPHY_PLL_FREQ_DET 0x010c | |
828 | #define MUX_SEL_CPIF0 0x0200 | |
829 | #define DIV_CPIF 0x0600 | |
830 | #define ENABLE_SCLK_CPIF 0x0a00 | |
831 | ||
832 | static unsigned long cpif_clk_regs[] __initdata = { | |
833 | MPHY_PLL_LOCK, | |
834 | MPHY_PLL_CON0, | |
835 | MPHY_PLL_CON1, | |
836 | MPHY_PLL_FREQ_DET, | |
837 | MUX_SEL_CPIF0, | |
838 | ENABLE_SCLK_CPIF, | |
839 | }; | |
840 | ||
841 | /* list of all parent clock list */ | |
842 | PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", }; | |
843 | ||
844 | static struct samsung_pll_clock cpif_pll_clks[] __initdata = { | |
845 | PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk", | |
846 | MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates), | |
847 | }; | |
848 | ||
849 | static struct samsung_mux_clock cpif_mux_clks[] __initdata = { | |
850 | /* MUX_SEL_CPIF0 */ | |
851 | MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0, | |
852 | 0, 1), | |
853 | }; | |
854 | ||
855 | static struct samsung_div_clock cpif_div_clks[] __initdata = { | |
856 | /* DIV_CPIF */ | |
857 | DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF, | |
858 | 0, 6), | |
859 | }; | |
860 | ||
861 | static struct samsung_gate_clock cpif_gate_clks[] __initdata = { | |
862 | /* ENABLE_SCLK_CPIF */ | |
863 | GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll", | |
864 | ENABLE_SCLK_CPIF, 9, 0, 0), | |
865 | GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy", | |
866 | ENABLE_SCLK_CPIF, 4, 0, 0), | |
867 | }; | |
868 | ||
869 | static struct samsung_cmu_info cpif_cmu_info __initdata = { | |
870 | .pll_clks = cpif_pll_clks, | |
871 | .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks), | |
872 | .mux_clks = cpif_mux_clks, | |
873 | .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks), | |
874 | .div_clks = cpif_div_clks, | |
875 | .nr_div_clks = ARRAY_SIZE(cpif_div_clks), | |
876 | .gate_clks = cpif_gate_clks, | |
877 | .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks), | |
878 | .nr_clk_ids = CPIF_NR_CLK, | |
879 | .clk_regs = cpif_clk_regs, | |
880 | .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs), | |
881 | }; | |
882 | ||
883 | static void __init exynos5433_cmu_cpif_init(struct device_node *np) | |
884 | { | |
885 | samsung_cmu_register_one(np, &cpif_cmu_info); | |
886 | } | |
887 | CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif", | |
888 | exynos5433_cmu_cpif_init); | |
889 | ||
890 | /* | |
891 | * Register offset definitions for CMU_MIF | |
892 | */ | |
893 | #define MEM0_PLL_LOCK 0x0000 | |
894 | #define MEM1_PLL_LOCK 0x0004 | |
895 | #define BUS_PLL_LOCK 0x0008 | |
896 | #define MFC_PLL_LOCK 0x000c | |
897 | #define MEM0_PLL_CON0 0x0100 | |
898 | #define MEM0_PLL_CON1 0x0104 | |
899 | #define MEM0_PLL_FREQ_DET 0x010c | |
900 | #define MEM1_PLL_CON0 0x0110 | |
901 | #define MEM1_PLL_CON1 0x0114 | |
902 | #define MEM1_PLL_FREQ_DET 0x011c | |
903 | #define BUS_PLL_CON0 0x0120 | |
904 | #define BUS_PLL_CON1 0x0124 | |
905 | #define BUS_PLL_FREQ_DET 0x012c | |
906 | #define MFC_PLL_CON0 0x0130 | |
907 | #define MFC_PLL_CON1 0x0134 | |
908 | #define MFC_PLL_FREQ_DET 0x013c | |
06d2f9df CC |
909 | #define MUX_SEL_MIF0 0x0200 |
910 | #define MUX_SEL_MIF1 0x0204 | |
911 | #define MUX_SEL_MIF2 0x0208 | |
912 | #define MUX_SEL_MIF3 0x020c | |
913 | #define MUX_SEL_MIF4 0x0210 | |
914 | #define MUX_SEL_MIF5 0x0214 | |
915 | #define MUX_SEL_MIF6 0x0218 | |
916 | #define MUX_SEL_MIF7 0x021c | |
917 | #define MUX_ENABLE_MIF0 0x0300 | |
918 | #define MUX_ENABLE_MIF1 0x0304 | |
919 | #define MUX_ENABLE_MIF2 0x0308 | |
920 | #define MUX_ENABLE_MIF3 0x030c | |
921 | #define MUX_ENABLE_MIF4 0x0310 | |
922 | #define MUX_ENABLE_MIF5 0x0314 | |
923 | #define MUX_ENABLE_MIF6 0x0318 | |
924 | #define MUX_ENABLE_MIF7 0x031c | |
925 | #define MUX_STAT_MIF0 0x0400 | |
926 | #define MUX_STAT_MIF1 0x0404 | |
927 | #define MUX_STAT_MIF2 0x0408 | |
928 | #define MUX_STAT_MIF3 0x040c | |
929 | #define MUX_STAT_MIF4 0x0410 | |
930 | #define MUX_STAT_MIF5 0x0414 | |
931 | #define MUX_STAT_MIF6 0x0418 | |
932 | #define MUX_STAT_MIF7 0x041c | |
933 | #define DIV_MIF1 0x0604 | |
934 | #define DIV_MIF2 0x0608 | |
935 | #define DIV_MIF3 0x060c | |
936 | #define DIV_MIF4 0x0610 | |
937 | #define DIV_MIF5 0x0614 | |
938 | #define DIV_MIF_PLL_FREQ_DET 0x0618 | |
939 | #define DIV_STAT_MIF1 0x0704 | |
940 | #define DIV_STAT_MIF2 0x0708 | |
941 | #define DIV_STAT_MIF3 0x070c | |
942 | #define DIV_STAT_MIF4 0x0710 | |
943 | #define DIV_STAT_MIF5 0x0714 | |
944 | #define DIV_STAT_MIF_PLL_FREQ_DET 0x0718 | |
945 | #define ENABLE_ACLK_MIF0 0x0800 | |
946 | #define ENABLE_ACLK_MIF1 0x0804 | |
947 | #define ENABLE_ACLK_MIF2 0x0808 | |
948 | #define ENABLE_ACLK_MIF3 0x080c | |
949 | #define ENABLE_PCLK_MIF 0x0900 | |
950 | #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904 | |
951 | #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908 | |
952 | #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c | |
953 | #define ENABLE_PCLK_MIF_SECURE_RTC 0x0910 | |
954 | #define ENABLE_SCLK_MIF 0x0a00 | |
955 | #define ENABLE_IP_MIF0 0x0b00 | |
956 | #define ENABLE_IP_MIF1 0x0b04 | |
957 | #define ENABLE_IP_MIF2 0x0b08 | |
958 | #define ENABLE_IP_MIF3 0x0b0c | |
959 | #define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10 | |
960 | #define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14 | |
961 | #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18 | |
962 | #define ENABLE_IP_MIF_SECURE_RTC 0x0b1c | |
963 | #define CLKOUT_CMU_MIF 0x0c00 | |
964 | #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04 | |
965 | #define DREX_FREQ_CTRL0 0x1000 | |
966 | #define DREX_FREQ_CTRL1 0x1004 | |
967 | #define PAUSE 0x1008 | |
968 | #define DDRPHY_LOCK_CTRL 0x100c | |
96bd6224 CC |
969 | |
970 | static unsigned long mif_clk_regs[] __initdata = { | |
971 | MEM0_PLL_LOCK, | |
972 | MEM1_PLL_LOCK, | |
973 | BUS_PLL_LOCK, | |
974 | MFC_PLL_LOCK, | |
975 | MEM0_PLL_CON0, | |
976 | MEM0_PLL_CON1, | |
977 | MEM0_PLL_FREQ_DET, | |
978 | MEM1_PLL_CON0, | |
979 | MEM1_PLL_CON1, | |
980 | MEM1_PLL_FREQ_DET, | |
981 | BUS_PLL_CON0, | |
982 | BUS_PLL_CON1, | |
983 | BUS_PLL_FREQ_DET, | |
984 | MFC_PLL_CON0, | |
985 | MFC_PLL_CON1, | |
986 | MFC_PLL_FREQ_DET, | |
06d2f9df CC |
987 | MUX_SEL_MIF0, |
988 | MUX_SEL_MIF1, | |
989 | MUX_SEL_MIF2, | |
990 | MUX_SEL_MIF3, | |
991 | MUX_SEL_MIF4, | |
992 | MUX_SEL_MIF5, | |
993 | MUX_SEL_MIF6, | |
994 | MUX_SEL_MIF7, | |
995 | MUX_ENABLE_MIF0, | |
996 | MUX_ENABLE_MIF1, | |
997 | MUX_ENABLE_MIF2, | |
998 | MUX_ENABLE_MIF3, | |
999 | MUX_ENABLE_MIF4, | |
1000 | MUX_ENABLE_MIF5, | |
1001 | MUX_ENABLE_MIF6, | |
1002 | MUX_ENABLE_MIF7, | |
1003 | MUX_STAT_MIF0, | |
1004 | MUX_STAT_MIF1, | |
1005 | MUX_STAT_MIF2, | |
1006 | MUX_STAT_MIF3, | |
1007 | MUX_STAT_MIF4, | |
1008 | MUX_STAT_MIF5, | |
1009 | MUX_STAT_MIF6, | |
1010 | MUX_STAT_MIF7, | |
1011 | DIV_MIF1, | |
1012 | DIV_MIF2, | |
1013 | DIV_MIF3, | |
1014 | DIV_MIF4, | |
1015 | DIV_MIF5, | |
1016 | DIV_MIF_PLL_FREQ_DET, | |
1017 | DIV_STAT_MIF1, | |
1018 | DIV_STAT_MIF2, | |
1019 | DIV_STAT_MIF3, | |
1020 | DIV_STAT_MIF4, | |
1021 | DIV_STAT_MIF5, | |
1022 | DIV_STAT_MIF_PLL_FREQ_DET, | |
1023 | ENABLE_ACLK_MIF0, | |
1024 | ENABLE_ACLK_MIF1, | |
1025 | ENABLE_ACLK_MIF2, | |
1026 | ENABLE_ACLK_MIF3, | |
1027 | ENABLE_PCLK_MIF, | |
1028 | ENABLE_PCLK_MIF_SECURE_DREX0_TZ, | |
1029 | ENABLE_PCLK_MIF_SECURE_DREX1_TZ, | |
1030 | ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, | |
1031 | ENABLE_PCLK_MIF_SECURE_RTC, | |
1032 | ENABLE_SCLK_MIF, | |
1033 | ENABLE_IP_MIF0, | |
1034 | ENABLE_IP_MIF1, | |
1035 | ENABLE_IP_MIF2, | |
1036 | ENABLE_IP_MIF3, | |
1037 | ENABLE_IP_MIF_SECURE_DREX0_TZ, | |
1038 | ENABLE_IP_MIF_SECURE_DREX1_TZ, | |
1039 | ENABLE_IP_MIF_SECURE_MONOTONIC_CNT, | |
1040 | ENABLE_IP_MIF_SECURE_RTC, | |
1041 | CLKOUT_CMU_MIF, | |
1042 | CLKOUT_CMU_MIF_DIV_STAT, | |
1043 | DREX_FREQ_CTRL0, | |
1044 | DREX_FREQ_CTRL1, | |
1045 | PAUSE, | |
1046 | DDRPHY_LOCK_CTRL, | |
96bd6224 CC |
1047 | }; |
1048 | ||
1049 | static struct samsung_pll_clock mif_pll_clks[] __initdata = { | |
1050 | PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk", | |
1051 | MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates), | |
1052 | PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk", | |
1053 | MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates), | |
1054 | PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk", | |
1055 | BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates), | |
1056 | PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk", | |
1057 | MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates), | |
1058 | }; | |
1059 | ||
06d2f9df CC |
1060 | /* list of all parent clock list */ |
1061 | PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", }; | |
1062 | PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", }; | |
1063 | PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", }; | |
1064 | PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", }; | |
1065 | PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", }; | |
1066 | PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", }; | |
1067 | PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", }; | |
1068 | PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", }; | |
1069 | ||
1070 | PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", }; | |
1071 | PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", }; | |
1072 | PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", }; | |
1073 | PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", }; | |
1074 | ||
1075 | PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", }; | |
1076 | PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",}; | |
1077 | ||
1078 | PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a", | |
1079 | "mout_bus_pll_div2", }; | |
1080 | PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", }; | |
1081 | ||
1082 | PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b", | |
1083 | "sclk_mphy_pll", }; | |
1084 | PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a", | |
1085 | "mout_mfc_pll_div2", }; | |
1086 | PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", }; | |
1087 | PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b", | |
1088 | "sclk_mphy_pll", }; | |
1089 | PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a", | |
1090 | "mout_mfc_pll_div2", }; | |
1091 | ||
1092 | PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b", | |
1093 | "sclk_mphy_pll", }; | |
1094 | PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a", | |
1095 | "mout_mfc_pll_div2", }; | |
1096 | PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", }; | |
1097 | PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", }; | |
1098 | PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", }; | |
1099 | ||
1100 | PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", }; | |
1101 | PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" }; | |
1102 | ||
1103 | PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b", | |
1104 | "sclk_mphy_pll", }; | |
1105 | PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a", | |
1106 | "mout_mfc_pll_div2", }; | |
1107 | PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", }; | |
1108 | PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",}; | |
1109 | ||
1110 | static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = { | |
1111 | /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */ | |
1112 | FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0), | |
1113 | FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0), | |
1114 | FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0), | |
1115 | FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0), | |
1116 | }; | |
1117 | ||
1118 | static struct samsung_mux_clock mif_mux_clks[] __initdata = { | |
1119 | /* MUX_SEL_MIF0 */ | |
1120 | MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p, | |
1121 | MUX_SEL_MIF0, 28, 1), | |
1122 | MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p, | |
1123 | MUX_SEL_MIF0, 24, 1), | |
1124 | MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p, | |
1125 | MUX_SEL_MIF0, 20, 1), | |
1126 | MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p, | |
1127 | MUX_SEL_MIF0, 16, 1), | |
1128 | MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0, | |
1129 | 12, 1), | |
1130 | MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0, | |
1131 | 8, 1), | |
1132 | MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0, | |
1133 | 4, 1), | |
1134 | MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0, | |
1135 | 0, 1), | |
1136 | ||
1137 | /* MUX_SEL_MIF1 */ | |
1138 | MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p, | |
1139 | MUX_SEL_MIF1, 24, 1), | |
1140 | MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p, | |
1141 | MUX_SEL_MIF1, 20, 1), | |
1142 | MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p, | |
1143 | MUX_SEL_MIF1, 16, 1), | |
1144 | MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p, | |
1145 | MUX_SEL_MIF1, 12, 1), | |
1146 | MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p, | |
1147 | MUX_SEL_MIF1, 8, 1), | |
1148 | MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p, | |
1149 | MUX_SEL_MIF1, 4, 1), | |
1150 | ||
1151 | /* MUX_SEL_MIF2 */ | |
1152 | MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200", | |
1153 | mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1), | |
1154 | MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400", | |
1155 | mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1), | |
1156 | ||
1157 | /* MUX_SEL_MIF3 */ | |
1158 | MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b", | |
1159 | mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1), | |
1160 | MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a", | |
1161 | mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1), | |
1162 | ||
1163 | /* MUX_SEL_MIF4 */ | |
1164 | MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c", | |
1165 | mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1), | |
1166 | MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b", | |
1167 | mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1), | |
1168 | MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a", | |
1169 | mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1), | |
1170 | MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c", | |
1171 | mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1), | |
1172 | MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b", | |
1173 | mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1), | |
1174 | MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a", | |
1175 | mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1), | |
1176 | ||
1177 | /* MUX_SEL_MIF5 */ | |
1178 | MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c", | |
1179 | mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1), | |
1180 | MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b", | |
1181 | mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1), | |
1182 | MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a", | |
1183 | mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1), | |
1184 | MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p, | |
1185 | MUX_SEL_MIF5, 8, 1), | |
1186 | MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p, | |
1187 | MUX_SEL_MIF5, 4, 1), | |
1188 | MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p, | |
1189 | MUX_SEL_MIF5, 0, 1), | |
1190 | ||
1191 | /* MUX_SEL_MIF6 */ | |
1192 | MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p, | |
1193 | MUX_SEL_MIF6, 8, 1), | |
1194 | MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p, | |
1195 | MUX_SEL_MIF6, 4, 1), | |
1196 | MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p, | |
1197 | MUX_SEL_MIF6, 0, 1), | |
1198 | ||
1199 | /* MUX_SEL_MIF7 */ | |
1200 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c", | |
1201 | mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1), | |
1202 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b", | |
1203 | mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1), | |
1204 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a", | |
1205 | mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1), | |
1206 | MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p, | |
1207 | MUX_SEL_MIF7, 8, 1), | |
1208 | MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p, | |
1209 | MUX_SEL_MIF7, 4, 1), | |
1210 | MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p, | |
1211 | MUX_SEL_MIF7, 0, 1), | |
1212 | }; | |
1213 | ||
1214 | static struct samsung_div_clock mif_div_clks[] __initdata = { | |
1215 | /* DIV_MIF1 */ | |
1216 | DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy", | |
1217 | DIV_MIF1, 16, 2), | |
1218 | DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1, | |
1219 | 12, 2), | |
1220 | DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1, | |
1221 | 8, 2), | |
1222 | DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1, | |
1223 | 4, 4), | |
1224 | ||
1225 | /* DIV_MIF2 */ | |
1226 | DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2", | |
1227 | DIV_MIF2, 20, 3), | |
1228 | DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre", | |
1229 | DIV_MIF2, 16, 4), | |
1230 | DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre", | |
1231 | DIV_MIF2, 12, 4), | |
1232 | DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200", | |
1233 | "mout_aclk_mifnm_200", DIV_MIF2, 8, 3), | |
1234 | DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400", | |
1235 | DIV_MIF2, 4, 2), | |
1236 | DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400", | |
1237 | DIV_MIF2, 0, 3), | |
1238 | ||
1239 | /* DIV_MIF3 */ | |
1240 | DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre", | |
1241 | DIV_MIF3, 16, 4), | |
1242 | DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b", | |
1243 | DIV_MIF3, 4, 3), | |
1244 | DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200", | |
1245 | DIV_MIF3, 0, 3), | |
1246 | ||
1247 | /* DIV_MIF4 */ | |
1248 | DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c", | |
1249 | DIV_MIF4, 24, 4), | |
1250 | DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk", | |
1251 | "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4), | |
1252 | DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c", | |
1253 | DIV_MIF4, 16, 4), | |
1254 | DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c", | |
1255 | DIV_MIF4, 12, 4), | |
1256 | DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk", | |
1257 | "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4), | |
1258 | DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk", | |
1259 | "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4), | |
1260 | DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk", | |
1261 | "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4), | |
1262 | ||
1263 | /* DIV_MIF5 */ | |
1264 | DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5, | |
1265 | 0, 3), | |
1266 | }; | |
1267 | ||
1268 | static struct samsung_gate_clock mif_gate_clks[] __initdata = { | |
1269 | /* ENABLE_ACLK_MIF0 */ | |
1270 | GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0, | |
1271 | 19, CLK_IGNORE_UNUSED, 0), | |
1272 | GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0, | |
1273 | 18, CLK_IGNORE_UNUSED, 0), | |
1274 | GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0, | |
1275 | 17, CLK_IGNORE_UNUSED, 0), | |
1276 | GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0, | |
1277 | 16, CLK_IGNORE_UNUSED, 0), | |
1278 | GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0, | |
1279 | 15, CLK_IGNORE_UNUSED, 0), | |
1280 | GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0, | |
1281 | 14, CLK_IGNORE_UNUSED, 0), | |
1282 | GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1", | |
1283 | ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0), | |
1284 | GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0", | |
1285 | ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0), | |
1286 | GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1", | |
1287 | ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0), | |
1288 | GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0", | |
1289 | ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0), | |
1290 | GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1", | |
1291 | ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0), | |
1292 | GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0", | |
1293 | ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0), | |
1294 | GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1", | |
1295 | ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0), | |
1296 | GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0", | |
1297 | ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0), | |
1298 | GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1", | |
1299 | ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0), | |
1300 | GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0", | |
1301 | ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0), | |
1302 | GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1", | |
1303 | ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0), | |
1304 | GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0", | |
1305 | ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0), | |
1306 | GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1", | |
1307 | ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0), | |
1308 | GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0", | |
1309 | ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0), | |
1310 | ||
1311 | /* ENABLE_ACLK_MIF1 */ | |
1312 | GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem", | |
1313 | "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28, | |
1314 | CLK_IGNORE_UNUSED, 0), | |
1315 | GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci", | |
1316 | "div_aclk_mif_200", ENABLE_ACLK_MIF1, | |
1317 | 27, CLK_IGNORE_UNUSED, 0), | |
1318 | GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci", | |
1319 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, | |
1320 | 26, CLK_IGNORE_UNUSED, 0), | |
1321 | GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1", | |
1322 | "div_aclk_mifnm_200", ENABLE_ACLK_MIF1, | |
1323 | 25, CLK_IGNORE_UNUSED, 0), | |
1324 | GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1", | |
1325 | "div_aclk_drex1", ENABLE_ACLK_MIF1, | |
1326 | 24, CLK_IGNORE_UNUSED, 0), | |
1327 | GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0", | |
1328 | "div_aclk_mifnm_200", ENABLE_ACLK_MIF1, | |
1329 | 23, CLK_IGNORE_UNUSED, 0), | |
1330 | GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0", | |
1331 | "div_aclk_drex0", ENABLE_ACLK_MIF1, | |
1332 | 22, CLK_IGNORE_UNUSED, 0), | |
1333 | GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3", | |
1334 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, | |
1335 | 21, CLK_IGNORE_UNUSED, 0), | |
1336 | GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3", | |
1337 | "div_aclk_drex1", ENABLE_ACLK_MIF1, | |
1338 | 20, CLK_IGNORE_UNUSED, 0), | |
1339 | GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1", | |
1340 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, | |
1341 | 19, CLK_IGNORE_UNUSED, 0), | |
1342 | GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1", | |
1343 | "div_aclk_drex1", ENABLE_ACLK_MIF1, | |
1344 | 18, CLK_IGNORE_UNUSED, 0), | |
1345 | GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0", | |
1346 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, | |
1347 | 17, CLK_IGNORE_UNUSED, 0), | |
1348 | GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0", | |
1349 | "div_aclk_drex1", ENABLE_ACLK_MIF1, | |
1350 | 16, CLK_IGNORE_UNUSED, 0), | |
1351 | GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3", | |
1352 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, | |
1353 | 15, CLK_IGNORE_UNUSED, 0), | |
1354 | GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3", | |
1355 | "div_aclk_drex0", ENABLE_ACLK_MIF1, | |
1356 | 14, CLK_IGNORE_UNUSED, 0), | |
1357 | GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1", | |
1358 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, | |
1359 | 13, CLK_IGNORE_UNUSED, 0), | |
1360 | GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1", | |
1361 | "div_aclk_drex0", ENABLE_ACLK_MIF1, | |
1362 | 12, CLK_IGNORE_UNUSED, 0), | |
1363 | GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0", | |
1364 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, | |
1365 | 11, CLK_IGNORE_UNUSED, 0), | |
1366 | GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0", | |
1367 | "div_aclk_drex0", ENABLE_ACLK_MIF1, | |
1368 | 10, CLK_IGNORE_UNUSED, 0), | |
1369 | GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133", | |
1370 | ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0), | |
1371 | GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133", | |
1372 | ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0), | |
1373 | GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133", | |
1374 | ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0), | |
1375 | GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400", | |
1376 | ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0), | |
1377 | GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200", | |
1378 | ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0), | |
1379 | GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133", | |
1380 | ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0), | |
1381 | GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200", | |
1382 | ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0), | |
1383 | GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133", | |
1384 | ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0), | |
1385 | GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400", | |
1386 | ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0), | |
1387 | GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1, | |
1388 | 0, CLK_IGNORE_UNUSED, 0), | |
1389 | ||
1390 | /* ENABLE_ACLK_MIF2 */ | |
1391 | GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266", | |
1392 | ENABLE_ACLK_MIF2, 20, 0, 0), | |
1393 | GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1", | |
1394 | ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0), | |
1395 | GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1", | |
1396 | ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0), | |
1397 | GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1", | |
1398 | ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0), | |
1399 | GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0", | |
1400 | ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0), | |
1401 | GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0", | |
1402 | ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0), | |
1403 | GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0", | |
1404 | ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0), | |
1405 | GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx", | |
1406 | "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7, | |
1407 | CLK_IGNORE_UNUSED, 0), | |
1408 | GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci", | |
1409 | "div_aclk_mif_400", ENABLE_ACLK_MIF2, | |
1410 | 5, CLK_IGNORE_UNUSED, 0), | |
1411 | GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400", | |
1412 | ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0), | |
1413 | GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d", | |
1414 | "div_aclk_mif_200", ENABLE_ACLK_MIF2, | |
1415 | 3, CLK_IGNORE_UNUSED, 0), | |
1416 | GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys", | |
1417 | "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0), | |
1418 | ||
1419 | /* ENABLE_ACLK_MIF3 */ | |
1420 | GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400", | |
1421 | ENABLE_ACLK_MIF3, 4, | |
1422 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), | |
1423 | GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333", | |
1424 | ENABLE_ACLK_MIF3, 1, | |
1425 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), | |
1426 | GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200", | |
1427 | ENABLE_ACLK_MIF3, 0, | |
1428 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), | |
1429 | ||
1430 | /* ENABLE_PCLK_MIF */ | |
1431 | GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1", | |
1432 | ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0), | |
1433 | GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1", | |
1434 | ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0), | |
1435 | GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1", | |
1436 | ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0), | |
1437 | GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0", | |
1438 | ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0), | |
1439 | GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0", | |
1440 | ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0), | |
1441 | GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0", | |
1442 | ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0), | |
1443 | GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci", | |
1444 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 21, | |
1445 | CLK_IGNORE_UNUSED, 0), | |
1446 | GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133", | |
1447 | ENABLE_PCLK_MIF, 19, 0, 0), | |
1448 | GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133", | |
1449 | ENABLE_PCLK_MIF, 18, 0, 0), | |
1450 | GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3", | |
1451 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0), | |
1452 | GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1", | |
1453 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0), | |
1454 | GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0", | |
1455 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0), | |
1456 | GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3", | |
1457 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0), | |
1458 | GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1", | |
1459 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0), | |
1460 | GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0", | |
1461 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0), | |
1462 | GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133", | |
1463 | ENABLE_PCLK_MIF, 11, 0, 0), | |
1464 | GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133", | |
1465 | ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0), | |
1466 | GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133", | |
1467 | ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0), | |
1468 | GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133", | |
1469 | ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0), | |
1470 | GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133", | |
1471 | ENABLE_PCLK_MIF, 7, 0, 0), | |
1472 | GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133", | |
1473 | ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0), | |
1474 | GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133", | |
1475 | ENABLE_PCLK_MIF, 5, 0, 0), | |
1476 | GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133", | |
1477 | ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0), | |
1478 | GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133", | |
1479 | ENABLE_PCLK_MIF, 2, 0, 0), | |
1480 | GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133", | |
1481 | ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), | |
1482 | ||
1483 | /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */ | |
1484 | GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133", | |
1485 | ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0), | |
1486 | ||
1487 | /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */ | |
1488 | GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133", | |
1489 | ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0), | |
1490 | ||
1491 | /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */ | |
1492 | GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133", | |
1493 | ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0), | |
1494 | ||
1495 | /* ENABLE_PCLK_MIF_SECURE_RTC */ | |
1496 | GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133", | |
1497 | ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0), | |
1498 | ||
1499 | /* ENABLE_SCLK_MIF */ | |
1500 | GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1", | |
1501 | ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0), | |
1502 | GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp", | |
1503 | "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF, | |
1504 | 14, CLK_IGNORE_UNUSED, 0), | |
1505 | GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0", | |
1506 | ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0), | |
1507 | GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd", | |
1508 | ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0), | |
1509 | GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp", | |
1510 | "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF, | |
1511 | 7, CLK_IGNORE_UNUSED, 0), | |
1512 | GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp", | |
1513 | "div_sclk_decon_vclk", ENABLE_SCLK_MIF, | |
1514 | 6, CLK_IGNORE_UNUSED, 0), | |
1515 | GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp", | |
1516 | "div_sclk_decon_eclk", ENABLE_SCLK_MIF, | |
1517 | 5, CLK_IGNORE_UNUSED, 0), | |
1518 | GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif", | |
1519 | ENABLE_SCLK_MIF, 4, | |
1520 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), | |
1521 | GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2", | |
1522 | ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0), | |
1523 | GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2", | |
1524 | ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0), | |
1525 | GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll", | |
1526 | ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0), | |
1527 | GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll", | |
1528 | ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), | |
1529 | }; | |
1530 | ||
96bd6224 CC |
1531 | static struct samsung_cmu_info mif_cmu_info __initdata = { |
1532 | .pll_clks = mif_pll_clks, | |
1533 | .nr_pll_clks = ARRAY_SIZE(mif_pll_clks), | |
06d2f9df CC |
1534 | .mux_clks = mif_mux_clks, |
1535 | .nr_mux_clks = ARRAY_SIZE(mif_mux_clks), | |
1536 | .div_clks = mif_div_clks, | |
1537 | .nr_div_clks = ARRAY_SIZE(mif_div_clks), | |
1538 | .gate_clks = mif_gate_clks, | |
1539 | .nr_gate_clks = ARRAY_SIZE(mif_gate_clks), | |
1540 | .fixed_factor_clks = mif_fixed_factor_clks, | |
1541 | .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks), | |
96bd6224 CC |
1542 | .nr_clk_ids = MIF_NR_CLK, |
1543 | .clk_regs = mif_clk_regs, | |
1544 | .nr_clk_regs = ARRAY_SIZE(mif_clk_regs), | |
1545 | }; | |
1546 | ||
1547 | static void __init exynos5433_cmu_mif_init(struct device_node *np) | |
1548 | { | |
1549 | samsung_cmu_register_one(np, &mif_cmu_info); | |
1550 | } | |
1551 | CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif", | |
1552 | exynos5433_cmu_mif_init); | |
1553 | ||
1554 | /* | |
1555 | * Register offset definitions for CMU_PERIC | |
1556 | */ | |
1557 | #define DIV_PERIC 0x0600 | |
d0f5de66 | 1558 | #define DIV_STAT_PERIC 0x0700 |
96bd6224 CC |
1559 | #define ENABLE_ACLK_PERIC 0x0800 |
1560 | #define ENABLE_PCLK_PERIC0 0x0900 | |
1561 | #define ENABLE_PCLK_PERIC1 0x0904 | |
1562 | #define ENABLE_SCLK_PERIC 0x0A00 | |
1563 | #define ENABLE_IP_PERIC0 0x0B00 | |
1564 | #define ENABLE_IP_PERIC1 0x0B04 | |
1565 | #define ENABLE_IP_PERIC2 0x0B08 | |
1566 | ||
1567 | static unsigned long peric_clk_regs[] __initdata = { | |
1568 | DIV_PERIC, | |
d0f5de66 | 1569 | DIV_STAT_PERIC, |
96bd6224 CC |
1570 | ENABLE_ACLK_PERIC, |
1571 | ENABLE_PCLK_PERIC0, | |
1572 | ENABLE_PCLK_PERIC1, | |
1573 | ENABLE_SCLK_PERIC, | |
1574 | ENABLE_IP_PERIC0, | |
1575 | ENABLE_IP_PERIC1, | |
1576 | ENABLE_IP_PERIC2, | |
1577 | }; | |
1578 | ||
d0f5de66 CC |
1579 | static struct samsung_div_clock peric_div_clks[] __initdata = { |
1580 | /* DIV_PERIC */ | |
1581 | DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4), | |
1582 | DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4), | |
1583 | }; | |
1584 | ||
96bd6224 | 1585 | static struct samsung_gate_clock peric_gate_clks[] __initdata = { |
d0f5de66 CC |
1586 | /* ENABLE_ACLK_PERIC */ |
1587 | GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66", | |
1588 | ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0), | |
1589 | GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66", | |
1590 | ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0), | |
1591 | GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66", | |
1592 | ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0), | |
1593 | GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66", | |
1594 | ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0), | |
1595 | ||
96bd6224 | 1596 | /* ENABLE_PCLK_PERIC0 */ |
d0f5de66 CC |
1597 | GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
1598 | 31, CLK_SET_RATE_PARENT, 0), | |
1599 | GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66", | |
1600 | ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0), | |
1601 | GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66", | |
1602 | ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0), | |
1603 | GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1604 | 28, CLK_SET_RATE_PARENT, 0), | |
1605 | GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1606 | 26, CLK_SET_RATE_PARENT, 0), | |
1607 | GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1608 | 25, CLK_SET_RATE_PARENT, 0), | |
1609 | GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1610 | 24, CLK_SET_RATE_PARENT, 0), | |
96bd6224 CC |
1611 | GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
1612 | 23, CLK_SET_RATE_PARENT, 0), | |
1613 | GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1614 | 22, CLK_SET_RATE_PARENT, 0), | |
1615 | GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1616 | 21, CLK_SET_RATE_PARENT, 0), | |
d0f5de66 CC |
1617 | GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
1618 | 20, CLK_SET_RATE_PARENT, 0), | |
1619 | GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66", | |
1620 | ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0), | |
1621 | GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66", | |
1622 | ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0), | |
1623 | GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66", | |
1624 | ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0), | |
1625 | GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66", | |
1626 | ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0), | |
1627 | GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66", | |
1628 | ENABLE_PCLK_PERIC0, 15, | |
1629 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
96bd6224 CC |
1630 | GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
1631 | 14, CLK_SET_RATE_PARENT, 0), | |
1632 | GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1633 | 13, CLK_SET_RATE_PARENT, 0), | |
1634 | GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1635 | 12, CLK_SET_RATE_PARENT, 0), | |
1636 | GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66", | |
1637 | ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0), | |
1638 | GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66", | |
1639 | ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0), | |
1640 | GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66", | |
1641 | ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0), | |
1642 | GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66", | |
1643 | ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), | |
1644 | GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1645 | 7, CLK_SET_RATE_PARENT, 0), | |
1646 | GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1647 | 6, CLK_SET_RATE_PARENT, 0), | |
1648 | GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1649 | 5, CLK_SET_RATE_PARENT, 0), | |
1650 | GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1651 | 4, CLK_SET_RATE_PARENT, 0), | |
1652 | GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1653 | 3, CLK_SET_RATE_PARENT, 0), | |
1654 | GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1655 | 2, CLK_SET_RATE_PARENT, 0), | |
1656 | GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1657 | 1, CLK_SET_RATE_PARENT, 0), | |
1658 | GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1659 | 0, CLK_SET_RATE_PARENT, 0), | |
1660 | ||
1661 | /* ENABLE_PCLK_PERIC1 */ | |
1662 | GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1, | |
1663 | 9, CLK_SET_RATE_PARENT, 0), | |
1664 | GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1, | |
1665 | 8, CLK_SET_RATE_PARENT, 0), | |
1666 | GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66", | |
1667 | ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0), | |
1668 | GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66", | |
1669 | ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0), | |
1670 | GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66", | |
1671 | ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0), | |
1672 | GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66", | |
1673 | ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0), | |
1674 | GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66", | |
1675 | ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0), | |
1676 | GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66", | |
1677 | ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0), | |
1678 | GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66", | |
1679 | ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0), | |
1680 | GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66", | |
1681 | ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0), | |
1682 | ||
1683 | /* ENABLE_SCLK_PERIC */ | |
d0f5de66 CC |
1684 | GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in", |
1685 | ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0), | |
1686 | GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in", | |
1687 | ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0), | |
96bd6224 CC |
1688 | GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC, |
1689 | 19, CLK_SET_RATE_PARENT, 0), | |
1690 | GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC, | |
1691 | 18, CLK_SET_RATE_PARENT, 0), | |
d0f5de66 CC |
1692 | GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC, |
1693 | 17, 0, 0), | |
1694 | GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC, | |
1695 | 16, 0, 0), | |
1696 | GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0), | |
1697 | GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in", | |
1698 | ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0), | |
1699 | GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in", | |
1700 | ENABLE_SCLK_PERIC, 12, | |
1701 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), | |
1702 | GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in", | |
1703 | ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), | |
1704 | GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk", | |
1705 | "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10, | |
1706 | CLK_SET_RATE_PARENT, 0), | |
1707 | GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric", | |
1708 | ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), | |
1709 | GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric", | |
1710 | ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), | |
1711 | GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric", | |
1712 | ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), | |
96bd6224 CC |
1713 | GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC, |
1714 | 5, CLK_SET_RATE_PARENT, 0), | |
1715 | GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC, | |
d0f5de66 | 1716 | 4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), |
96bd6224 CC |
1717 | GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC, |
1718 | 3, CLK_SET_RATE_PARENT, 0), | |
1719 | GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric", | |
1720 | ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), | |
1721 | GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric", | |
1722 | ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), | |
1723 | GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric", | |
1724 | ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), | |
1725 | }; | |
1726 | ||
1727 | static struct samsung_cmu_info peric_cmu_info __initdata = { | |
d0f5de66 CC |
1728 | .div_clks = peric_div_clks, |
1729 | .nr_div_clks = ARRAY_SIZE(peric_div_clks), | |
96bd6224 CC |
1730 | .gate_clks = peric_gate_clks, |
1731 | .nr_gate_clks = ARRAY_SIZE(peric_gate_clks), | |
1732 | .nr_clk_ids = PERIC_NR_CLK, | |
1733 | .clk_regs = peric_clk_regs, | |
1734 | .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), | |
1735 | }; | |
1736 | ||
1737 | static void __init exynos5433_cmu_peric_init(struct device_node *np) | |
1738 | { | |
1739 | samsung_cmu_register_one(np, &peric_cmu_info); | |
1740 | } | |
1741 | ||
1742 | CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric", | |
1743 | exynos5433_cmu_peric_init); | |
1744 | ||
1745 | /* | |
1746 | * Register offset definitions for CMU_PERIS | |
1747 | */ | |
56bcf3f3 CC |
1748 | #define ENABLE_ACLK_PERIS 0x0800 |
1749 | #define ENABLE_PCLK_PERIS 0x0900 | |
1750 | #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904 | |
1751 | #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908 | |
1752 | #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c | |
1753 | #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910 | |
1754 | #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914 | |
1755 | #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918 | |
1756 | #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c | |
1757 | #define ENABLE_SCLK_PERIS 0x0a00 | |
1758 | #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04 | |
1759 | #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08 | |
1760 | #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c | |
1761 | #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10 | |
1762 | #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14 | |
1763 | #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18 | |
1764 | #define ENABLE_IP_PERIS0 0x0b00 | |
1765 | #define ENABLE_IP_PERIS1 0x0b04 | |
1766 | #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08 | |
1767 | #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c | |
1768 | #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10 | |
1769 | #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14 | |
1770 | #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18 | |
1771 | #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c | |
1772 | #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20 | |
96bd6224 CC |
1773 | |
1774 | static unsigned long peris_clk_regs[] __initdata = { | |
1775 | ENABLE_ACLK_PERIS, | |
1776 | ENABLE_PCLK_PERIS, | |
56bcf3f3 CC |
1777 | ENABLE_PCLK_PERIS_SECURE_TZPC, |
1778 | ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, | |
1779 | ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, | |
1780 | ENABLE_PCLK_PERIS_SECURE_TOPRTC, | |
1781 | ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, | |
1782 | ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, | |
1783 | ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, | |
1784 | ENABLE_SCLK_PERIS, | |
1785 | ENABLE_SCLK_PERIS_SECURE_SECKEY, | |
1786 | ENABLE_SCLK_PERIS_SECURE_CHIPID, | |
1787 | ENABLE_SCLK_PERIS_SECURE_TOPRTC, | |
1788 | ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, | |
1789 | ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, | |
1790 | ENABLE_SCLK_PERIS_SECURE_OTP_CON, | |
1791 | ENABLE_IP_PERIS0, | |
1792 | ENABLE_IP_PERIS1, | |
1793 | ENABLE_IP_PERIS_SECURE_TZPC, | |
1794 | ENABLE_IP_PERIS_SECURE_SECKEY, | |
1795 | ENABLE_IP_PERIS_SECURE_CHIPID, | |
1796 | ENABLE_IP_PERIS_SECURE_TOPRTC, | |
1797 | ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE, | |
1798 | ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT, | |
1799 | ENABLE_IP_PERIS_SECURE_OTP_CON, | |
96bd6224 CC |
1800 | }; |
1801 | ||
1802 | static struct samsung_gate_clock peris_gate_clks[] __initdata = { | |
56bcf3f3 CC |
1803 | /* ENABLE_ACLK_PERIS */ |
1804 | GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66", | |
1805 | ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0), | |
1806 | GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66", | |
1807 | ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0), | |
1808 | GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66", | |
1809 | ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0), | |
1810 | ||
96bd6224 CC |
1811 | /* ENABLE_PCLK_PERIS */ |
1812 | GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66", | |
1813 | ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0), | |
1814 | GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66", | |
1815 | ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0), | |
1816 | GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66", | |
1817 | ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0), | |
1818 | GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66", | |
1819 | ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0), | |
1820 | GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66", | |
1821 | ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0), | |
1822 | GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66", | |
1823 | ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0), | |
1824 | GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66", | |
1825 | ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0), | |
1826 | GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66", | |
1827 | ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0), | |
1828 | GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66", | |
1829 | ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0), | |
1830 | GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66", | |
1831 | ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0), | |
56bcf3f3 CC |
1832 | |
1833 | /* ENABLE_PCLK_PERIS_SECURE_TZPC */ | |
1834 | GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66", | |
1835 | ENABLE_PCLK_PERIS_SECURE_TZPC, 12, 0, 0), | |
1836 | GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66", | |
1837 | ENABLE_PCLK_PERIS_SECURE_TZPC, 11, 0, 0), | |
1838 | GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66", | |
1839 | ENABLE_PCLK_PERIS_SECURE_TZPC, 10, 0, 0), | |
1840 | GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66", | |
1841 | ENABLE_PCLK_PERIS_SECURE_TZPC, 9, 0, 0), | |
1842 | GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66", | |
1843 | ENABLE_PCLK_PERIS_SECURE_TZPC, 8, 0, 0), | |
1844 | GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66", | |
1845 | ENABLE_PCLK_PERIS_SECURE_TZPC, 7, 0, 0), | |
1846 | GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66", | |
1847 | ENABLE_PCLK_PERIS_SECURE_TZPC, 6, 0, 0), | |
1848 | GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66", | |
1849 | ENABLE_PCLK_PERIS_SECURE_TZPC, 5, 0, 0), | |
1850 | GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66", | |
1851 | ENABLE_PCLK_PERIS_SECURE_TZPC, 4, 0, 0), | |
1852 | GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66", | |
1853 | ENABLE_PCLK_PERIS_SECURE_TZPC, 3, 0, 0), | |
1854 | GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66", | |
1855 | ENABLE_PCLK_PERIS_SECURE_TZPC, 2, 0, 0), | |
1856 | GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66", | |
1857 | ENABLE_PCLK_PERIS_SECURE_TZPC, 1, 0, 0), | |
1858 | GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66", | |
1859 | ENABLE_PCLK_PERIS_SECURE_TZPC, 0, 0, 0), | |
1860 | ||
1861 | /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */ | |
1862 | GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66", | |
1863 | ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, 0, 0), | |
1864 | ||
1865 | /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */ | |
1866 | GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66", | |
1867 | ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, 0, 0), | |
1868 | ||
1869 | /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */ | |
1870 | GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66", | |
1871 | ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0), | |
1872 | ||
1873 | /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */ | |
1874 | GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif", | |
1875 | "aclk_peris_66", | |
1876 | ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0), | |
1877 | ||
1878 | /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */ | |
1879 | GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif", | |
1880 | "aclk_peris_66", | |
1881 | ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0), | |
1882 | ||
1883 | /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */ | |
1884 | GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif", | |
1885 | "aclk_peris_66", | |
1886 | ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0), | |
1887 | ||
1888 | /* ENABLE_SCLK_PERIS */ | |
1889 | GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common", | |
1890 | ENABLE_SCLK_PERIS, 10, 0, 0), | |
1891 | GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common", | |
1892 | ENABLE_SCLK_PERIS, 4, 0, 0), | |
1893 | GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common", | |
1894 | ENABLE_SCLK_PERIS, 3, 0, 0), | |
1895 | ||
1896 | /* ENABLE_SCLK_PERIS_SECURE_SECKEY */ | |
1897 | GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common", | |
1898 | ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, 0, 0), | |
1899 | ||
1900 | /* ENABLE_SCLK_PERIS_SECURE_CHIPID */ | |
1901 | GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common", | |
1902 | ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0), | |
1903 | ||
1904 | /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */ | |
1905 | GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common", | |
1906 | ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0), | |
1907 | ||
1908 | /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */ | |
1909 | GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common", | |
1910 | ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0), | |
1911 | ||
1912 | /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */ | |
1913 | GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common", | |
1914 | ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0), | |
1915 | ||
1916 | /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */ | |
1917 | GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common", | |
1918 | ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0), | |
96bd6224 CC |
1919 | }; |
1920 | ||
1921 | static struct samsung_cmu_info peris_cmu_info __initdata = { | |
1922 | .gate_clks = peris_gate_clks, | |
1923 | .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), | |
1924 | .nr_clk_ids = PERIS_NR_CLK, | |
1925 | .clk_regs = peris_clk_regs, | |
1926 | .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), | |
1927 | }; | |
1928 | ||
1929 | static void __init exynos5433_cmu_peris_init(struct device_node *np) | |
1930 | { | |
1931 | samsung_cmu_register_one(np, &peris_cmu_info); | |
1932 | } | |
1933 | ||
1934 | CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris", | |
1935 | exynos5433_cmu_peris_init); | |
1936 | ||
1937 | /* | |
1938 | * Register offset definitions for CMU_FSYS | |
1939 | */ | |
1940 | #define MUX_SEL_FSYS0 0x0200 | |
1941 | #define MUX_SEL_FSYS1 0x0204 | |
1942 | #define MUX_SEL_FSYS2 0x0208 | |
1943 | #define MUX_SEL_FSYS3 0x020c | |
1944 | #define MUX_SEL_FSYS4 0x0210 | |
1945 | #define MUX_ENABLE_FSYS0 0x0300 | |
1946 | #define MUX_ENABLE_FSYS1 0x0304 | |
1947 | #define MUX_ENABLE_FSYS2 0x0308 | |
1948 | #define MUX_ENABLE_FSYS3 0x030c | |
1949 | #define MUX_ENABLE_FSYS4 0x0310 | |
1950 | #define MUX_STAT_FSYS0 0x0400 | |
1951 | #define MUX_STAT_FSYS1 0x0404 | |
1952 | #define MUX_STAT_FSYS2 0x0408 | |
1953 | #define MUX_STAT_FSYS3 0x040c | |
1954 | #define MUX_STAT_FSYS4 0x0410 | |
1955 | #define MUX_IGNORE_FSYS2 0x0508 | |
1956 | #define MUX_IGNORE_FSYS3 0x050c | |
1957 | #define ENABLE_ACLK_FSYS0 0x0800 | |
1958 | #define ENABLE_ACLK_FSYS1 0x0804 | |
1959 | #define ENABLE_PCLK_FSYS 0x0900 | |
1960 | #define ENABLE_SCLK_FSYS 0x0a00 | |
1961 | #define ENABLE_IP_FSYS0 0x0b00 | |
1962 | #define ENABLE_IP_FSYS1 0x0b04 | |
1963 | ||
1964 | /* list of all parent clock list */ | |
4b801355 | 1965 | PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", }; |
96bd6224 | 1966 | PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "div_aclk_fsys_200", }; |
4b801355 CC |
1967 | PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",}; |
1968 | PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",}; | |
96bd6224 CC |
1969 | PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", }; |
1970 | PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", }; | |
1971 | PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", }; | |
4b801355 CC |
1972 | PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",}; |
1973 | PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", }; | |
1974 | ||
1975 | PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p) | |
1976 | = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", }; | |
1977 | PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p) | |
1978 | = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", }; | |
1979 | PNAME(mout_phyclk_usbhost20_phy_hsic1_p) | |
1980 | = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", }; | |
1981 | PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p) | |
1982 | = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", }; | |
1983 | PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p) | |
1984 | = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", }; | |
1985 | PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p) | |
1986 | = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", }; | |
1987 | PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p) | |
1988 | = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", }; | |
1989 | PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p) | |
1990 | = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", }; | |
1991 | PNAME(mout_phyclk_ufs_rx1_symbol_user_p) | |
1992 | = { "oscclk", "phyclk_ufs_rx1_symbol_phy", }; | |
1993 | PNAME(mout_phyclk_ufs_rx0_symbol_user_p) | |
1994 | = { "oscclk", "phyclk_ufs_rx0_symbol_phy", }; | |
1995 | PNAME(mout_phyclk_ufs_tx1_symbol_user_p) | |
1996 | = { "oscclk", "phyclk_ufs_tx1_symbol_phy", }; | |
1997 | PNAME(mout_phyclk_ufs_tx0_symbol_user_p) | |
1998 | = { "oscclk", "phyclk_ufs_tx0_symbol_phy", }; | |
1999 | PNAME(mout_phyclk_lli_mphy_to_ufs_user_p) | |
2000 | = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", }; | |
2001 | PNAME(mout_sclk_mphy_p) | |
2002 | = { "mout_sclk_ufs_mphy_user", | |
2003 | "mout_phyclk_lli_mphy_to_ufs_user", }; | |
96bd6224 CC |
2004 | |
2005 | static unsigned long fsys_clk_regs[] __initdata = { | |
2006 | MUX_SEL_FSYS0, | |
2007 | MUX_SEL_FSYS1, | |
2008 | MUX_SEL_FSYS2, | |
2009 | MUX_SEL_FSYS3, | |
2010 | MUX_SEL_FSYS4, | |
2011 | MUX_ENABLE_FSYS0, | |
2012 | MUX_ENABLE_FSYS1, | |
2013 | MUX_ENABLE_FSYS2, | |
2014 | MUX_ENABLE_FSYS3, | |
2015 | MUX_ENABLE_FSYS4, | |
2016 | MUX_STAT_FSYS0, | |
2017 | MUX_STAT_FSYS1, | |
2018 | MUX_STAT_FSYS2, | |
2019 | MUX_STAT_FSYS3, | |
2020 | MUX_STAT_FSYS4, | |
2021 | MUX_IGNORE_FSYS2, | |
2022 | MUX_IGNORE_FSYS3, | |
2023 | ENABLE_ACLK_FSYS0, | |
2024 | ENABLE_ACLK_FSYS1, | |
2025 | ENABLE_PCLK_FSYS, | |
2026 | ENABLE_SCLK_FSYS, | |
2027 | ENABLE_IP_FSYS0, | |
2028 | ENABLE_IP_FSYS1, | |
2029 | }; | |
2030 | ||
4b801355 CC |
2031 | static struct samsung_fixed_rate_clock fsys_fixed_clks[] __initdata = { |
2032 | /* PHY clocks from USBDRD30_PHY */ | |
2033 | FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY, | |
2034 | "phyclk_usbdrd30_udrd30_phyclock_phy", NULL, | |
2035 | CLK_IS_ROOT, 60000000), | |
2036 | FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY, | |
2037 | "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL, | |
2038 | CLK_IS_ROOT, 125000000), | |
2039 | /* PHY clocks from USBHOST30_PHY */ | |
2040 | FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY, | |
2041 | "phyclk_usbhost30_uhost30_phyclock_phy", NULL, | |
2042 | CLK_IS_ROOT, 60000000), | |
2043 | FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY, | |
2044 | "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL, | |
2045 | CLK_IS_ROOT, 125000000), | |
2046 | /* PHY clocks from USBHOST20_PHY */ | |
2047 | FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY, | |
2048 | "phyclk_usbhost20_phy_freeclk_phy", NULL, CLK_IS_ROOT, | |
2049 | 60000000), | |
2050 | FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY, | |
2051 | "phyclk_usbhost20_phy_phyclock_phy", NULL, CLK_IS_ROOT, | |
2052 | 60000000), | |
2053 | FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY, | |
2054 | "phyclk_usbhost20_phy_clk48mohci_phy", NULL, | |
2055 | CLK_IS_ROOT, 48000000), | |
2056 | FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY, | |
2057 | "phyclk_usbhost20_phy_hsic1_phy", NULL, CLK_IS_ROOT, | |
2058 | 60000000), | |
2059 | /* PHY clocks from UFS_PHY */ | |
2060 | FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy", | |
2061 | NULL, CLK_IS_ROOT, 300000000), | |
2062 | FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy", | |
2063 | NULL, CLK_IS_ROOT, 300000000), | |
2064 | FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy", | |
2065 | NULL, CLK_IS_ROOT, 300000000), | |
2066 | FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy", | |
2067 | NULL, CLK_IS_ROOT, 300000000), | |
2068 | /* PHY clocks from LLI_PHY */ | |
2069 | FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy", | |
2070 | NULL, CLK_IS_ROOT, 26000000), | |
2071 | }; | |
2072 | ||
96bd6224 CC |
2073 | static struct samsung_mux_clock fsys_mux_clks[] __initdata = { |
2074 | /* MUX_SEL_FSYS0 */ | |
4b801355 CC |
2075 | MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user", |
2076 | mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1), | |
96bd6224 CC |
2077 | MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user", |
2078 | mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1), | |
2079 | ||
2080 | /* MUX_SEL_FSYS1 */ | |
4b801355 CC |
2081 | MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user", |
2082 | mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1), | |
2083 | MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user", | |
2084 | mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1), | |
96bd6224 CC |
2085 | MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user", |
2086 | mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1), | |
2087 | MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user", | |
2088 | mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1), | |
2089 | MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user", | |
2090 | mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1), | |
4b801355 CC |
2091 | MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user", |
2092 | mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1), | |
2093 | MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user", | |
2094 | mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1), | |
2095 | ||
2096 | /* MUX_SEL_FSYS2 */ | |
2097 | MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER, | |
2098 | "mout_phyclk_usbhost30_uhost30_pipe_pclk_user", | |
2099 | mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p, | |
2100 | MUX_SEL_FSYS2, 28, 1), | |
2101 | MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER, | |
2102 | "mout_phyclk_usbhost30_uhost30_phyclock_user", | |
2103 | mout_phyclk_usbhost30_uhost30_phyclock_user_p, | |
2104 | MUX_SEL_FSYS2, 24, 1), | |
2105 | MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER, | |
2106 | "mout_phyclk_usbhost20_phy_hsic1", | |
2107 | mout_phyclk_usbhost20_phy_hsic1_p, | |
2108 | MUX_SEL_FSYS2, 20, 1), | |
2109 | MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER, | |
2110 | "mout_phyclk_usbhost20_phy_clk48mohci_user", | |
2111 | mout_phyclk_usbhost20_phy_clk48mohci_user_p, | |
2112 | MUX_SEL_FSYS2, 16, 1), | |
2113 | MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER, | |
2114 | "mout_phyclk_usbhost20_phy_phyclock_user", | |
2115 | mout_phyclk_usbhost20_phy_phyclock_user_p, | |
2116 | MUX_SEL_FSYS2, 12, 1), | |
2117 | MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER, | |
2118 | "mout_phyclk_usbhost20_phy_freeclk_user", | |
2119 | mout_phyclk_usbhost20_phy_freeclk_user_p, | |
2120 | MUX_SEL_FSYS2, 8, 1), | |
2121 | MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER, | |
2122 | "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user", | |
2123 | mout_phyclk_usbdrd30_udrd30_pipe_pclk_p, | |
2124 | MUX_SEL_FSYS2, 4, 1), | |
2125 | MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER, | |
2126 | "mout_phyclk_usbdrd30_udrd30_phyclock_user", | |
2127 | mout_phyclk_usbdrd30_udrd30_phyclock_user_p, | |
2128 | MUX_SEL_FSYS2, 0, 1), | |
2129 | ||
2130 | /* MUX_SEL_FSYS3 */ | |
2131 | MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER, | |
2132 | "mout_phyclk_ufs_rx1_symbol_user", | |
2133 | mout_phyclk_ufs_rx1_symbol_user_p, | |
2134 | MUX_SEL_FSYS3, 16, 1), | |
2135 | MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER, | |
2136 | "mout_phyclk_ufs_rx0_symbol_user", | |
2137 | mout_phyclk_ufs_rx0_symbol_user_p, | |
2138 | MUX_SEL_FSYS3, 12, 1), | |
2139 | MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER, | |
2140 | "mout_phyclk_ufs_tx1_symbol_user", | |
2141 | mout_phyclk_ufs_tx1_symbol_user_p, | |
2142 | MUX_SEL_FSYS3, 8, 1), | |
2143 | MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER, | |
2144 | "mout_phyclk_ufs_tx0_symbol_user", | |
2145 | mout_phyclk_ufs_tx0_symbol_user_p, | |
2146 | MUX_SEL_FSYS3, 4, 1), | |
2147 | MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER, | |
2148 | "mout_phyclk_lli_mphy_to_ufs_user", | |
2149 | mout_phyclk_lli_mphy_to_ufs_user_p, | |
2150 | MUX_SEL_FSYS3, 0, 1), | |
2151 | ||
2152 | /* MUX_SEL_FSYS4 */ | |
2153 | MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p, | |
2154 | MUX_SEL_FSYS4, 0, 1), | |
96bd6224 CC |
2155 | }; |
2156 | ||
2157 | static struct samsung_gate_clock fsys_gate_clks[] __initdata = { | |
2158 | /* ENABLE_ACLK_FSYS0 */ | |
2159 | GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user", | |
2160 | ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0), | |
2161 | GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user", | |
2162 | ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0), | |
2163 | GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user", | |
2164 | ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0), | |
2165 | GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user", | |
2166 | ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0), | |
2167 | GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user", | |
2168 | ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0), | |
2169 | GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user", | |
2170 | ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0), | |
2171 | GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user", | |
2172 | ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0), | |
2173 | GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user", | |
2174 | ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0), | |
2175 | GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user", | |
2176 | ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0), | |
2177 | GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user", | |
2178 | ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0), | |
2179 | GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user", | |
2180 | ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0), | |
2181 | ||
4b801355 CC |
2182 | /* ENABLE_ACLK_FSYS1 */ |
2183 | GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user", | |
2184 | ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0), | |
2185 | GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1", | |
2186 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2187 | 26, CLK_IGNORE_UNUSED, 0), | |
2188 | GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user", | |
2189 | ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0), | |
2190 | GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user", | |
2191 | ENABLE_ACLK_FSYS1, 24, 0, 0), | |
2192 | GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1", | |
2193 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2194 | 22, CLK_IGNORE_UNUSED, 0), | |
2195 | GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user", | |
2196 | ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0), | |
2197 | GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user", | |
2198 | ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0), | |
2199 | GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30", | |
2200 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2201 | 13, 0, 0), | |
2202 | GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30", | |
2203 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2204 | 12, 0, 0), | |
2205 | GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0", | |
2206 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2207 | 11, CLK_IGNORE_UNUSED, 0), | |
2208 | GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs", | |
2209 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2210 | 10, CLK_IGNORE_UNUSED, 0), | |
2211 | GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx", | |
2212 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2213 | 9, CLK_IGNORE_UNUSED, 0), | |
2214 | GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp", | |
2215 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2216 | 8, CLK_IGNORE_UNUSED, 0), | |
2217 | GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs", | |
2218 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2219 | 7, CLK_IGNORE_UNUSED, 0), | |
2220 | GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0", | |
2221 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2222 | 6, CLK_IGNORE_UNUSED, 0), | |
2223 | GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user", | |
2224 | ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0), | |
2225 | GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user", | |
2226 | ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0), | |
2227 | GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user", | |
2228 | ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0), | |
2229 | GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user", | |
2230 | ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0), | |
2231 | GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user", | |
2232 | ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0), | |
2233 | GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user", | |
2234 | ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0), | |
2235 | ||
2236 | /* ENABLE_PCLK_FSYS */ | |
2237 | GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user", | |
2238 | ENABLE_PCLK_FSYS, 17, 0, 0), | |
2239 | GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user", | |
2240 | ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0), | |
2241 | GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user", | |
2242 | ENABLE_PCLK_FSYS, 14, 0, 0), | |
2243 | GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user", | |
2244 | ENABLE_PCLK_FSYS, 13, 0, 0), | |
2245 | GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user", | |
2246 | ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0), | |
2247 | GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user", | |
2248 | ENABLE_PCLK_FSYS, 5, 0, 0), | |
2249 | GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30", | |
2250 | "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0), | |
2251 | GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30", | |
2252 | "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0), | |
2253 | GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user", | |
2254 | ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0), | |
2255 | GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user", | |
2256 | ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0), | |
2257 | GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys", | |
2258 | "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, | |
2259 | 0, CLK_IGNORE_UNUSED, 0), | |
2260 | ||
96bd6224 | 2261 | /* ENABLE_SCLK_FSYS */ |
4b801355 CC |
2262 | GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user", |
2263 | ENABLE_SCLK_FSYS, 21, 0, 0), | |
2264 | GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK, | |
2265 | "phyclk_usbhost30_uhost30_pipe_pclk", | |
2266 | "mout_phyclk_usbhost30_uhost30_pipe_pclk_user", | |
2267 | ENABLE_SCLK_FSYS, 18, 0, 0), | |
2268 | GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK, | |
2269 | "phyclk_usbhost30_uhost30_phyclock", | |
2270 | "mout_phyclk_usbhost30_uhost30_phyclock_user", | |
2271 | ENABLE_SCLK_FSYS, 17, 0, 0), | |
2272 | GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol", | |
2273 | "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS, | |
2274 | 16, 0, 0), | |
2275 | GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol", | |
2276 | "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS, | |
2277 | 15, 0, 0), | |
2278 | GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol", | |
2279 | "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS, | |
2280 | 14, 0, 0), | |
2281 | GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol", | |
2282 | "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS, | |
2283 | 13, 0, 0), | |
2284 | GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1", | |
2285 | "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS, | |
2286 | 12, 0, 0), | |
2287 | GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI, | |
2288 | "phyclk_usbhost20_phy_clk48mohci", | |
2289 | "mout_phyclk_usbhost20_phy_clk48mohci_user", | |
2290 | ENABLE_SCLK_FSYS, 11, 0, 0), | |
2291 | GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK, | |
2292 | "phyclk_usbhost20_phy_phyclock", | |
2293 | "mout_phyclk_usbhost20_phy_phyclock_user", | |
2294 | ENABLE_SCLK_FSYS, 10, 0, 0), | |
2295 | GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK, | |
2296 | "phyclk_usbhost20_phy_freeclk", | |
2297 | "mout_phyclk_usbhost20_phy_freeclk_user", | |
2298 | ENABLE_SCLK_FSYS, 9, 0, 0), | |
2299 | GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK, | |
2300 | "phyclk_usbdrd30_udrd30_pipe_pclk", | |
2301 | "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user", | |
2302 | ENABLE_SCLK_FSYS, 8, 0, 0), | |
2303 | GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK, | |
2304 | "phyclk_usbdrd30_udrd30_phyclock", | |
2305 | "mout_phyclk_usbdrd30_udrd30_phyclock_user", | |
2306 | ENABLE_SCLK_FSYS, 7, 0, 0), | |
2307 | GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy", | |
2308 | ENABLE_SCLK_FSYS, 6, 0, 0), | |
2309 | GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user", | |
2310 | ENABLE_SCLK_FSYS, 5, 0, 0), | |
96bd6224 CC |
2311 | GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user", |
2312 | ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0), | |
2313 | GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user", | |
2314 | ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0), | |
2315 | GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user", | |
2316 | ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), | |
4b801355 CC |
2317 | GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user", |
2318 | ENABLE_SCLK_FSYS, 1, 0, 0), | |
2319 | GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user", | |
2320 | ENABLE_SCLK_FSYS, 0, 0, 0), | |
96bd6224 CC |
2321 | |
2322 | /* ENABLE_IP_FSYS0 */ | |
2323 | GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0), | |
2324 | GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0), | |
2325 | }; | |
2326 | ||
2327 | static struct samsung_cmu_info fsys_cmu_info __initdata = { | |
2328 | .mux_clks = fsys_mux_clks, | |
2329 | .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), | |
2330 | .gate_clks = fsys_gate_clks, | |
2331 | .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), | |
4b801355 CC |
2332 | .fixed_clks = fsys_fixed_clks, |
2333 | .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks), | |
96bd6224 CC |
2334 | .nr_clk_ids = FSYS_NR_CLK, |
2335 | .clk_regs = fsys_clk_regs, | |
2336 | .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), | |
2337 | }; | |
2338 | ||
2339 | static void __init exynos5433_cmu_fsys_init(struct device_node *np) | |
2340 | { | |
2341 | samsung_cmu_register_one(np, &fsys_cmu_info); | |
2342 | } | |
2343 | ||
2344 | CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys", | |
2345 | exynos5433_cmu_fsys_init); | |
a29308da CC |
2346 | |
2347 | /* | |
2348 | * Register offset definitions for CMU_G2D | |
2349 | */ | |
2350 | #define MUX_SEL_G2D0 0x0200 | |
2351 | #define MUX_SEL_ENABLE_G2D0 0x0300 | |
2352 | #define MUX_SEL_STAT_G2D0 0x0400 | |
2353 | #define DIV_G2D 0x0600 | |
2354 | #define DIV_STAT_G2D 0x0700 | |
2355 | #define DIV_ENABLE_ACLK_G2D 0x0800 | |
2356 | #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804 | |
2357 | #define DIV_ENABLE_PCLK_G2D 0x0900 | |
2358 | #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904 | |
2359 | #define DIV_ENABLE_IP_G2D0 0x0b00 | |
2360 | #define DIV_ENABLE_IP_G2D1 0x0b04 | |
2361 | #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08 | |
2362 | ||
2363 | static unsigned long g2d_clk_regs[] __initdata = { | |
2364 | MUX_SEL_G2D0, | |
2365 | MUX_SEL_ENABLE_G2D0, | |
2366 | MUX_SEL_STAT_G2D0, | |
2367 | DIV_G2D, | |
2368 | DIV_STAT_G2D, | |
2369 | DIV_ENABLE_ACLK_G2D, | |
2370 | DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, | |
2371 | DIV_ENABLE_PCLK_G2D, | |
2372 | DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, | |
2373 | DIV_ENABLE_IP_G2D0, | |
2374 | DIV_ENABLE_IP_G2D1, | |
2375 | DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D, | |
2376 | }; | |
2377 | ||
2378 | /* list of all parent clock list */ | |
2379 | PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", }; | |
2380 | PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", }; | |
2381 | ||
2382 | static struct samsung_mux_clock g2d_mux_clks[] __initdata = { | |
2383 | /* MUX_SEL_G2D0 */ | |
2384 | MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user", | |
2385 | mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1), | |
2386 | MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user", | |
2387 | mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1), | |
2388 | }; | |
2389 | ||
2390 | static struct samsung_div_clock g2d_div_clks[] __initdata = { | |
2391 | /* DIV_G2D */ | |
2392 | DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user", | |
2393 | DIV_G2D, 0, 2), | |
2394 | }; | |
2395 | ||
2396 | static struct samsung_gate_clock g2d_gate_clks[] __initdata = { | |
2397 | /* DIV_ENABLE_ACLK_G2D */ | |
2398 | GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user", | |
2399 | DIV_ENABLE_ACLK_G2D, 12, 0, 0), | |
2400 | GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user", | |
2401 | DIV_ENABLE_ACLK_G2D, 11, 0, 0), | |
2402 | GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user", | |
2403 | DIV_ENABLE_ACLK_G2D, 10, 0, 0), | |
2404 | GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user", | |
2405 | DIV_ENABLE_ACLK_G2D, 9, 0, 0), | |
2406 | GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user", | |
2407 | DIV_ENABLE_ACLK_G2D, 8, 0, 0), | |
2408 | GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx", | |
2409 | "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D, | |
2410 | 7, 0, 0), | |
2411 | GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d", | |
2412 | DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0), | |
2413 | GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d", | |
2414 | DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0), | |
2415 | GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user", | |
2416 | DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0), | |
2417 | GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d", | |
2418 | DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0), | |
2419 | GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user", | |
2420 | DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0), | |
2421 | GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user", | |
2422 | DIV_ENABLE_ACLK_G2D, 1, 0, 0), | |
2423 | GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user", | |
2424 | DIV_ENABLE_ACLK_G2D, 0, 0, 0), | |
2425 | ||
2426 | /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */ | |
2427 | GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user", | |
2428 | DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), | |
2429 | ||
2430 | /* DIV_ENABLE_PCLK_G2D */ | |
2431 | GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d", | |
2432 | DIV_ENABLE_PCLK_G2D, 7, 0, 0), | |
2433 | GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d", | |
2434 | DIV_ENABLE_PCLK_G2D, 6, 0, 0), | |
2435 | GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d", | |
2436 | DIV_ENABLE_PCLK_G2D, 5, 0, 0), | |
2437 | GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d", | |
2438 | DIV_ENABLE_PCLK_G2D, 4, 0, 0), | |
2439 | GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d", | |
2440 | DIV_ENABLE_PCLK_G2D, 3, 0, 0), | |
2441 | GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d", | |
2442 | DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0), | |
2443 | GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d", | |
2444 | DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0), | |
2445 | GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D, | |
2446 | 0, 0, 0), | |
2447 | ||
2448 | /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */ | |
2449 | GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d", | |
2450 | DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), | |
2451 | }; | |
2452 | ||
2453 | static struct samsung_cmu_info g2d_cmu_info __initdata = { | |
2454 | .mux_clks = g2d_mux_clks, | |
2455 | .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks), | |
2456 | .div_clks = g2d_div_clks, | |
2457 | .nr_div_clks = ARRAY_SIZE(g2d_div_clks), | |
2458 | .gate_clks = g2d_gate_clks, | |
2459 | .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks), | |
2460 | .nr_clk_ids = G2D_NR_CLK, | |
2461 | .clk_regs = g2d_clk_regs, | |
2462 | .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs), | |
2463 | }; | |
2464 | ||
2465 | static void __init exynos5433_cmu_g2d_init(struct device_node *np) | |
2466 | { | |
2467 | samsung_cmu_register_one(np, &g2d_cmu_info); | |
2468 | } | |
2469 | ||
2470 | CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d", | |
2471 | exynos5433_cmu_g2d_init); | |
2a1808a6 CC |
2472 | |
2473 | /* | |
2474 | * Register offset definitions for CMU_DISP | |
2475 | */ | |
2476 | #define DISP_PLL_LOCK 0x0000 | |
2477 | #define DISP_PLL_CON0 0x0100 | |
2478 | #define DISP_PLL_CON1 0x0104 | |
2479 | #define DISP_PLL_FREQ_DET 0x0108 | |
2480 | #define MUX_SEL_DISP0 0x0200 | |
2481 | #define MUX_SEL_DISP1 0x0204 | |
2482 | #define MUX_SEL_DISP2 0x0208 | |
2483 | #define MUX_SEL_DISP3 0x020c | |
2484 | #define MUX_SEL_DISP4 0x0210 | |
2485 | #define MUX_ENABLE_DISP0 0x0300 | |
2486 | #define MUX_ENABLE_DISP1 0x0304 | |
2487 | #define MUX_ENABLE_DISP2 0x0308 | |
2488 | #define MUX_ENABLE_DISP3 0x030c | |
2489 | #define MUX_ENABLE_DISP4 0x0310 | |
2490 | #define MUX_STAT_DISP0 0x0400 | |
2491 | #define MUX_STAT_DISP1 0x0404 | |
2492 | #define MUX_STAT_DISP2 0x0408 | |
2493 | #define MUX_STAT_DISP3 0x040c | |
2494 | #define MUX_STAT_DISP4 0x0410 | |
2495 | #define MUX_IGNORE_DISP2 0x0508 | |
2496 | #define DIV_DISP 0x0600 | |
2497 | #define DIV_DISP_PLL_FREQ_DET 0x0604 | |
2498 | #define DIV_STAT_DISP 0x0700 | |
2499 | #define DIV_STAT_DISP_PLL_FREQ_DET 0x0704 | |
2500 | #define ENABLE_ACLK_DISP0 0x0800 | |
2501 | #define ENABLE_ACLK_DISP1 0x0804 | |
2502 | #define ENABLE_PCLK_DISP 0x0900 | |
2503 | #define ENABLE_SCLK_DISP 0x0a00 | |
2504 | #define ENABLE_IP_DISP0 0x0b00 | |
2505 | #define ENABLE_IP_DISP1 0x0b04 | |
2506 | #define CLKOUT_CMU_DISP 0x0c00 | |
2507 | #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04 | |
2508 | ||
2509 | static unsigned long disp_clk_regs[] __initdata = { | |
2510 | DISP_PLL_LOCK, | |
2511 | DISP_PLL_CON0, | |
2512 | DISP_PLL_CON1, | |
2513 | DISP_PLL_FREQ_DET, | |
2514 | MUX_SEL_DISP0, | |
2515 | MUX_SEL_DISP1, | |
2516 | MUX_SEL_DISP2, | |
2517 | MUX_SEL_DISP3, | |
2518 | MUX_SEL_DISP4, | |
2519 | MUX_ENABLE_DISP0, | |
2520 | MUX_ENABLE_DISP1, | |
2521 | MUX_ENABLE_DISP2, | |
2522 | MUX_ENABLE_DISP3, | |
2523 | MUX_ENABLE_DISP4, | |
2524 | MUX_STAT_DISP0, | |
2525 | MUX_STAT_DISP1, | |
2526 | MUX_STAT_DISP2, | |
2527 | MUX_STAT_DISP3, | |
2528 | MUX_STAT_DISP4, | |
2529 | MUX_IGNORE_DISP2, | |
2530 | DIV_DISP, | |
2531 | DIV_DISP_PLL_FREQ_DET, | |
2532 | DIV_STAT_DISP, | |
2533 | DIV_STAT_DISP_PLL_FREQ_DET, | |
2534 | ENABLE_ACLK_DISP0, | |
2535 | ENABLE_ACLK_DISP1, | |
2536 | ENABLE_PCLK_DISP, | |
2537 | ENABLE_SCLK_DISP, | |
2538 | ENABLE_IP_DISP0, | |
2539 | ENABLE_IP_DISP1, | |
2540 | CLKOUT_CMU_DISP, | |
2541 | CLKOUT_CMU_DISP_DIV_STAT, | |
2542 | }; | |
2543 | ||
2544 | /* list of all parent clock list */ | |
2545 | PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", }; | |
2546 | PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", }; | |
2547 | PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", }; | |
2548 | PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", }; | |
2549 | PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk", | |
2550 | "sclk_decon_tv_eclk_disp", }; | |
2551 | PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk", | |
2552 | "sclk_decon_vclk_disp", }; | |
2553 | PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk", | |
2554 | "sclk_decon_eclk_disp", }; | |
2555 | PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk", | |
2556 | "sclk_decon_tv_vclk_disp", }; | |
2557 | PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", }; | |
2558 | ||
2559 | PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk", | |
2560 | "phyclk_mipidphy1_bitclkdiv8_phy", }; | |
2561 | PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk", | |
2562 | "phyclk_mipidphy1_rxclkesc0_phy", }; | |
2563 | PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk", | |
2564 | "phyclk_mipidphy0_bitclkdiv8_phy", }; | |
2565 | PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk", | |
2566 | "phyclk_mipidphy0_rxclkesc0_phy", }; | |
2567 | PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk", | |
2568 | "phyclk_hdmiphy_tmds_clko_phy", }; | |
2569 | PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk", | |
2570 | "phyclk_hdmiphy_pixel_clko_phy", }; | |
2571 | ||
2572 | PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll", | |
2573 | "mout_sclk_dsim0_user", }; | |
2574 | PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll", | |
2575 | "mout_sclk_decon_tv_eclk_user", }; | |
2576 | PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll", | |
2577 | "mout_sclk_decon_vclk_user", }; | |
2578 | PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll", | |
2579 | "mout_sclk_decon_eclk_user", }; | |
2580 | ||
2581 | PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp", | |
2582 | "mout_sclk_dsim1_user", }; | |
2583 | PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = { | |
2584 | "mout_phyclk_hdmiphy_pixel_clko_user", | |
2585 | "mout_sclk_decon_tv_vclk_b_disp", }; | |
2586 | PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp", | |
2587 | "mout_sclk_decon_tv_vclk_user", }; | |
2588 | ||
2589 | static struct samsung_pll_clock disp_pll_clks[] __initdata = { | |
2590 | PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk", | |
2591 | DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates), | |
2592 | }; | |
2593 | ||
2594 | static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = { | |
2595 | /* | |
2596 | * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}. | |
2597 | * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk} | |
2598 | * and sclk_decon_{vclk|tv_vclk}. | |
2599 | */ | |
2600 | FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk", | |
2601 | 1, 2, 0), | |
2602 | FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk", | |
2603 | 1, 2, 0), | |
2604 | }; | |
2605 | ||
2606 | static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = { | |
2607 | /* PHY clocks from MIPI_DPHY1 */ | |
2608 | FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, CLK_IS_ROOT, | |
2609 | 188000000), | |
2610 | FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, CLK_IS_ROOT, | |
2611 | 100000000), | |
2612 | /* PHY clocks from MIPI_DPHY0 */ | |
2613 | FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, CLK_IS_ROOT, | |
2614 | 188000000), | |
2615 | FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT, | |
2616 | 100000000), | |
2617 | /* PHY clocks from HDMI_PHY */ | |
2618 | FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000), | |
2619 | FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000), | |
2620 | }; | |
2621 | ||
2622 | static struct samsung_mux_clock disp_mux_clks[] __initdata = { | |
2623 | /* MUX_SEL_DISP0 */ | |
2624 | MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0, | |
2625 | 0, 1), | |
2626 | ||
2627 | /* MUX_SEL_DISP1 */ | |
2628 | MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user", | |
2629 | mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1), | |
2630 | MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user", | |
2631 | mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1), | |
2632 | MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p, | |
2633 | MUX_SEL_DISP1, 20, 1), | |
2634 | MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user", | |
2635 | mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1), | |
2636 | MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user", | |
2637 | mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1), | |
2638 | MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user", | |
2639 | mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1), | |
2640 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user", | |
2641 | mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1), | |
2642 | MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user", | |
2643 | mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1), | |
2644 | ||
2645 | /* MUX_SEL_DISP2 */ | |
2646 | MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER, | |
2647 | "mout_phyclk_mipidphy1_bitclkdiv8_user", | |
2648 | mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2, | |
2649 | 20, 1), | |
2650 | MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER, | |
2651 | "mout_phyclk_mipidphy1_rxclkesc0_user", | |
2652 | mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2, | |
2653 | 16, 1), | |
2654 | MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER, | |
2655 | "mout_phyclk_mipidphy0_bitclkdiv8_user", | |
2656 | mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2, | |
2657 | 12, 1), | |
2658 | MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER, | |
2659 | "mout_phyclk_mipidphy0_rxclkesc0_user", | |
2660 | mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2, | |
2661 | 8, 1), | |
2662 | MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER, | |
2663 | "mout_phyclk_hdmiphy_tmds_clko_user", | |
2664 | mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2, | |
2665 | 4, 1), | |
2666 | MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER, | |
2667 | "mout_phyclk_hdmiphy_pixel_clko_user", | |
2668 | mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2, | |
2669 | 0, 1), | |
2670 | ||
2671 | /* MUX_SEL_DISP3 */ | |
2672 | MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p, | |
2673 | MUX_SEL_DISP3, 12, 1), | |
2674 | MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk", | |
2675 | mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1), | |
2676 | MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk", | |
2677 | mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1), | |
2678 | MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk", | |
2679 | mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1), | |
2680 | ||
2681 | /* MUX_SEL_DISP4 */ | |
2682 | MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp", | |
2683 | mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1), | |
2684 | MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp", | |
2685 | mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1), | |
2686 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP, | |
2687 | "mout_sclk_decon_tv_vclk_c_disp", | |
2688 | mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1), | |
2689 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP, | |
2690 | "mout_sclk_decon_tv_vclk_b_disp", | |
2691 | mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1), | |
2692 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP, | |
2693 | "mout_sclk_decon_tv_vclk_a_disp", | |
2694 | mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1), | |
2695 | }; | |
2696 | ||
2697 | static struct samsung_div_clock disp_div_clks[] __initdata = { | |
2698 | /* DIV_DISP */ | |
2699 | DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp", | |
2700 | "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3), | |
2701 | DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp", | |
2702 | "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3), | |
2703 | DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0", | |
2704 | DIV_DISP, 16, 3), | |
2705 | DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp", | |
2706 | "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3), | |
2707 | DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp", | |
2708 | "mout_sclk_decon_vclk", DIV_DISP, 8, 3), | |
2709 | DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp", | |
2710 | "mout_sclk_decon_eclk", DIV_DISP, 4, 3), | |
2711 | DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user", | |
2712 | DIV_DISP, 0, 2), | |
2713 | }; | |
2714 | ||
2715 | static struct samsung_gate_clock disp_gate_clks[] __initdata = { | |
2716 | /* ENABLE_ACLK_DISP0 */ | |
2717 | GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user", | |
2718 | ENABLE_ACLK_DISP0, 2, 0, 0), | |
2719 | GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user", | |
2720 | ENABLE_ACLK_DISP0, 0, 0, 0), | |
2721 | ||
2722 | /* ENABLE_ACLK_DISP1 */ | |
2723 | GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user", | |
2724 | ENABLE_ACLK_DISP1, 25, 0, 0), | |
2725 | GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user", | |
2726 | ENABLE_ACLK_DISP1, 24, 0, 0), | |
2727 | GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x", | |
2728 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0), | |
2729 | GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x", | |
2730 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0), | |
2731 | GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3", | |
2732 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0), | |
2733 | GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2", | |
2734 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0), | |
2735 | GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1", | |
2736 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0), | |
2737 | GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0", | |
2738 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0), | |
2739 | GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4", | |
2740 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0), | |
2741 | GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3", | |
2742 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0), | |
2743 | GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2", | |
2744 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0), | |
2745 | GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1", | |
2746 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0), | |
2747 | GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0", | |
2748 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0), | |
2749 | GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p", | |
2750 | "div_pclk_disp", ENABLE_ACLK_DISP1, | |
2751 | 12, CLK_IGNORE_UNUSED, 0), | |
2752 | GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p", | |
2753 | "div_pclk_disp", ENABLE_ACLK_DISP1, | |
2754 | 11, CLK_IGNORE_UNUSED, 0), | |
2755 | GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p", | |
2756 | "div_pclk_disp", ENABLE_ACLK_DISP1, | |
2757 | 10, CLK_IGNORE_UNUSED, 0), | |
2758 | GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp", | |
2759 | ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0), | |
2760 | GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user", | |
2761 | ENABLE_ACLK_DISP1, 7, 0, 0), | |
2762 | GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user", | |
2763 | ENABLE_ACLK_DISP1, 6, 0, 0), | |
2764 | GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x", | |
2765 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0), | |
2766 | GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x", | |
2767 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0), | |
2768 | GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user", | |
2769 | ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0), | |
2770 | GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp", | |
2771 | ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0), | |
2772 | GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333", | |
2773 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1, | |
2774 | CLK_IGNORE_UNUSED, 0), | |
2775 | GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333", | |
2776 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, | |
2777 | 0, CLK_IGNORE_UNUSED, 0), | |
2778 | ||
2779 | /* ENABLE_PCLK_DISP */ | |
2780 | GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp", | |
2781 | ENABLE_PCLK_DISP, 23, 0, 0), | |
2782 | GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp", | |
2783 | ENABLE_PCLK_DISP, 22, 0, 0), | |
2784 | GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp", | |
2785 | ENABLE_PCLK_DISP, 21, 0, 0), | |
2786 | GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp", | |
2787 | ENABLE_PCLK_DISP, 20, 0, 0), | |
2788 | GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp", | |
2789 | ENABLE_PCLK_DISP, 19, 0, 0), | |
2790 | GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp", | |
2791 | ENABLE_PCLK_DISP, 18, 0, 0), | |
2792 | GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp", | |
2793 | ENABLE_PCLK_DISP, 17, 0, 0), | |
2794 | GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp", | |
2795 | ENABLE_PCLK_DISP, 16, 0, 0), | |
2796 | GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp", | |
2797 | ENABLE_PCLK_DISP, 15, 0, 0), | |
2798 | GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp", | |
2799 | ENABLE_PCLK_DISP, 14, 0, 0), | |
2800 | GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp", | |
2801 | ENABLE_PCLK_DISP, 13, 0, 0), | |
2802 | GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp", | |
2803 | ENABLE_PCLK_DISP, 12, 0, 0), | |
2804 | GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp", | |
2805 | ENABLE_PCLK_DISP, 11, 0, 0), | |
2806 | GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp", | |
2807 | ENABLE_PCLK_DISP, 10, 0, 0), | |
2808 | GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp", | |
2809 | ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0), | |
2810 | GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp", | |
2811 | ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0), | |
2812 | GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp", | |
2813 | ENABLE_PCLK_DISP, 7, 0, 0), | |
2814 | GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp", | |
2815 | ENABLE_PCLK_DISP, 6, 0, 0), | |
2816 | GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp", | |
2817 | ENABLE_PCLK_DISP, 5, 0, 0), | |
2818 | GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp", | |
2819 | ENABLE_PCLK_DISP, 3, 0, 0), | |
2820 | GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp", | |
2821 | ENABLE_PCLK_DISP, 2, 0, 0), | |
2822 | GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp", | |
2823 | ENABLE_PCLK_DISP, 1, 0, 0), | |
2824 | ||
2825 | /* ENABLE_SCLK_DISP */ | |
2826 | GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8", | |
2827 | "mout_phyclk_mipidphy1_bitclkdiv8_user", | |
2828 | ENABLE_SCLK_DISP, 26, 0, 0), | |
2829 | GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0", | |
2830 | "mout_phyclk_mipidphy1_rxclkesc0_user", | |
2831 | ENABLE_SCLK_DISP, 25, 0, 0), | |
2832 | GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1", | |
2833 | "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0), | |
2834 | GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1", | |
2835 | "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0), | |
2836 | GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp", | |
2837 | ENABLE_SCLK_DISP, 22, 0, 0), | |
2838 | GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk", | |
2839 | "div_sclk_decon_tv_vclk_disp", | |
2840 | ENABLE_SCLK_DISP, 21, 0, 0), | |
2841 | GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8", | |
2842 | "mout_phyclk_mipidphy0_bitclkdiv8_user", | |
2843 | ENABLE_SCLK_DISP, 15, 0, 0), | |
2844 | GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0", | |
2845 | "mout_phyclk_mipidphy0_rxclkesc0_user", | |
2846 | ENABLE_SCLK_DISP, 14, 0, 0), | |
2847 | GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko", | |
2848 | "mout_phyclk_hdmiphy_tmds_clko_user", | |
2849 | ENABLE_SCLK_DISP, 13, 0, 0), | |
2850 | GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel", | |
2851 | "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0), | |
2852 | GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies", | |
2853 | "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0), | |
2854 | GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0", | |
2855 | "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0), | |
2856 | GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0", | |
2857 | "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0), | |
2858 | GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user", | |
2859 | ENABLE_SCLK_DISP, 7, 0, 0), | |
2860 | GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp", | |
2861 | ENABLE_SCLK_DISP, 6, 0, 0), | |
2862 | GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp", | |
2863 | ENABLE_SCLK_DISP, 5, 0, 0), | |
2864 | GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk", | |
2865 | "div_sclk_decon_tv_eclk_disp", | |
2866 | ENABLE_SCLK_DISP, 4, 0, 0), | |
2867 | GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk", | |
2868 | "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0), | |
2869 | GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk", | |
2870 | "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0), | |
2871 | }; | |
2872 | ||
2873 | static struct samsung_cmu_info disp_cmu_info __initdata = { | |
2874 | .pll_clks = disp_pll_clks, | |
2875 | .nr_pll_clks = ARRAY_SIZE(disp_pll_clks), | |
2876 | .mux_clks = disp_mux_clks, | |
2877 | .nr_mux_clks = ARRAY_SIZE(disp_mux_clks), | |
2878 | .div_clks = disp_div_clks, | |
2879 | .nr_div_clks = ARRAY_SIZE(disp_div_clks), | |
2880 | .gate_clks = disp_gate_clks, | |
2881 | .nr_gate_clks = ARRAY_SIZE(disp_gate_clks), | |
2882 | .fixed_clks = disp_fixed_clks, | |
2883 | .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks), | |
2884 | .fixed_factor_clks = disp_fixed_factor_clks, | |
2885 | .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks), | |
2886 | .nr_clk_ids = DISP_NR_CLK, | |
2887 | .clk_regs = disp_clk_regs, | |
2888 | .nr_clk_regs = ARRAY_SIZE(disp_clk_regs), | |
2889 | }; | |
2890 | ||
2891 | static void __init exynos5433_cmu_disp_init(struct device_node *np) | |
2892 | { | |
2893 | samsung_cmu_register_one(np, &disp_cmu_info); | |
2894 | } | |
2895 | ||
2896 | CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp", | |
2897 | exynos5433_cmu_disp_init); | |
2e997c03 CC |
2898 | |
2899 | /* | |
2900 | * Register offset definitions for CMU_AUD | |
2901 | */ | |
2902 | #define MUX_SEL_AUD0 0x0200 | |
2903 | #define MUX_SEL_AUD1 0x0204 | |
2904 | #define MUX_ENABLE_AUD0 0x0300 | |
2905 | #define MUX_ENABLE_AUD1 0x0304 | |
2906 | #define MUX_STAT_AUD0 0x0400 | |
2907 | #define DIV_AUD0 0x0600 | |
2908 | #define DIV_AUD1 0x0604 | |
2909 | #define DIV_STAT_AUD0 0x0700 | |
2910 | #define DIV_STAT_AUD1 0x0704 | |
2911 | #define ENABLE_ACLK_AUD 0x0800 | |
2912 | #define ENABLE_PCLK_AUD 0x0900 | |
2913 | #define ENABLE_SCLK_AUD0 0x0a00 | |
2914 | #define ENABLE_SCLK_AUD1 0x0a04 | |
2915 | #define ENABLE_IP_AUD0 0x0b00 | |
2916 | #define ENABLE_IP_AUD1 0x0b04 | |
2917 | ||
2918 | static unsigned long aud_clk_regs[] __initdata = { | |
2919 | MUX_SEL_AUD0, | |
2920 | MUX_SEL_AUD1, | |
2921 | MUX_ENABLE_AUD0, | |
2922 | MUX_ENABLE_AUD1, | |
2923 | MUX_STAT_AUD0, | |
2924 | DIV_AUD0, | |
2925 | DIV_AUD1, | |
2926 | DIV_STAT_AUD0, | |
2927 | DIV_STAT_AUD1, | |
2928 | ENABLE_ACLK_AUD, | |
2929 | ENABLE_PCLK_AUD, | |
2930 | ENABLE_SCLK_AUD0, | |
2931 | ENABLE_SCLK_AUD1, | |
2932 | ENABLE_IP_AUD0, | |
2933 | ENABLE_IP_AUD1, | |
2934 | }; | |
2935 | ||
2936 | /* list of all parent clock list */ | |
2937 | PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", }; | |
2938 | PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",}; | |
2939 | ||
2940 | static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = { | |
2941 | FRATE(0, "ioclk_jtag_tclk", NULL, CLK_IS_ROOT, 33000000), | |
2942 | FRATE(0, "ioclk_slimbus_clk", NULL, CLK_IS_ROOT, 25000000), | |
2943 | FRATE(0, "ioclk_i2s_bclk", NULL, CLK_IS_ROOT, 50000000), | |
2944 | }; | |
2945 | ||
2946 | static struct samsung_mux_clock aud_mux_clks[] __initdata = { | |
2947 | /* MUX_SEL_AUD0 */ | |
2948 | MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user", | |
2949 | mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1), | |
2950 | ||
2951 | /* MUX_SEL_AUD1 */ | |
2952 | MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p, | |
2953 | MUX_SEL_AUD1, 8, 1), | |
2954 | MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p, | |
2955 | MUX_SEL_AUD1, 0, 1), | |
2956 | }; | |
2957 | ||
2958 | static struct samsung_div_clock aud_div_clks[] __initdata = { | |
2959 | /* DIV_AUD0 */ | |
2960 | DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0, | |
2961 | 12, 4), | |
2962 | DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0, | |
2963 | 8, 4), | |
2964 | DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0, | |
2965 | 4, 4), | |
2966 | DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0, | |
2967 | 0, 4), | |
2968 | ||
2969 | /* DIV_AUD1 */ | |
2970 | DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus", | |
2971 | "mout_aud_pll_user", DIV_AUD1, 16, 5), | |
2972 | DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user", | |
2973 | DIV_AUD1, 12, 4), | |
2974 | DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm", | |
2975 | DIV_AUD1, 4, 8), | |
2976 | DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s", | |
2977 | DIV_AUD1, 0, 4), | |
2978 | }; | |
2979 | ||
2980 | static struct samsung_gate_clock aud_gate_clks[] __initdata = { | |
2981 | /* ENABLE_ACLK_AUD */ | |
2982 | GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud", | |
2983 | ENABLE_ACLK_AUD, 12, 0, 0), | |
2984 | GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud", | |
2985 | ENABLE_ACLK_AUD, 7, 0, 0), | |
2986 | GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud", | |
2987 | ENABLE_ACLK_AUD, 0, 4, 0), | |
2988 | GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud", | |
2989 | ENABLE_ACLK_AUD, 0, 3, 0), | |
2990 | GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud", | |
2991 | ENABLE_ACLK_AUD, 0, 2, 0), | |
2992 | GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD, | |
2993 | 0, 1, 0), | |
2994 | GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD, | |
2995 | 0, CLK_IGNORE_UNUSED, 0), | |
2996 | ||
2997 | /* ENABLE_PCLK_AUD */ | |
2998 | GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD, | |
2999 | 13, 0, 0), | |
3000 | GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD, | |
3001 | 12, 0, 0), | |
3002 | GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD, | |
3003 | 11, 0, 0), | |
3004 | GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud", | |
3005 | ENABLE_PCLK_AUD, 10, 0, 0), | |
3006 | GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud", | |
3007 | ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0), | |
3008 | GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud", | |
3009 | ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0), | |
3010 | GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud", | |
3011 | ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0), | |
3012 | GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud", | |
3013 | ENABLE_PCLK_AUD, 6, 0, 0), | |
3014 | GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud", | |
3015 | ENABLE_PCLK_AUD, 5, 0, 0), | |
3016 | GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud", | |
3017 | ENABLE_PCLK_AUD, 4, 0, 0), | |
3018 | GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud", | |
3019 | ENABLE_PCLK_AUD, 3, 0, 0), | |
3020 | GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD, | |
3021 | 2, 0, 0), | |
3022 | GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud", | |
3023 | ENABLE_PCLK_AUD, 0, 0, 0), | |
3024 | ||
3025 | /* ENABLE_SCLK_AUD0 */ | |
3026 | GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0, | |
3027 | 2, 0, 0), | |
3028 | GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud", | |
3029 | ENABLE_SCLK_AUD0, 1, 0, 0), | |
3030 | GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0, | |
3031 | 0, 0, 0), | |
3032 | ||
3033 | /* ENABLE_SCLK_AUD1 */ | |
3034 | GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk", | |
3035 | ENABLE_SCLK_AUD1, 6, 0, 0), | |
3036 | GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk", | |
3037 | ENABLE_SCLK_AUD1, 5, 0, 0), | |
3038 | GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus", | |
3039 | ENABLE_SCLK_AUD1, 4, 0, 0), | |
3040 | GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart", | |
3041 | ENABLE_SCLK_AUD1, 3, 0, 0), | |
3042 | GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm", | |
3043 | ENABLE_SCLK_AUD1, 2, 0, 0), | |
3044 | GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk", | |
3045 | ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0), | |
3046 | GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s", | |
3047 | ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0), | |
3048 | }; | |
3049 | ||
3050 | static struct samsung_cmu_info aud_cmu_info __initdata = { | |
3051 | .mux_clks = aud_mux_clks, | |
3052 | .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), | |
3053 | .div_clks = aud_div_clks, | |
3054 | .nr_div_clks = ARRAY_SIZE(aud_div_clks), | |
3055 | .gate_clks = aud_gate_clks, | |
3056 | .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), | |
3057 | .fixed_clks = aud_fixed_clks, | |
3058 | .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks), | |
3059 | .nr_clk_ids = AUD_NR_CLK, | |
3060 | .clk_regs = aud_clk_regs, | |
3061 | .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), | |
3062 | }; | |
3063 | ||
3064 | static void __init exynos5433_cmu_aud_init(struct device_node *np) | |
3065 | { | |
3066 | samsung_cmu_register_one(np, &aud_cmu_info); | |
3067 | } | |
3068 | CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud", | |
3069 | exynos5433_cmu_aud_init); | |
5785d6e6 CC |
3070 | |
3071 | ||
3072 | /* | |
3073 | * Register offset definitions for CMU_BUS{0|1|2} | |
3074 | */ | |
3075 | #define DIV_BUS 0x0600 | |
3076 | #define DIV_STAT_BUS 0x0700 | |
3077 | #define ENABLE_ACLK_BUS 0x0800 | |
3078 | #define ENABLE_PCLK_BUS 0x0900 | |
3079 | #define ENABLE_IP_BUS0 0x0b00 | |
3080 | #define ENABLE_IP_BUS1 0x0b04 | |
3081 | ||
3082 | #define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */ | |
3083 | #define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */ | |
3084 | #define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */ | |
3085 | ||
3086 | /* list of all parent clock list */ | |
3087 | PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", }; | |
3088 | ||
3089 | #define CMU_BUS_COMMON_CLK_REGS \ | |
3090 | DIV_BUS, \ | |
3091 | DIV_STAT_BUS, \ | |
3092 | ENABLE_ACLK_BUS, \ | |
3093 | ENABLE_PCLK_BUS, \ | |
3094 | ENABLE_IP_BUS0, \ | |
3095 | ENABLE_IP_BUS1 | |
3096 | ||
3097 | static unsigned long bus01_clk_regs[] __initdata = { | |
3098 | CMU_BUS_COMMON_CLK_REGS, | |
3099 | }; | |
3100 | ||
3101 | static unsigned long bus2_clk_regs[] __initdata = { | |
3102 | MUX_SEL_BUS2, | |
3103 | MUX_ENABLE_BUS2, | |
3104 | MUX_STAT_BUS2, | |
3105 | CMU_BUS_COMMON_CLK_REGS, | |
3106 | }; | |
3107 | ||
3108 | static struct samsung_div_clock bus0_div_clks[] __initdata = { | |
3109 | /* DIV_BUS0 */ | |
3110 | DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400", | |
3111 | DIV_BUS, 0, 3), | |
3112 | }; | |
3113 | ||
3114 | /* CMU_BUS0 clocks */ | |
3115 | static struct samsung_gate_clock bus0_gate_clks[] __initdata = { | |
3116 | /* ENABLE_ACLK_BUS0 */ | |
3117 | GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133", | |
3118 | ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), | |
3119 | GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133", | |
3120 | ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), | |
3121 | GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400", | |
3122 | ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0), | |
3123 | ||
3124 | /* ENABLE_PCLK_BUS0 */ | |
3125 | GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133", | |
3126 | ENABLE_PCLK_BUS, 2, 0, 0), | |
3127 | GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133", | |
3128 | ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), | |
3129 | GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133", | |
3130 | ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), | |
3131 | }; | |
3132 | ||
3133 | /* CMU_BUS1 clocks */ | |
3134 | static struct samsung_div_clock bus1_div_clks[] __initdata = { | |
3135 | /* DIV_BUS1 */ | |
3136 | DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400", | |
3137 | DIV_BUS, 0, 3), | |
3138 | }; | |
3139 | ||
3140 | static struct samsung_gate_clock bus1_gate_clks[] __initdata = { | |
3141 | /* ENABLE_ACLK_BUS1 */ | |
3142 | GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133", | |
3143 | ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), | |
3144 | GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133", | |
3145 | ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), | |
3146 | GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400", | |
3147 | ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0), | |
3148 | ||
3149 | /* ENABLE_PCLK_BUS1 */ | |
3150 | GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133", | |
3151 | ENABLE_PCLK_BUS, 2, 0, 0), | |
3152 | GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133", | |
3153 | ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), | |
3154 | GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133", | |
3155 | ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), | |
3156 | }; | |
3157 | ||
3158 | /* CMU_BUS2 clocks */ | |
3159 | static struct samsung_mux_clock bus2_mux_clks[] __initdata = { | |
3160 | /* MUX_SEL_BUS2 */ | |
3161 | MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user", | |
3162 | mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1), | |
3163 | }; | |
3164 | ||
3165 | static struct samsung_div_clock bus2_div_clks[] __initdata = { | |
3166 | /* DIV_BUS2 */ | |
3167 | DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133", | |
3168 | "mout_aclk_bus2_400_user", DIV_BUS, 0, 3), | |
3169 | }; | |
3170 | ||
3171 | static struct samsung_gate_clock bus2_gate_clks[] __initdata = { | |
3172 | /* ENABLE_ACLK_BUS2 */ | |
3173 | GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133", | |
3174 | ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0), | |
3175 | GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133", | |
3176 | ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), | |
3177 | GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400", | |
3178 | "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS, | |
3179 | 1, CLK_IGNORE_UNUSED, 0), | |
3180 | GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400", | |
3181 | "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS, | |
3182 | 0, CLK_IGNORE_UNUSED, 0), | |
3183 | ||
3184 | /* ENABLE_PCLK_BUS2 */ | |
3185 | GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133", | |
3186 | ENABLE_PCLK_BUS, 2, 0, 0), | |
3187 | GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133", | |
3188 | ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), | |
3189 | GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133", | |
3190 | ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), | |
3191 | }; | |
3192 | ||
3193 | #define CMU_BUS_INFO_CLKS(id) \ | |
3194 | .div_clks = bus##id##_div_clks, \ | |
3195 | .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \ | |
3196 | .gate_clks = bus##id##_gate_clks, \ | |
3197 | .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \ | |
3198 | .nr_clk_ids = BUSx_NR_CLK | |
3199 | ||
3200 | static struct samsung_cmu_info bus0_cmu_info __initdata = { | |
3201 | CMU_BUS_INFO_CLKS(0), | |
3202 | .clk_regs = bus01_clk_regs, | |
3203 | .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), | |
3204 | }; | |
3205 | ||
3206 | static struct samsung_cmu_info bus1_cmu_info __initdata = { | |
3207 | CMU_BUS_INFO_CLKS(1), | |
3208 | .clk_regs = bus01_clk_regs, | |
3209 | .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), | |
3210 | }; | |
3211 | ||
3212 | static struct samsung_cmu_info bus2_cmu_info __initdata = { | |
3213 | CMU_BUS_INFO_CLKS(2), | |
3214 | .mux_clks = bus2_mux_clks, | |
3215 | .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks), | |
3216 | .clk_regs = bus2_clk_regs, | |
3217 | .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs), | |
3218 | }; | |
3219 | ||
3220 | #define exynos5433_cmu_bus_init(id) \ | |
3221 | static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\ | |
3222 | { \ | |
3223 | samsung_cmu_register_one(np, &bus##id##_cmu_info); \ | |
3224 | } \ | |
3225 | CLK_OF_DECLARE(exynos5433_cmu_bus##id, \ | |
3226 | "samsung,exynos5433-cmu-bus"#id, \ | |
3227 | exynos5433_cmu_bus##id##_init) | |
3228 | ||
3229 | exynos5433_cmu_bus_init(0); | |
3230 | exynos5433_cmu_bus_init(1); | |
3231 | exynos5433_cmu_bus_init(2); | |
453e519e CC |
3232 | |
3233 | /* | |
3234 | * Register offset definitions for CMU_G3D | |
3235 | */ | |
3236 | #define G3D_PLL_LOCK 0x0000 | |
3237 | #define G3D_PLL_CON0 0x0100 | |
3238 | #define G3D_PLL_CON1 0x0104 | |
3239 | #define G3D_PLL_FREQ_DET 0x010c | |
3240 | #define MUX_SEL_G3D 0x0200 | |
3241 | #define MUX_ENABLE_G3D 0x0300 | |
3242 | #define MUX_STAT_G3D 0x0400 | |
3243 | #define DIV_G3D 0x0600 | |
3244 | #define DIV_G3D_PLL_FREQ_DET 0x0604 | |
3245 | #define DIV_STAT_G3D 0x0700 | |
3246 | #define DIV_STAT_G3D_PLL_FREQ_DET 0x0704 | |
3247 | #define ENABLE_ACLK_G3D 0x0800 | |
3248 | #define ENABLE_PCLK_G3D 0x0900 | |
3249 | #define ENABLE_SCLK_G3D 0x0a00 | |
3250 | #define ENABLE_IP_G3D0 0x0b00 | |
3251 | #define ENABLE_IP_G3D1 0x0b04 | |
3252 | #define CLKOUT_CMU_G3D 0x0c00 | |
3253 | #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04 | |
3254 | #define CLK_STOPCTRL 0x1000 | |
3255 | ||
3256 | static unsigned long g3d_clk_regs[] __initdata = { | |
3257 | G3D_PLL_LOCK, | |
3258 | G3D_PLL_CON0, | |
3259 | G3D_PLL_CON1, | |
3260 | G3D_PLL_FREQ_DET, | |
3261 | MUX_SEL_G3D, | |
3262 | MUX_ENABLE_G3D, | |
3263 | MUX_STAT_G3D, | |
3264 | DIV_G3D, | |
3265 | DIV_G3D_PLL_FREQ_DET, | |
3266 | DIV_STAT_G3D, | |
3267 | DIV_STAT_G3D_PLL_FREQ_DET, | |
3268 | ENABLE_ACLK_G3D, | |
3269 | ENABLE_PCLK_G3D, | |
3270 | ENABLE_SCLK_G3D, | |
3271 | ENABLE_IP_G3D0, | |
3272 | ENABLE_IP_G3D1, | |
3273 | CLKOUT_CMU_G3D, | |
3274 | CLKOUT_CMU_G3D_DIV_STAT, | |
3275 | CLK_STOPCTRL, | |
3276 | }; | |
3277 | ||
3278 | /* list of all parent clock list */ | |
3279 | PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", }; | |
3280 | PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", }; | |
3281 | ||
3282 | static struct samsung_pll_clock g3d_pll_clks[] __initdata = { | |
3283 | PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", | |
3284 | G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates), | |
3285 | }; | |
3286 | ||
3287 | static struct samsung_mux_clock g3d_mux_clks[] __initdata = { | |
3288 | /* MUX_SEL_G3D */ | |
3289 | MUX(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p, | |
3290 | MUX_SEL_G3D, 8, 1), | |
3291 | MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, | |
3292 | MUX_SEL_G3D, 0, 1), | |
3293 | }; | |
3294 | ||
3295 | static struct samsung_div_clock g3d_div_clks[] __initdata = { | |
3296 | /* DIV_G3D */ | |
3297 | DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D, | |
3298 | 8, 2), | |
3299 | DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D, | |
3300 | 4, 3), | |
3301 | DIV(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D, | |
3302 | 0, 3), | |
3303 | }; | |
3304 | ||
3305 | static struct samsung_gate_clock g3d_gate_clks[] __initdata = { | |
3306 | /* ENABLE_ACLK_G3D */ | |
3307 | GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d", | |
3308 | ENABLE_ACLK_G3D, 7, 0, 0), | |
3309 | GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d", | |
3310 | ENABLE_ACLK_G3D, 6, 0, 0), | |
3311 | GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d", | |
3312 | ENABLE_ACLK_G3D, 5, 0, 0), | |
3313 | GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d", | |
3314 | ENABLE_ACLK_G3D, 4, 0, 0), | |
3315 | GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d", | |
3316 | ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0), | |
3317 | GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d", | |
3318 | ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0), | |
3319 | GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d", | |
3320 | ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0), | |
3321 | GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d", | |
3322 | ENABLE_ACLK_G3D, 0, 0, 0), | |
3323 | ||
3324 | /* ENABLE_PCLK_G3D */ | |
3325 | GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d", | |
3326 | ENABLE_PCLK_G3D, 3, 0, 0), | |
3327 | GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d", | |
3328 | ENABLE_PCLK_G3D, 2, 0, 0), | |
3329 | GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d", | |
3330 | ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0), | |
3331 | GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d", | |
3332 | ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0), | |
3333 | ||
3334 | /* ENABLE_SCLK_G3D */ | |
3335 | GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d", | |
3336 | ENABLE_SCLK_G3D, 0, 0, 0), | |
3337 | }; | |
3338 | ||
3339 | static struct samsung_cmu_info g3d_cmu_info __initdata = { | |
3340 | .pll_clks = g3d_pll_clks, | |
3341 | .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks), | |
3342 | .mux_clks = g3d_mux_clks, | |
3343 | .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks), | |
3344 | .div_clks = g3d_div_clks, | |
3345 | .nr_div_clks = ARRAY_SIZE(g3d_div_clks), | |
3346 | .gate_clks = g3d_gate_clks, | |
3347 | .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks), | |
3348 | .nr_clk_ids = G3D_NR_CLK, | |
3349 | .clk_regs = g3d_clk_regs, | |
3350 | .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), | |
3351 | }; | |
3352 | ||
3353 | static void __init exynos5433_cmu_g3d_init(struct device_node *np) | |
3354 | { | |
3355 | samsung_cmu_register_one(np, &g3d_cmu_info); | |
3356 | } | |
3357 | CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d", | |
3358 | exynos5433_cmu_g3d_init); | |
2a2f33e8 CC |
3359 | |
3360 | /* | |
3361 | * Register offset definitions for CMU_GSCL | |
3362 | */ | |
3363 | #define MUX_SEL_GSCL 0x0200 | |
3364 | #define MUX_ENABLE_GSCL 0x0300 | |
3365 | #define MUX_STAT_GSCL 0x0400 | |
3366 | #define ENABLE_ACLK_GSCL 0x0800 | |
3367 | #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804 | |
3368 | #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808 | |
3369 | #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c | |
3370 | #define ENABLE_PCLK_GSCL 0x0900 | |
3371 | #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904 | |
3372 | #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908 | |
3373 | #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c | |
3374 | #define ENABLE_IP_GSCL0 0x0b00 | |
3375 | #define ENABLE_IP_GSCL1 0x0b04 | |
3376 | #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08 | |
3377 | #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c | |
3378 | #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10 | |
3379 | ||
3380 | static unsigned long gscl_clk_regs[] __initdata = { | |
3381 | MUX_SEL_GSCL, | |
3382 | MUX_ENABLE_GSCL, | |
3383 | MUX_STAT_GSCL, | |
3384 | ENABLE_ACLK_GSCL, | |
3385 | ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, | |
3386 | ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, | |
3387 | ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, | |
3388 | ENABLE_PCLK_GSCL, | |
3389 | ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, | |
3390 | ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, | |
3391 | ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, | |
3392 | ENABLE_IP_GSCL0, | |
3393 | ENABLE_IP_GSCL1, | |
3394 | ENABLE_IP_GSCL_SECURE_SMMU_GSCL0, | |
3395 | ENABLE_IP_GSCL_SECURE_SMMU_GSCL1, | |
3396 | ENABLE_IP_GSCL_SECURE_SMMU_GSCL2, | |
3397 | }; | |
3398 | ||
3399 | /* list of all parent clock list */ | |
3400 | PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", }; | |
3401 | PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", }; | |
3402 | ||
3403 | static struct samsung_mux_clock gscl_mux_clks[] __initdata = { | |
3404 | /* MUX_SEL_GSCL */ | |
3405 | MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user", | |
3406 | aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1), | |
3407 | MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user", | |
3408 | aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1), | |
3409 | }; | |
3410 | ||
3411 | static struct samsung_gate_clock gscl_gate_clks[] __initdata = { | |
3412 | /* ENABLE_ACLK_GSCL */ | |
3413 | GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user", | |
3414 | ENABLE_ACLK_GSCL, 11, 0, 0), | |
3415 | GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user", | |
3416 | ENABLE_ACLK_GSCL, 10, 0, 0), | |
3417 | GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user", | |
3418 | ENABLE_ACLK_GSCL, 9, 0, 0), | |
3419 | GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp", | |
3420 | "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL, | |
3421 | 8, CLK_IGNORE_UNUSED, 0), | |
3422 | GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user", | |
3423 | ENABLE_ACLK_GSCL, 7, 0, 0), | |
3424 | GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user", | |
3425 | ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0), | |
3426 | GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333", | |
3427 | "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 0, 0), | |
3428 | GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333", | |
3429 | "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 0, 0), | |
3430 | GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user", | |
3431 | ENABLE_ACLK_GSCL, 3, 0, 0), | |
3432 | GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user", | |
3433 | ENABLE_ACLK_GSCL, 2, 0, 0), | |
3434 | GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user", | |
3435 | ENABLE_ACLK_GSCL, 1, 0, 0), | |
3436 | GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user", | |
3437 | ENABLE_ACLK_GSCL, 0, 0, 0), | |
3438 | ||
3439 | /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */ | |
3440 | GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user", | |
3441 | ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), | |
3442 | ||
3443 | /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */ | |
3444 | GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user", | |
3445 | ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0), | |
3446 | ||
3447 | /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */ | |
3448 | GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user", | |
3449 | ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0), | |
3450 | ||
3451 | /* ENABLE_PCLK_GSCL */ | |
3452 | GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user", | |
3453 | ENABLE_PCLK_GSCL, 7, 0, 0), | |
3454 | GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user", | |
3455 | ENABLE_PCLK_GSCL, 6, 0, 0), | |
3456 | GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user", | |
3457 | ENABLE_PCLK_GSCL, 5, 0, 0), | |
3458 | GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user", | |
3459 | ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0), | |
3460 | GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl", | |
3461 | "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL, | |
3462 | 3, CLK_IGNORE_UNUSED, 0), | |
3463 | GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user", | |
3464 | ENABLE_PCLK_GSCL, 2, 0, 0), | |
3465 | GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user", | |
3466 | ENABLE_PCLK_GSCL, 1, 0, 0), | |
3467 | GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user", | |
3468 | ENABLE_PCLK_GSCL, 0, 0, 0), | |
3469 | ||
3470 | /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */ | |
3471 | GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user", | |
3472 | ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), | |
3473 | ||
3474 | /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */ | |
3475 | GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user", | |
3476 | ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), | |
3477 | ||
3478 | /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */ | |
3479 | GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user", | |
3480 | ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), | |
3481 | }; | |
3482 | ||
3483 | static struct samsung_cmu_info gscl_cmu_info __initdata = { | |
3484 | .mux_clks = gscl_mux_clks, | |
3485 | .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks), | |
3486 | .gate_clks = gscl_gate_clks, | |
3487 | .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks), | |
3488 | .nr_clk_ids = GSCL_NR_CLK, | |
3489 | .clk_regs = gscl_clk_regs, | |
3490 | .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs), | |
3491 | }; | |
3492 | ||
3493 | static void __init exynos5433_cmu_gscl_init(struct device_node *np) | |
3494 | { | |
3495 | samsung_cmu_register_one(np, &gscl_cmu_info); | |
3496 | } | |
3497 | CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl", | |
3498 | exynos5433_cmu_gscl_init); | |
df40a13c CC |
3499 | |
3500 | /* | |
3501 | * Register offset definitions for CMU_APOLLO | |
3502 | */ | |
3503 | #define APOLLO_PLL_LOCK 0x0000 | |
3504 | #define APOLLO_PLL_CON0 0x0100 | |
3505 | #define APOLLO_PLL_CON1 0x0104 | |
3506 | #define APOLLO_PLL_FREQ_DET 0x010c | |
3507 | #define MUX_SEL_APOLLO0 0x0200 | |
3508 | #define MUX_SEL_APOLLO1 0x0204 | |
3509 | #define MUX_SEL_APOLLO2 0x0208 | |
3510 | #define MUX_ENABLE_APOLLO0 0x0300 | |
3511 | #define MUX_ENABLE_APOLLO1 0x0304 | |
3512 | #define MUX_ENABLE_APOLLO2 0x0308 | |
3513 | #define MUX_STAT_APOLLO0 0x0400 | |
3514 | #define MUX_STAT_APOLLO1 0x0404 | |
3515 | #define MUX_STAT_APOLLO2 0x0408 | |
3516 | #define DIV_APOLLO0 0x0600 | |
3517 | #define DIV_APOLLO1 0x0604 | |
3518 | #define DIV_APOLLO_PLL_FREQ_DET 0x0608 | |
3519 | #define DIV_STAT_APOLLO0 0x0700 | |
3520 | #define DIV_STAT_APOLLO1 0x0704 | |
3521 | #define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708 | |
3522 | #define ENABLE_ACLK_APOLLO 0x0800 | |
3523 | #define ENABLE_PCLK_APOLLO 0x0900 | |
3524 | #define ENABLE_SCLK_APOLLO 0x0a00 | |
3525 | #define ENABLE_IP_APOLLO0 0x0b00 | |
3526 | #define ENABLE_IP_APOLLO1 0x0b04 | |
3527 | #define CLKOUT_CMU_APOLLO 0x0c00 | |
3528 | #define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04 | |
3529 | #define ARMCLK_STOPCTRL 0x1000 | |
3530 | #define APOLLO_PWR_CTRL 0x1020 | |
3531 | #define APOLLO_PWR_CTRL2 0x1024 | |
3532 | #define APOLLO_INTR_SPREAD_ENABLE 0x1080 | |
3533 | #define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084 | |
3534 | #define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088 | |
3535 | ||
3536 | static unsigned long apollo_clk_regs[] __initdata = { | |
3537 | APOLLO_PLL_LOCK, | |
3538 | APOLLO_PLL_CON0, | |
3539 | APOLLO_PLL_CON1, | |
3540 | APOLLO_PLL_FREQ_DET, | |
3541 | MUX_SEL_APOLLO0, | |
3542 | MUX_SEL_APOLLO1, | |
3543 | MUX_SEL_APOLLO2, | |
3544 | MUX_ENABLE_APOLLO0, | |
3545 | MUX_ENABLE_APOLLO1, | |
3546 | MUX_ENABLE_APOLLO2, | |
3547 | MUX_STAT_APOLLO0, | |
3548 | MUX_STAT_APOLLO1, | |
3549 | MUX_STAT_APOLLO2, | |
3550 | DIV_APOLLO0, | |
3551 | DIV_APOLLO1, | |
3552 | DIV_APOLLO_PLL_FREQ_DET, | |
3553 | DIV_STAT_APOLLO0, | |
3554 | DIV_STAT_APOLLO1, | |
3555 | DIV_STAT_APOLLO_PLL_FREQ_DET, | |
3556 | ENABLE_ACLK_APOLLO, | |
3557 | ENABLE_PCLK_APOLLO, | |
3558 | ENABLE_SCLK_APOLLO, | |
3559 | ENABLE_IP_APOLLO0, | |
3560 | ENABLE_IP_APOLLO1, | |
3561 | CLKOUT_CMU_APOLLO, | |
3562 | CLKOUT_CMU_APOLLO_DIV_STAT, | |
3563 | ARMCLK_STOPCTRL, | |
3564 | APOLLO_PWR_CTRL, | |
3565 | APOLLO_PWR_CTRL2, | |
3566 | APOLLO_INTR_SPREAD_ENABLE, | |
3567 | APOLLO_INTR_SPREAD_USE_STANDBYWFI, | |
3568 | APOLLO_INTR_SPREAD_BLOCKING_DURATION, | |
3569 | }; | |
3570 | ||
3571 | /* list of all parent clock list */ | |
3572 | PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", }; | |
3573 | PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", }; | |
3574 | PNAME(mout_apollo_p) = { "mout_apollo_pll", | |
3575 | "mout_bus_pll_apollo_user", }; | |
3576 | ||
3577 | static struct samsung_pll_clock apollo_pll_clks[] __initdata = { | |
3578 | PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk", | |
3579 | APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates), | |
3580 | }; | |
3581 | ||
3582 | static struct samsung_mux_clock apollo_mux_clks[] __initdata = { | |
3583 | /* MUX_SEL_APOLLO0 */ | |
3584 | MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p, | |
3585 | MUX_SEL_APOLLO0, 0, 1, 0, CLK_MUX_READ_ONLY), | |
3586 | ||
3587 | /* MUX_SEL_APOLLO1 */ | |
3588 | MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user", | |
3589 | mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1), | |
3590 | ||
3591 | /* MUX_SEL_APOLLO2 */ | |
3592 | MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2, | |
3593 | 0, 1, 0, CLK_MUX_READ_ONLY), | |
3594 | }; | |
3595 | ||
3596 | static struct samsung_div_clock apollo_div_clks[] __initdata = { | |
3597 | /* DIV_APOLLO0 */ | |
3598 | DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2", | |
3599 | DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE, | |
3600 | CLK_DIVIDER_READ_ONLY), | |
3601 | DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2", | |
3602 | DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE, | |
3603 | CLK_DIVIDER_READ_ONLY), | |
3604 | DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2", | |
3605 | DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE, | |
3606 | CLK_DIVIDER_READ_ONLY), | |
3607 | DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2", | |
3608 | DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE, | |
3609 | CLK_DIVIDER_READ_ONLY), | |
3610 | DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2", | |
3611 | DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE, | |
3612 | CLK_DIVIDER_READ_ONLY), | |
3613 | DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1", | |
3614 | DIV_APOLLO0, 4, 3, CLK_GET_RATE_NOCACHE, | |
3615 | CLK_DIVIDER_READ_ONLY), | |
3616 | DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo", | |
3617 | DIV_APOLLO0, 0, 3, CLK_GET_RATE_NOCACHE, | |
3618 | CLK_DIVIDER_READ_ONLY), | |
3619 | ||
3620 | /* DIV_APOLLO1 */ | |
3621 | DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo", | |
3622 | DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE, | |
3623 | CLK_DIVIDER_READ_ONLY), | |
3624 | DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo", | |
3625 | DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE, | |
3626 | CLK_DIVIDER_READ_ONLY), | |
3627 | }; | |
3628 | ||
3629 | static struct samsung_gate_clock apollo_gate_clks[] __initdata = { | |
3630 | /* ENABLE_ACLK_APOLLO */ | |
3631 | GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys", | |
3632 | "div_atclk_apollo", ENABLE_ACLK_APOLLO, | |
3633 | 6, CLK_IGNORE_UNUSED, 0), | |
3634 | GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys", | |
3635 | "div_atclk_apollo", ENABLE_ACLK_APOLLO, | |
3636 | 5, CLK_IGNORE_UNUSED, 0), | |
3637 | GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys", | |
3638 | "div_atclk_apollo", ENABLE_ACLK_APOLLO, | |
3639 | 4, CLK_IGNORE_UNUSED, 0), | |
3640 | GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys", | |
3641 | "div_atclk_apollo", ENABLE_ACLK_APOLLO, | |
3642 | 3, CLK_IGNORE_UNUSED, 0), | |
3643 | GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci", | |
3644 | "div_aclk_apollo", ENABLE_ACLK_APOLLO, | |
3645 | 2, CLK_IGNORE_UNUSED, 0), | |
3646 | GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop", | |
3647 | "div_pclk_apollo", ENABLE_ACLK_APOLLO, | |
3648 | 1, CLK_IGNORE_UNUSED, 0), | |
3649 | GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200", | |
3650 | "div_pclk_apollo", ENABLE_ACLK_APOLLO, | |
3651 | 0, CLK_IGNORE_UNUSED, 0), | |
3652 | ||
3653 | /* ENABLE_PCLK_APOLLO */ | |
3654 | GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo", | |
3655 | "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO, | |
3656 | 2, CLK_IGNORE_UNUSED, 0), | |
3657 | GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo", | |
3658 | ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), | |
3659 | GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo", | |
3660 | "div_pclk_apollo", ENABLE_PCLK_APOLLO, | |
3661 | 0, CLK_IGNORE_UNUSED, 0), | |
3662 | ||
3663 | /* ENABLE_SCLK_APOLLO */ | |
3664 | GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo", | |
3665 | ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0), | |
3666 | GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo", | |
3667 | ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), | |
3668 | GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo_pll", | |
3669 | ENABLE_SCLK_APOLLO, 0, CLK_IGNORE_UNUSED, 0), | |
3670 | }; | |
3671 | ||
3672 | static struct samsung_cmu_info apollo_cmu_info __initdata = { | |
3673 | .pll_clks = apollo_pll_clks, | |
3674 | .nr_pll_clks = ARRAY_SIZE(apollo_pll_clks), | |
3675 | .mux_clks = apollo_mux_clks, | |
3676 | .nr_mux_clks = ARRAY_SIZE(apollo_mux_clks), | |
3677 | .div_clks = apollo_div_clks, | |
3678 | .nr_div_clks = ARRAY_SIZE(apollo_div_clks), | |
3679 | .gate_clks = apollo_gate_clks, | |
3680 | .nr_gate_clks = ARRAY_SIZE(apollo_gate_clks), | |
3681 | .nr_clk_ids = APOLLO_NR_CLK, | |
3682 | .clk_regs = apollo_clk_regs, | |
3683 | .nr_clk_regs = ARRAY_SIZE(apollo_clk_regs), | |
3684 | }; | |
3685 | ||
3686 | static void __init exynos5433_cmu_apollo_init(struct device_node *np) | |
3687 | { | |
3688 | samsung_cmu_register_one(np, &apollo_cmu_info); | |
3689 | } | |
3690 | CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo", | |
3691 | exynos5433_cmu_apollo_init); | |
6c5d76d1 CC |
3692 | |
3693 | /* | |
3694 | * Register offset definitions for CMU_ATLAS | |
3695 | */ | |
3696 | #define ATLAS_PLL_LOCK 0x0000 | |
3697 | #define ATLAS_PLL_CON0 0x0100 | |
3698 | #define ATLAS_PLL_CON1 0x0104 | |
3699 | #define ATLAS_PLL_FREQ_DET 0x010c | |
3700 | #define MUX_SEL_ATLAS0 0x0200 | |
3701 | #define MUX_SEL_ATLAS1 0x0204 | |
3702 | #define MUX_SEL_ATLAS2 0x0208 | |
3703 | #define MUX_ENABLE_ATLAS0 0x0300 | |
3704 | #define MUX_ENABLE_ATLAS1 0x0304 | |
3705 | #define MUX_ENABLE_ATLAS2 0x0308 | |
3706 | #define MUX_STAT_ATLAS0 0x0400 | |
3707 | #define MUX_STAT_ATLAS1 0x0404 | |
3708 | #define MUX_STAT_ATLAS2 0x0408 | |
3709 | #define DIV_ATLAS0 0x0600 | |
3710 | #define DIV_ATLAS1 0x0604 | |
3711 | #define DIV_ATLAS_PLL_FREQ_DET 0x0608 | |
3712 | #define DIV_STAT_ATLAS0 0x0700 | |
3713 | #define DIV_STAT_ATLAS1 0x0704 | |
3714 | #define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708 | |
3715 | #define ENABLE_ACLK_ATLAS 0x0800 | |
3716 | #define ENABLE_PCLK_ATLAS 0x0900 | |
3717 | #define ENABLE_SCLK_ATLAS 0x0a00 | |
3718 | #define ENABLE_IP_ATLAS0 0x0b00 | |
3719 | #define ENABLE_IP_ATLAS1 0x0b04 | |
3720 | #define CLKOUT_CMU_ATLAS 0x0c00 | |
3721 | #define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04 | |
3722 | #define ARMCLK_STOPCTRL 0x1000 | |
3723 | #define ATLAS_PWR_CTRL 0x1020 | |
3724 | #define ATLAS_PWR_CTRL2 0x1024 | |
3725 | #define ATLAS_INTR_SPREAD_ENABLE 0x1080 | |
3726 | #define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084 | |
3727 | #define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088 | |
3728 | ||
3729 | static unsigned long atlas_clk_regs[] __initdata = { | |
3730 | ATLAS_PLL_LOCK, | |
3731 | ATLAS_PLL_CON0, | |
3732 | ATLAS_PLL_CON1, | |
3733 | ATLAS_PLL_FREQ_DET, | |
3734 | MUX_SEL_ATLAS0, | |
3735 | MUX_SEL_ATLAS1, | |
3736 | MUX_SEL_ATLAS2, | |
3737 | MUX_ENABLE_ATLAS0, | |
3738 | MUX_ENABLE_ATLAS1, | |
3739 | MUX_ENABLE_ATLAS2, | |
3740 | MUX_STAT_ATLAS0, | |
3741 | MUX_STAT_ATLAS1, | |
3742 | MUX_STAT_ATLAS2, | |
3743 | DIV_ATLAS0, | |
3744 | DIV_ATLAS1, | |
3745 | DIV_ATLAS_PLL_FREQ_DET, | |
3746 | DIV_STAT_ATLAS0, | |
3747 | DIV_STAT_ATLAS1, | |
3748 | DIV_STAT_ATLAS_PLL_FREQ_DET, | |
3749 | ENABLE_ACLK_ATLAS, | |
3750 | ENABLE_PCLK_ATLAS, | |
3751 | ENABLE_SCLK_ATLAS, | |
3752 | ENABLE_IP_ATLAS0, | |
3753 | ENABLE_IP_ATLAS1, | |
3754 | CLKOUT_CMU_ATLAS, | |
3755 | CLKOUT_CMU_ATLAS_DIV_STAT, | |
3756 | ARMCLK_STOPCTRL, | |
3757 | ATLAS_PWR_CTRL, | |
3758 | ATLAS_PWR_CTRL2, | |
3759 | ATLAS_INTR_SPREAD_ENABLE, | |
3760 | ATLAS_INTR_SPREAD_USE_STANDBYWFI, | |
3761 | ATLAS_INTR_SPREAD_BLOCKING_DURATION, | |
3762 | }; | |
3763 | ||
3764 | /* list of all parent clock list */ | |
3765 | PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", }; | |
3766 | PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", }; | |
3767 | PNAME(mout_atlas_p) = { "mout_atlas_pll", | |
3768 | "mout_bus_pll_atlas_user", }; | |
3769 | ||
3770 | static struct samsung_pll_clock atlas_pll_clks[] __initdata = { | |
3771 | PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk", | |
3772 | ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates), | |
3773 | }; | |
3774 | ||
3775 | static struct samsung_mux_clock atlas_mux_clks[] __initdata = { | |
3776 | /* MUX_SEL_ATLAS0 */ | |
3777 | MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p, | |
3778 | MUX_SEL_ATLAS0, 0, 1, 0, CLK_MUX_READ_ONLY), | |
3779 | ||
3780 | /* MUX_SEL_ATLAS1 */ | |
3781 | MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user", | |
3782 | mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1), | |
3783 | ||
3784 | /* MUX_SEL_ATLAS2 */ | |
3785 | MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2, | |
3786 | 0, 1, 0, CLK_MUX_READ_ONLY), | |
3787 | }; | |
3788 | ||
3789 | static struct samsung_div_clock atlas_div_clks[] __initdata = { | |
3790 | /* DIV_ATLAS0 */ | |
3791 | DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2", | |
3792 | DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE, | |
3793 | CLK_DIVIDER_READ_ONLY), | |
3794 | DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas", | |
3795 | DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE, | |
3796 | CLK_DIVIDER_READ_ONLY), | |
3797 | DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2", | |
3798 | DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE, | |
3799 | CLK_DIVIDER_READ_ONLY), | |
3800 | DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2", | |
3801 | DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE, | |
3802 | CLK_DIVIDER_READ_ONLY), | |
3803 | DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2", | |
3804 | DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE, | |
3805 | CLK_DIVIDER_READ_ONLY), | |
3806 | DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1", | |
3807 | DIV_ATLAS0, 4, 3, CLK_GET_RATE_NOCACHE, | |
3808 | CLK_DIVIDER_READ_ONLY), | |
3809 | DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas", | |
3810 | DIV_ATLAS0, 0, 3, CLK_GET_RATE_NOCACHE, | |
3811 | CLK_DIVIDER_READ_ONLY), | |
3812 | ||
3813 | /* DIV_ATLAS1 */ | |
3814 | DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas", | |
3815 | DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE, | |
3816 | CLK_DIVIDER_READ_ONLY), | |
3817 | DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas", | |
3818 | DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE, | |
3819 | CLK_DIVIDER_READ_ONLY), | |
3820 | }; | |
3821 | ||
3822 | static struct samsung_gate_clock atlas_gate_clks[] __initdata = { | |
3823 | /* ENABLE_ACLK_ATLAS */ | |
3824 | GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys", | |
3825 | "div_atclk_atlas", ENABLE_ACLK_ATLAS, | |
3826 | 9, CLK_IGNORE_UNUSED, 0), | |
3827 | GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys", | |
3828 | "div_atclk_atlas", ENABLE_ACLK_ATLAS, | |
3829 | 8, CLK_IGNORE_UNUSED, 0), | |
3830 | GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys", | |
3831 | "div_atclk_atlas", ENABLE_ACLK_ATLAS, | |
3832 | 7, CLK_IGNORE_UNUSED, 0), | |
3833 | GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys", | |
3834 | "div_atclk_atlas", ENABLE_ACLK_ATLAS, | |
3835 | 6, CLK_IGNORE_UNUSED, 0), | |
3836 | GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys", | |
3837 | "div_atclk_atlas", ENABLE_ACLK_ATLAS, | |
3838 | 5, CLK_IGNORE_UNUSED, 0), | |
3839 | GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss", | |
3840 | "div_atclk_atlas", ENABLE_ACLK_ATLAS, | |
3841 | 4, CLK_IGNORE_UNUSED, 0), | |
3842 | GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix", | |
3843 | "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS, | |
3844 | 3, CLK_IGNORE_UNUSED, 0), | |
3845 | GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci", | |
3846 | "div_aclk_atlas", ENABLE_ACLK_ATLAS, | |
3847 | 2, CLK_IGNORE_UNUSED, 0), | |
3848 | GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas", | |
3849 | ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), | |
3850 | GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas", | |
3851 | ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0), | |
3852 | ||
3853 | /* ENABLE_PCLK_ATLAS */ | |
3854 | GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys", | |
3855 | "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS, | |
3856 | 5, CLK_IGNORE_UNUSED, 0), | |
3857 | GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys", | |
3858 | "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS, | |
3859 | 4, CLK_IGNORE_UNUSED, 0), | |
3860 | GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys", | |
3861 | "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS, | |
3862 | 3, CLK_IGNORE_UNUSED, 0), | |
3863 | GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas", | |
3864 | ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0), | |
3865 | GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas", | |
3866 | ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), | |
3867 | GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas", | |
3868 | ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0), | |
3869 | ||
3870 | /* ENABLE_SCLK_ATLAS */ | |
3871 | GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas", | |
3872 | ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0), | |
3873 | GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas", | |
3874 | ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0), | |
3875 | GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas", | |
3876 | ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0), | |
3877 | GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas", | |
3878 | ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0), | |
3879 | GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas", | |
3880 | ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0), | |
3881 | GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas", | |
3882 | ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0), | |
3883 | GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas", | |
3884 | ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0), | |
3885 | GATE(CLK_ATCLK, "atclk", "div_atclk_atlas", | |
3886 | ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), | |
3887 | GATE(CLK_SCLK_ATLAS, "sclk_atlas", "div_atlas2", | |
3888 | ENABLE_SCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0), | |
3889 | }; | |
3890 | ||
3891 | static struct samsung_cmu_info atlas_cmu_info __initdata = { | |
3892 | .pll_clks = atlas_pll_clks, | |
3893 | .nr_pll_clks = ARRAY_SIZE(atlas_pll_clks), | |
3894 | .mux_clks = atlas_mux_clks, | |
3895 | .nr_mux_clks = ARRAY_SIZE(atlas_mux_clks), | |
3896 | .div_clks = atlas_div_clks, | |
3897 | .nr_div_clks = ARRAY_SIZE(atlas_div_clks), | |
3898 | .gate_clks = atlas_gate_clks, | |
3899 | .nr_gate_clks = ARRAY_SIZE(atlas_gate_clks), | |
3900 | .nr_clk_ids = ATLAS_NR_CLK, | |
3901 | .clk_regs = atlas_clk_regs, | |
3902 | .nr_clk_regs = ARRAY_SIZE(atlas_clk_regs), | |
3903 | }; | |
3904 | ||
3905 | static void __init exynos5433_cmu_atlas_init(struct device_node *np) | |
3906 | { | |
3907 | samsung_cmu_register_one(np, &atlas_cmu_info); | |
3908 | } | |
3909 | CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas", | |
3910 | exynos5433_cmu_atlas_init); | |
b274bbfd CC |
3911 | |
3912 | /* | |
3913 | * Register offset definitions for CMU_MSCL | |
3914 | */ | |
3915 | #define MUX_SEL_MSCL0 0x0200 | |
3916 | #define MUX_SEL_MSCL1 0x0204 | |
3917 | #define MUX_ENABLE_MSCL0 0x0300 | |
3918 | #define MUX_ENABLE_MSCL1 0x0304 | |
3919 | #define MUX_STAT_MSCL0 0x0400 | |
3920 | #define MUX_STAT_MSCL1 0x0404 | |
3921 | #define DIV_MSCL 0x0600 | |
3922 | #define DIV_STAT_MSCL 0x0700 | |
3923 | #define ENABLE_ACLK_MSCL 0x0800 | |
3924 | #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804 | |
3925 | #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808 | |
3926 | #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c | |
3927 | #define ENABLE_PCLK_MSCL 0x0900 | |
3928 | #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904 | |
3929 | #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908 | |
a84d1f54 | 3930 | #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c |
b274bbfd CC |
3931 | #define ENABLE_SCLK_MSCL 0x0a00 |
3932 | #define ENABLE_IP_MSCL0 0x0b00 | |
3933 | #define ENABLE_IP_MSCL1 0x0b04 | |
3934 | #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08 | |
3935 | #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c | |
3936 | #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10 | |
3937 | ||
3938 | static unsigned long mscl_clk_regs[] __initdata = { | |
3939 | MUX_SEL_MSCL0, | |
3940 | MUX_SEL_MSCL1, | |
3941 | MUX_ENABLE_MSCL0, | |
3942 | MUX_ENABLE_MSCL1, | |
3943 | MUX_STAT_MSCL0, | |
3944 | MUX_STAT_MSCL1, | |
3945 | DIV_MSCL, | |
3946 | DIV_STAT_MSCL, | |
3947 | ENABLE_ACLK_MSCL, | |
3948 | ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0, | |
3949 | ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1, | |
3950 | ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG, | |
3951 | ENABLE_PCLK_MSCL, | |
3952 | ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0, | |
3953 | ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1, | |
3954 | ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG, | |
3955 | ENABLE_SCLK_MSCL, | |
3956 | ENABLE_IP_MSCL0, | |
3957 | ENABLE_IP_MSCL1, | |
3958 | ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0, | |
3959 | ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1, | |
3960 | ENABLE_IP_MSCL_SECURE_SMMU_JPEG, | |
3961 | }; | |
3962 | ||
3963 | /* list of all parent clock list */ | |
3964 | PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", }; | |
3965 | PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", }; | |
3966 | PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user", | |
3967 | "mout_aclk_mscl_400_user", }; | |
3968 | ||
3969 | static struct samsung_mux_clock mscl_mux_clks[] __initdata = { | |
3970 | /* MUX_SEL_MSCL0 */ | |
3971 | MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user", | |
3972 | mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1), | |
3973 | MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user", | |
3974 | mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1), | |
3975 | ||
3976 | /* MUX_SEL_MSCL1 */ | |
3977 | MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p, | |
3978 | MUX_SEL_MSCL1, 0, 1), | |
3979 | }; | |
3980 | ||
3981 | static struct samsung_div_clock mscl_div_clks[] __initdata = { | |
3982 | /* DIV_MSCL */ | |
3983 | DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user", | |
3984 | DIV_MSCL, 0, 3), | |
3985 | }; | |
3986 | ||
3987 | static struct samsung_gate_clock mscl_gate_clks[] __initdata = { | |
3988 | /* ENABLE_ACLK_MSCL */ | |
3989 | GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user", | |
3990 | ENABLE_ACLK_MSCL, 9, 0, 0), | |
3991 | GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1", | |
3992 | "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0), | |
3993 | GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0", | |
3994 | "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0), | |
3995 | GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl", | |
3996 | ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0), | |
3997 | GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user", | |
3998 | ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0), | |
3999 | GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl", | |
4000 | ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0), | |
4001 | GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user", | |
4002 | ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0), | |
4003 | GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user", | |
4004 | ENABLE_ACLK_MSCL, 2, 0, 0), | |
4005 | GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user", | |
4006 | ENABLE_ACLK_MSCL, 1, 0, 0), | |
4007 | GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user", | |
4008 | ENABLE_ACLK_MSCL, 0, 0, 0), | |
4009 | ||
4010 | /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */ | |
4011 | GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0", | |
4012 | "mout_aclk_mscl_400_user", | |
4013 | ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0, | |
4014 | 0, CLK_IGNORE_UNUSED, 0), | |
4015 | ||
4016 | /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */ | |
4017 | GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1", | |
4018 | "mout_aclk_mscl_400_user", | |
4019 | ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1, | |
4020 | 0, CLK_IGNORE_UNUSED, 0), | |
4021 | ||
4022 | /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */ | |
4023 | GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user", | |
4024 | ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG, | |
4025 | 0, CLK_IGNORE_UNUSED, 0), | |
4026 | ||
4027 | /* ENABLE_PCLK_MSCL */ | |
4028 | GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl", | |
4029 | ENABLE_PCLK_MSCL, 7, 0, 0), | |
4030 | GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl", | |
4031 | ENABLE_PCLK_MSCL, 6, 0, 0), | |
4032 | GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl", | |
4033 | ENABLE_PCLK_MSCL, 5, 0, 0), | |
4034 | GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl", | |
4035 | ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0), | |
4036 | GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl", | |
4037 | ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0), | |
4038 | GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl", | |
4039 | ENABLE_PCLK_MSCL, 2, 0, 0), | |
4040 | GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl", | |
4041 | ENABLE_PCLK_MSCL, 1, 0, 0), | |
4042 | GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl", | |
4043 | ENABLE_PCLK_MSCL, 0, 0, 0), | |
4044 | ||
4045 | /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */ | |
4046 | GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl", | |
4047 | ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0, | |
4048 | 0, CLK_IGNORE_UNUSED, 0), | |
4049 | ||
4050 | /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */ | |
4051 | GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl", | |
4052 | ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1, | |
4053 | 0, CLK_IGNORE_UNUSED, 0), | |
4054 | ||
4055 | /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */ | |
4056 | GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl", | |
4057 | ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG, | |
4058 | 0, CLK_IGNORE_UNUSED, 0), | |
4059 | ||
4060 | /* ENABLE_SCLK_MSCL */ | |
4061 | GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0, | |
4062 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), | |
4063 | }; | |
4064 | ||
4065 | static struct samsung_cmu_info mscl_cmu_info __initdata = { | |
4066 | .mux_clks = mscl_mux_clks, | |
4067 | .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), | |
4068 | .div_clks = mscl_div_clks, | |
4069 | .nr_div_clks = ARRAY_SIZE(mscl_div_clks), | |
4070 | .gate_clks = mscl_gate_clks, | |
4071 | .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks), | |
4072 | .nr_clk_ids = MSCL_NR_CLK, | |
4073 | .clk_regs = mscl_clk_regs, | |
4074 | .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs), | |
4075 | }; | |
4076 | ||
4077 | static void __init exynos5433_cmu_mscl_init(struct device_node *np) | |
4078 | { | |
4079 | samsung_cmu_register_one(np, &mscl_cmu_info); | |
4080 | } | |
4081 | CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl", | |
4082 | exynos5433_cmu_mscl_init); | |
9910b6bb CC |
4083 | |
4084 | /* | |
4085 | * Register offset definitions for CMU_MFC | |
4086 | */ | |
4087 | #define MUX_SEL_MFC 0x0200 | |
4088 | #define MUX_ENABLE_MFC 0x0300 | |
4089 | #define MUX_STAT_MFC 0x0400 | |
4090 | #define DIV_MFC 0x0600 | |
4091 | #define DIV_STAT_MFC 0x0700 | |
4092 | #define ENABLE_ACLK_MFC 0x0800 | |
4093 | #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804 | |
4094 | #define ENABLE_PCLK_MFC 0x0900 | |
4095 | #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904 | |
4096 | #define ENABLE_IP_MFC0 0x0b00 | |
4097 | #define ENABLE_IP_MFC1 0x0b04 | |
4098 | #define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08 | |
4099 | ||
4100 | static unsigned long mfc_clk_regs[] __initdata = { | |
4101 | MUX_SEL_MFC, | |
4102 | MUX_ENABLE_MFC, | |
4103 | MUX_STAT_MFC, | |
4104 | DIV_MFC, | |
4105 | DIV_STAT_MFC, | |
4106 | ENABLE_ACLK_MFC, | |
4107 | ENABLE_ACLK_MFC_SECURE_SMMU_MFC, | |
4108 | ENABLE_PCLK_MFC, | |
4109 | ENABLE_PCLK_MFC_SECURE_SMMU_MFC, | |
4110 | ENABLE_IP_MFC0, | |
4111 | ENABLE_IP_MFC1, | |
4112 | ENABLE_IP_MFC_SECURE_SMMU_MFC, | |
4113 | }; | |
4114 | ||
4115 | PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", }; | |
4116 | ||
4117 | static struct samsung_mux_clock mfc_mux_clks[] __initdata = { | |
4118 | /* MUX_SEL_MFC */ | |
4119 | MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user", | |
4120 | mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0), | |
4121 | }; | |
4122 | ||
4123 | static struct samsung_div_clock mfc_div_clks[] __initdata = { | |
4124 | /* DIV_MFC */ | |
4125 | DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user", | |
4126 | DIV_MFC, 0, 2), | |
4127 | }; | |
4128 | ||
4129 | static struct samsung_gate_clock mfc_gate_clks[] __initdata = { | |
4130 | /* ENABLE_ACLK_MFC */ | |
4131 | GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user", | |
4132 | ENABLE_ACLK_MFC, 6, 0, 0), | |
4133 | GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user", | |
4134 | ENABLE_ACLK_MFC, 5, 0, 0), | |
4135 | GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc", | |
4136 | ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0), | |
4137 | GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user", | |
4138 | ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0), | |
4139 | GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc", | |
4140 | ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0), | |
4141 | GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user", | |
4142 | ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0), | |
4143 | GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user", | |
4144 | ENABLE_ACLK_MFC, 0, 0, 0), | |
4145 | ||
4146 | /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */ | |
4147 | GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user", | |
4148 | ENABLE_ACLK_MFC_SECURE_SMMU_MFC, | |
4149 | 1, CLK_IGNORE_UNUSED, 0), | |
4150 | GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user", | |
4151 | ENABLE_ACLK_MFC_SECURE_SMMU_MFC, | |
4152 | 0, CLK_IGNORE_UNUSED, 0), | |
4153 | ||
4154 | /* ENABLE_PCLK_MFC */ | |
4155 | GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc", | |
4156 | ENABLE_PCLK_MFC, 4, 0, 0), | |
4157 | GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc", | |
4158 | ENABLE_PCLK_MFC, 3, 0, 0), | |
4159 | GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc", | |
4160 | ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0), | |
4161 | GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc", | |
4162 | ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0), | |
4163 | GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc", | |
4164 | ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0), | |
4165 | ||
4166 | /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */ | |
4167 | GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc", | |
4168 | ENABLE_PCLK_MFC_SECURE_SMMU_MFC, | |
4169 | 1, CLK_IGNORE_UNUSED, 0), | |
4170 | GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc", | |
4171 | ENABLE_PCLK_MFC_SECURE_SMMU_MFC, | |
4172 | 0, CLK_IGNORE_UNUSED, 0), | |
4173 | }; | |
4174 | ||
4175 | static struct samsung_cmu_info mfc_cmu_info __initdata = { | |
4176 | .mux_clks = mfc_mux_clks, | |
4177 | .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks), | |
4178 | .div_clks = mfc_div_clks, | |
4179 | .nr_div_clks = ARRAY_SIZE(mfc_div_clks), | |
4180 | .gate_clks = mfc_gate_clks, | |
4181 | .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks), | |
4182 | .nr_clk_ids = MFC_NR_CLK, | |
4183 | .clk_regs = mfc_clk_regs, | |
4184 | .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs), | |
4185 | }; | |
4186 | ||
4187 | static void __init exynos5433_cmu_mfc_init(struct device_node *np) | |
4188 | { | |
4189 | samsung_cmu_register_one(np, &mfc_cmu_info); | |
4190 | } | |
4191 | CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc", | |
4192 | exynos5433_cmu_mfc_init); | |
45e58aa5 CC |
4193 | |
4194 | /* | |
4195 | * Register offset definitions for CMU_HEVC | |
4196 | */ | |
4197 | #define MUX_SEL_HEVC 0x0200 | |
4198 | #define MUX_ENABLE_HEVC 0x0300 | |
4199 | #define MUX_STAT_HEVC 0x0400 | |
4200 | #define DIV_HEVC 0x0600 | |
4201 | #define DIV_STAT_HEVC 0x0700 | |
4202 | #define ENABLE_ACLK_HEVC 0x0800 | |
4203 | #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804 | |
4204 | #define ENABLE_PCLK_HEVC 0x0900 | |
4205 | #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904 | |
4206 | #define ENABLE_IP_HEVC0 0x0b00 | |
4207 | #define ENABLE_IP_HEVC1 0x0b04 | |
4208 | #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08 | |
4209 | ||
4210 | static unsigned long hevc_clk_regs[] __initdata = { | |
4211 | MUX_SEL_HEVC, | |
4212 | MUX_ENABLE_HEVC, | |
4213 | MUX_STAT_HEVC, | |
4214 | DIV_HEVC, | |
4215 | DIV_STAT_HEVC, | |
4216 | ENABLE_ACLK_HEVC, | |
4217 | ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC, | |
4218 | ENABLE_PCLK_HEVC, | |
4219 | ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC, | |
4220 | ENABLE_IP_HEVC0, | |
4221 | ENABLE_IP_HEVC1, | |
4222 | ENABLE_IP_HEVC_SECURE_SMMU_HEVC, | |
4223 | }; | |
4224 | ||
4225 | PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", }; | |
4226 | ||
4227 | static struct samsung_mux_clock hevc_mux_clks[] __initdata = { | |
4228 | /* MUX_SEL_HEVC */ | |
4229 | MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user", | |
4230 | mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0), | |
4231 | }; | |
4232 | ||
4233 | static struct samsung_div_clock hevc_div_clks[] __initdata = { | |
4234 | /* DIV_HEVC */ | |
4235 | DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user", | |
4236 | DIV_HEVC, 0, 2), | |
4237 | }; | |
4238 | ||
4239 | static struct samsung_gate_clock hevc_gate_clks[] __initdata = { | |
4240 | /* ENABLE_ACLK_HEVC */ | |
4241 | GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user", | |
4242 | ENABLE_ACLK_HEVC, 6, 0, 0), | |
4243 | GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user", | |
4244 | ENABLE_ACLK_HEVC, 5, 0, 0), | |
4245 | GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc", | |
4246 | ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0), | |
4247 | GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user", | |
4248 | ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0), | |
4249 | GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc", | |
4250 | ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0), | |
4251 | GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user", | |
4252 | ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0), | |
4253 | GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user", | |
4254 | ENABLE_ACLK_HEVC, 0, 0, 0), | |
4255 | ||
4256 | /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */ | |
4257 | GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1", | |
4258 | "mout_aclk_hevc_400_user", | |
4259 | ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC, | |
4260 | 1, CLK_IGNORE_UNUSED, 0), | |
4261 | GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0", | |
4262 | "mout_aclk_hevc_400_user", | |
4263 | ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC, | |
4264 | 0, CLK_IGNORE_UNUSED, 0), | |
4265 | ||
4266 | /* ENABLE_PCLK_HEVC */ | |
4267 | GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc", | |
4268 | ENABLE_PCLK_HEVC, 4, 0, 0), | |
4269 | GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc", | |
4270 | ENABLE_PCLK_HEVC, 3, 0, 0), | |
4271 | GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc", | |
4272 | ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0), | |
4273 | GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc", | |
4274 | ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0), | |
4275 | GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc", | |
4276 | ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0), | |
4277 | ||
4278 | /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */ | |
4279 | GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc", | |
4280 | ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC, | |
4281 | 1, CLK_IGNORE_UNUSED, 0), | |
4282 | GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc", | |
4283 | ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC, | |
4284 | 0, CLK_IGNORE_UNUSED, 0), | |
4285 | }; | |
4286 | ||
4287 | static struct samsung_cmu_info hevc_cmu_info __initdata = { | |
4288 | .mux_clks = hevc_mux_clks, | |
4289 | .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks), | |
4290 | .div_clks = hevc_div_clks, | |
4291 | .nr_div_clks = ARRAY_SIZE(hevc_div_clks), | |
4292 | .gate_clks = hevc_gate_clks, | |
4293 | .nr_gate_clks = ARRAY_SIZE(hevc_gate_clks), | |
4294 | .nr_clk_ids = HEVC_NR_CLK, | |
4295 | .clk_regs = hevc_clk_regs, | |
4296 | .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs), | |
4297 | }; | |
4298 | ||
4299 | static void __init exynos5433_cmu_hevc_init(struct device_node *np) | |
4300 | { | |
4301 | samsung_cmu_register_one(np, &hevc_cmu_info); | |
4302 | } | |
4303 | CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc", | |
4304 | exynos5433_cmu_hevc_init); | |
8e46c4b8 CC |
4305 | |
4306 | /* | |
4307 | * Register offset definitions for CMU_ISP | |
4308 | */ | |
4309 | #define MUX_SEL_ISP 0x0200 | |
4310 | #define MUX_ENABLE_ISP 0x0300 | |
4311 | #define MUX_STAT_ISP 0x0400 | |
4312 | #define DIV_ISP 0x0600 | |
4313 | #define DIV_STAT_ISP 0x0700 | |
4314 | #define ENABLE_ACLK_ISP0 0x0800 | |
4315 | #define ENABLE_ACLK_ISP1 0x0804 | |
4316 | #define ENABLE_ACLK_ISP2 0x0808 | |
4317 | #define ENABLE_PCLK_ISP 0x0900 | |
4318 | #define ENABLE_SCLK_ISP 0x0a00 | |
4319 | #define ENABLE_IP_ISP0 0x0b00 | |
4320 | #define ENABLE_IP_ISP1 0x0b04 | |
4321 | #define ENABLE_IP_ISP2 0x0b08 | |
4322 | #define ENABLE_IP_ISP3 0x0b0c | |
4323 | ||
4324 | static unsigned long isp_clk_regs[] __initdata = { | |
4325 | MUX_SEL_ISP, | |
4326 | MUX_ENABLE_ISP, | |
4327 | MUX_STAT_ISP, | |
4328 | DIV_ISP, | |
4329 | DIV_STAT_ISP, | |
4330 | ENABLE_ACLK_ISP0, | |
4331 | ENABLE_ACLK_ISP1, | |
4332 | ENABLE_ACLK_ISP2, | |
4333 | ENABLE_PCLK_ISP, | |
4334 | ENABLE_SCLK_ISP, | |
4335 | ENABLE_IP_ISP0, | |
4336 | ENABLE_IP_ISP1, | |
4337 | ENABLE_IP_ISP2, | |
4338 | ENABLE_IP_ISP3, | |
4339 | }; | |
4340 | ||
4341 | PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", }; | |
4342 | PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", }; | |
4343 | ||
4344 | static struct samsung_mux_clock isp_mux_clks[] __initdata = { | |
4345 | /* MUX_SEL_ISP */ | |
4346 | MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user", | |
4347 | mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0), | |
4348 | MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user", | |
4349 | mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0), | |
4350 | }; | |
4351 | ||
4352 | static struct samsung_div_clock isp_div_clks[] __initdata = { | |
4353 | /* DIV_ISP */ | |
4354 | DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis", | |
4355 | "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3), | |
4356 | DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user", | |
4357 | DIV_ISP, 8, 3), | |
4358 | DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200", | |
4359 | "mout_aclk_isp_400_user", DIV_ISP, 4, 3), | |
4360 | DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200", | |
4361 | "mout_aclk_isp_400_user", DIV_ISP, 0, 3), | |
4362 | }; | |
4363 | ||
4364 | static struct samsung_gate_clock isp_gate_clks[] __initdata = { | |
4365 | /* ENABLE_ACLK_ISP0 */ | |
4366 | GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user", | |
4367 | ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0), | |
4368 | GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user", | |
4369 | ENABLE_ACLK_ISP0, 5, 0, 0), | |
4370 | GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user", | |
4371 | ENABLE_ACLK_ISP0, 4, 0, 0), | |
4372 | GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user", | |
4373 | ENABLE_ACLK_ISP0, 3, 0, 0), | |
4374 | GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user", | |
4375 | ENABLE_ACLK_ISP0, 2, 0, 0), | |
4376 | GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user", | |
4377 | ENABLE_ACLK_ISP0, 1, 0, 0), | |
4378 | GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user", | |
4379 | ENABLE_ACLK_ISP0, 0, 0, 0), | |
4380 | ||
4381 | /* ENABLE_ACLK_ISP1 */ | |
4382 | GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp", | |
4383 | "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, | |
4384 | 17, CLK_IGNORE_UNUSED, 0), | |
4385 | GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc", | |
4386 | "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, | |
4387 | 16, CLK_IGNORE_UNUSED, 0), | |
4388 | GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc", | |
4389 | "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, | |
4390 | 15, CLK_IGNORE_UNUSED, 0), | |
4391 | GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p", | |
4392 | "div_pclk_isp", ENABLE_ACLK_ISP1, | |
4393 | 14, CLK_IGNORE_UNUSED, 0), | |
4394 | GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p", | |
4395 | "div_pclk_isp", ENABLE_ACLK_ISP1, | |
4396 | 13, CLK_IGNORE_UNUSED, 0), | |
4397 | GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1", | |
4398 | "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1, | |
4399 | 12, CLK_IGNORE_UNUSED, 0), | |
4400 | GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0", | |
4401 | "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1, | |
4402 | 11, CLK_IGNORE_UNUSED, 0), | |
4403 | GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1", | |
4404 | "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, | |
4405 | 10, CLK_IGNORE_UNUSED, 0), | |
4406 | GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0", | |
4407 | "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, | |
4408 | 9, CLK_IGNORE_UNUSED, 0), | |
4409 | GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p", | |
4410 | "div_aclk_isp_d_200", ENABLE_ACLK_ISP1, | |
4411 | 8, CLK_IGNORE_UNUSED, 0), | |
4412 | GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p", | |
4413 | "div_aclk_isp_c_200", ENABLE_ACLK_ISP1, | |
4414 | 7, CLK_IGNORE_UNUSED, 0), | |
4415 | GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp", | |
4416 | ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0), | |
4417 | GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp", | |
4418 | ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0), | |
4419 | GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p", | |
4420 | "div_aclk_isp_d_200", ENABLE_ACLK_ISP1, | |
4421 | 4, CLK_IGNORE_UNUSED, 0), | |
4422 | GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p", | |
4423 | "div_aclk_isp_c_200", ENABLE_ACLK_ISP1, | |
4424 | 3, CLK_IGNORE_UNUSED, 0), | |
4425 | GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user", | |
4426 | ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0), | |
4427 | GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user", | |
4428 | ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0), | |
4429 | GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user", | |
4430 | ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0), | |
4431 | ||
4432 | /* ENABLE_ACLK_ISP2 */ | |
4433 | GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp", | |
4434 | "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, | |
4435 | 13, CLK_IGNORE_UNUSED, 0), | |
4436 | GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user", | |
4437 | ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0), | |
4438 | GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user", | |
4439 | ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0), | |
4440 | GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user", | |
4441 | ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0), | |
4442 | GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc", | |
4443 | "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, | |
4444 | 9, CLK_IGNORE_UNUSED, 0), | |
4445 | GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user", | |
4446 | ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0), | |
4447 | GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user", | |
4448 | ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0), | |
4449 | GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp", | |
4450 | "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, | |
4451 | 6, CLK_IGNORE_UNUSED, 0), | |
4452 | GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user", | |
4453 | ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0), | |
4454 | GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user", | |
4455 | ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0), | |
4456 | GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user", | |
4457 | ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0), | |
4458 | GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc", | |
4459 | "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, | |
4460 | 2, CLK_IGNORE_UNUSED, 0), | |
4461 | GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user", | |
4462 | ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0), | |
4463 | GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user", | |
4464 | ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0), | |
4465 | ||
4466 | /* ENABLE_PCLK_ISP */ | |
4467 | GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200", | |
4468 | ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0), | |
4469 | GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200", | |
4470 | ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0), | |
4471 | GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200", | |
4472 | ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0), | |
4473 | GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200", | |
4474 | ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0), | |
4475 | GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200", | |
4476 | ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0), | |
4477 | GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200", | |
4478 | ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0), | |
4479 | GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200", | |
4480 | ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0), | |
4481 | GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp", | |
4482 | ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0), | |
4483 | GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp", | |
4484 | ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0), | |
4485 | GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp", | |
4486 | ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0), | |
4487 | GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp", | |
4488 | ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0), | |
4489 | GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp", | |
4490 | ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0), | |
4491 | GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp", | |
4492 | ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0), | |
4493 | GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp", | |
4494 | ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0), | |
4495 | GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp", | |
4496 | ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0), | |
4497 | GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp", | |
4498 | ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0), | |
4499 | GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp", | |
4500 | ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0), | |
4501 | GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp", | |
4502 | ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0), | |
4503 | GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local", | |
4504 | "div_aclk_isp_c_200", ENABLE_PCLK_ISP, | |
4505 | 7, CLK_IGNORE_UNUSED, 0), | |
4506 | GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200", | |
4507 | ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0), | |
4508 | GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200", | |
4509 | ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0), | |
4510 | GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis", | |
4511 | ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0), | |
4512 | GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200", | |
4513 | ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0), | |
4514 | GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200", | |
4515 | ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0), | |
4516 | GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200", | |
4517 | ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0), | |
4518 | GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200", | |
4519 | ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0), | |
4520 | ||
4521 | /* ENABLE_SCLK_ISP */ | |
4522 | GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis", | |
4523 | "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP, | |
4524 | 5, CLK_IGNORE_UNUSED, 0), | |
4525 | GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis", | |
4526 | "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP, | |
4527 | 4, CLK_IGNORE_UNUSED, 0), | |
4528 | GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp", | |
4529 | "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, | |
4530 | 3, CLK_IGNORE_UNUSED, 0), | |
4531 | GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd", | |
4532 | "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, | |
4533 | 2, CLK_IGNORE_UNUSED, 0), | |
4534 | GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc", | |
4535 | "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, | |
4536 | 1, CLK_IGNORE_UNUSED, 0), | |
4537 | GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc", | |
4538 | "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, | |
4539 | 0, CLK_IGNORE_UNUSED, 0), | |
4540 | }; | |
4541 | ||
4542 | static struct samsung_cmu_info isp_cmu_info __initdata = { | |
4543 | .mux_clks = isp_mux_clks, | |
4544 | .nr_mux_clks = ARRAY_SIZE(isp_mux_clks), | |
4545 | .div_clks = isp_div_clks, | |
4546 | .nr_div_clks = ARRAY_SIZE(isp_div_clks), | |
4547 | .gate_clks = isp_gate_clks, | |
4548 | .nr_gate_clks = ARRAY_SIZE(isp_gate_clks), | |
4549 | .nr_clk_ids = ISP_NR_CLK, | |
4550 | .clk_regs = isp_clk_regs, | |
4551 | .nr_clk_regs = ARRAY_SIZE(isp_clk_regs), | |
4552 | }; | |
4553 | ||
4554 | static void __init exynos5433_cmu_isp_init(struct device_node *np) | |
4555 | { | |
4556 | samsung_cmu_register_one(np, &isp_cmu_info); | |
4557 | } | |
4558 | CLK_OF_DECLARE(exynos5433_cmu_isp, "samsung,exynos5433-cmu-isp", | |
4559 | exynos5433_cmu_isp_init); | |
6958f22f CC |
4560 | |
4561 | /* | |
4562 | * Register offset definitions for CMU_CAM0 | |
4563 | */ | |
4564 | #define MUX_SEL_CAM00 0x0200 | |
4565 | #define MUX_SEL_CAM01 0x0204 | |
4566 | #define MUX_SEL_CAM02 0x0208 | |
4567 | #define MUX_SEL_CAM03 0x020c | |
4568 | #define MUX_SEL_CAM04 0x0210 | |
4569 | #define MUX_ENABLE_CAM00 0x0300 | |
4570 | #define MUX_ENABLE_CAM01 0x0304 | |
4571 | #define MUX_ENABLE_CAM02 0x0308 | |
4572 | #define MUX_ENABLE_CAM03 0x030c | |
4573 | #define MUX_ENABLE_CAM04 0x0310 | |
4574 | #define MUX_STAT_CAM00 0x0400 | |
4575 | #define MUX_STAT_CAM01 0x0404 | |
4576 | #define MUX_STAT_CAM02 0x0408 | |
4577 | #define MUX_STAT_CAM03 0x040c | |
4578 | #define MUX_STAT_CAM04 0x0410 | |
4579 | #define MUX_IGNORE_CAM01 0x0504 | |
4580 | #define DIV_CAM00 0x0600 | |
4581 | #define DIV_CAM01 0x0604 | |
4582 | #define DIV_CAM02 0x0608 | |
4583 | #define DIV_CAM03 0x060c | |
4584 | #define DIV_STAT_CAM00 0x0700 | |
4585 | #define DIV_STAT_CAM01 0x0704 | |
4586 | #define DIV_STAT_CAM02 0x0708 | |
4587 | #define DIV_STAT_CAM03 0x070c | |
4588 | #define ENABLE_ACLK_CAM00 0X0800 | |
4589 | #define ENABLE_ACLK_CAM01 0X0804 | |
4590 | #define ENABLE_ACLK_CAM02 0X0808 | |
4591 | #define ENABLE_PCLK_CAM0 0X0900 | |
4592 | #define ENABLE_SCLK_CAM0 0X0a00 | |
4593 | #define ENABLE_IP_CAM00 0X0b00 | |
4594 | #define ENABLE_IP_CAM01 0X0b04 | |
4595 | #define ENABLE_IP_CAM02 0X0b08 | |
4596 | #define ENABLE_IP_CAM03 0X0b0C | |
4597 | ||
4598 | static unsigned long cam0_clk_regs[] __initdata = { | |
4599 | MUX_SEL_CAM00, | |
4600 | MUX_SEL_CAM01, | |
4601 | MUX_SEL_CAM02, | |
4602 | MUX_SEL_CAM03, | |
4603 | MUX_SEL_CAM04, | |
4604 | MUX_ENABLE_CAM00, | |
4605 | MUX_ENABLE_CAM01, | |
4606 | MUX_ENABLE_CAM02, | |
4607 | MUX_ENABLE_CAM03, | |
4608 | MUX_ENABLE_CAM04, | |
4609 | MUX_STAT_CAM00, | |
4610 | MUX_STAT_CAM01, | |
4611 | MUX_STAT_CAM02, | |
4612 | MUX_STAT_CAM03, | |
4613 | MUX_STAT_CAM04, | |
4614 | MUX_IGNORE_CAM01, | |
4615 | DIV_CAM00, | |
4616 | DIV_CAM01, | |
4617 | DIV_CAM02, | |
4618 | DIV_CAM03, | |
4619 | DIV_STAT_CAM00, | |
4620 | DIV_STAT_CAM01, | |
4621 | DIV_STAT_CAM02, | |
4622 | DIV_STAT_CAM03, | |
4623 | ENABLE_ACLK_CAM00, | |
4624 | ENABLE_ACLK_CAM01, | |
4625 | ENABLE_ACLK_CAM02, | |
4626 | ENABLE_PCLK_CAM0, | |
4627 | ENABLE_SCLK_CAM0, | |
4628 | ENABLE_IP_CAM00, | |
4629 | ENABLE_IP_CAM01, | |
4630 | ENABLE_IP_CAM02, | |
4631 | ENABLE_IP_CAM03, | |
4632 | }; | |
4633 | PNAME(mout_aclk_cam0_333_user_p) = { "oscclk", "aclk_cam0_333", }; | |
4634 | PNAME(mout_aclk_cam0_400_user_p) = { "oscclk", "aclk_cam0_400", }; | |
4635 | PNAME(mout_aclk_cam0_552_user_p) = { "oscclk", "aclk_cam0_552", }; | |
4636 | ||
4637 | PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk", | |
4638 | "phyclk_rxbyteclkhs0_s4_phy", }; | |
4639 | PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk", | |
4640 | "phyclk_rxbyteclkhs0_s2a_phy", }; | |
4641 | ||
4642 | PNAME(mout_aclk_lite_d_b_p) = { "mout_aclk_lite_d_a", | |
4643 | "mout_aclk_cam0_333_user", }; | |
4644 | PNAME(mout_aclk_lite_d_a_p) = { "mout_aclk_cam0_552_user", | |
4645 | "mout_aclk_cam0_400_user", }; | |
4646 | PNAME(mout_aclk_lite_b_b_p) = { "mout_aclk_lite_b_a", | |
4647 | "mout_aclk_cam0_333_user", }; | |
4648 | PNAME(mout_aclk_lite_b_a_p) = { "mout_aclk_cam0_552_user", | |
4649 | "mout_aclk_cam0_400_user", }; | |
4650 | PNAME(mout_aclk_lite_a_b_p) = { "mout_aclk_lite_a_a", | |
4651 | "mout_aclk_cam0_333_user", }; | |
4652 | PNAME(mout_aclk_lite_a_a_p) = { "mout_aclk_cam0_552_user", | |
4653 | "mout_aclk_cam0_400_user", }; | |
4654 | PNAME(mout_aclk_cam0_400_p) = { "mout_aclk_cam0_400_user", | |
4655 | "mout_aclk_cam0_333_user", }; | |
4656 | ||
4657 | PNAME(mout_aclk_csis1_b_p) = { "mout_aclk_csis1_a", | |
4658 | "mout_aclk_cam0_333_user" }; | |
4659 | PNAME(mout_aclk_csis1_a_p) = { "mout_aclk_cam0_552_user", | |
4660 | "mout_aclk_cam0_400_user", }; | |
4661 | PNAME(mout_aclk_csis0_b_p) = { "mout_aclk_csis0_a", | |
4662 | "mout_aclk_cam0_333_user", }; | |
4663 | PNAME(mout_aclk_csis0_a_p) = { "mout_aclk_cam0_552_user", | |
4664 | "mout_aclk-cam0_400_user", }; | |
4665 | PNAME(mout_aclk_3aa1_b_p) = { "mout_aclk_3aa1_a", | |
4666 | "mout_aclk_cam0_333_user", }; | |
4667 | PNAME(mout_aclk_3aa1_a_p) = { "mout_aclk_cam0_552_user", | |
4668 | "mout_aclk_cam0_400_user", }; | |
4669 | PNAME(mout_aclk_3aa0_b_p) = { "mout_aclk_3aa0_a", | |
4670 | "mout_aclk_cam0_333_user", }; | |
4671 | PNAME(mout_aclk_3aa0_a_p) = { "mout_aclk_cam0_552_user", | |
4672 | "mout_aclk_cam0_400_user", }; | |
4673 | ||
4674 | PNAME(mout_sclk_lite_freecnt_c_p) = { "mout_sclk_lite_freecnt_b", | |
4675 | "div_pclk_lite_d", }; | |
4676 | PNAME(mout_sclk_lite_freecnt_b_p) = { "mout_sclk_lite_freecnt_a", | |
4677 | "div_pclk_pixelasync_lite_c", }; | |
4678 | PNAME(mout_sclk_lite_freecnt_a_p) = { "div_pclk_lite_a", | |
4679 | "div_pclk_lite_b", }; | |
4680 | PNAME(mout_sclk_pixelasync_lite_c_b_p) = { "mout_sclk_pixelasync_lite_c_a", | |
4681 | "mout_aclk_cam0_333_user", }; | |
4682 | PNAME(mout_sclk_pixelasync_lite_c_a_p) = { "mout_aclk_cam0_552_user", | |
4683 | "mout_aclk_cam0_400_user", }; | |
4684 | PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = { | |
4685 | "mout_sclk_pixelasync_lite_c_init_a", | |
4686 | "mout_aclk_cam0_400_user", }; | |
4687 | PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = { | |
4688 | "mout_aclk_cam0_552_user", | |
4689 | "mout_aclk_cam0_400_user", }; | |
4690 | ||
4691 | static struct samsung_fixed_rate_clock cam0_fixed_clks[] __initdata = { | |
4692 | FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy", | |
4693 | NULL, CLK_IS_ROOT, 100000000), | |
4694 | FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy", | |
4695 | NULL, CLK_IS_ROOT, 100000000), | |
4696 | }; | |
4697 | ||
4698 | static struct samsung_mux_clock cam0_mux_clks[] __initdata = { | |
4699 | /* MUX_SEL_CAM00 */ | |
4700 | MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user", | |
4701 | mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1), | |
4702 | MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user", | |
4703 | mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1), | |
4704 | MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user", | |
4705 | mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1), | |
4706 | ||
4707 | /* MUX_SEL_CAM01 */ | |
4708 | MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER, | |
4709 | "mout_phyclk_rxbyteclkhs0_s4_user", | |
4710 | mout_phyclk_rxbyteclkhs0_s4_user_p, | |
4711 | MUX_SEL_CAM01, 4, 1), | |
4712 | MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER, | |
4713 | "mout_phyclk_rxbyteclkhs0_s2a_user", | |
4714 | mout_phyclk_rxbyteclkhs0_s2a_user_p, | |
4715 | MUX_SEL_CAM01, 0, 1), | |
4716 | ||
4717 | /* MUX_SEL_CAM02 */ | |
4718 | MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p, | |
4719 | MUX_SEL_CAM02, 24, 1), | |
4720 | MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p, | |
4721 | MUX_SEL_CAM02, 20, 1), | |
4722 | MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p, | |
4723 | MUX_SEL_CAM02, 16, 1), | |
4724 | MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p, | |
4725 | MUX_SEL_CAM02, 12, 1), | |
4726 | MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p, | |
4727 | MUX_SEL_CAM02, 8, 1), | |
4728 | MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p, | |
4729 | MUX_SEL_CAM02, 4, 1), | |
4730 | MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p, | |
4731 | MUX_SEL_CAM02, 0, 1), | |
4732 | ||
4733 | /* MUX_SEL_CAM03 */ | |
4734 | MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p, | |
4735 | MUX_SEL_CAM03, 28, 1), | |
4736 | MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p, | |
4737 | MUX_SEL_CAM03, 24, 1), | |
4738 | MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p, | |
4739 | MUX_SEL_CAM03, 20, 1), | |
4740 | MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p, | |
4741 | MUX_SEL_CAM03, 16, 1), | |
4742 | MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p, | |
4743 | MUX_SEL_CAM03, 12, 1), | |
4744 | MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p, | |
4745 | MUX_SEL_CAM03, 8, 1), | |
4746 | MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p, | |
4747 | MUX_SEL_CAM03, 4, 1), | |
4748 | MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p, | |
4749 | MUX_SEL_CAM03, 0, 1), | |
4750 | ||
4751 | /* MUX_SEL_CAM04 */ | |
4752 | MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c", | |
4753 | mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1), | |
4754 | MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b", | |
4755 | mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 24, 1), | |
4756 | MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a", | |
4757 | mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 24, 1), | |
4758 | MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b", | |
4759 | mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 24, 1), | |
4760 | MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a", | |
4761 | mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 24, 1), | |
4762 | MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B, | |
4763 | "mout_sclk_pixelasync_lite_c_init_b", | |
4764 | mout_sclk_pixelasync_lite_c_init_b_p, | |
4765 | MUX_SEL_CAM04, 24, 1), | |
4766 | MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A, | |
4767 | "mout_sclk_pixelasync_lite_c_init_a", | |
4768 | mout_sclk_pixelasync_lite_c_init_a_p, | |
4769 | MUX_SEL_CAM04, 24, 1), | |
4770 | }; | |
4771 | ||
4772 | static struct samsung_div_clock cam0_div_clks[] __initdata = { | |
4773 | /* DIV_CAM00 */ | |
4774 | DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200", | |
4775 | DIV_CAM00, 8, 2), | |
4776 | DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400", | |
4777 | DIV_CAM00, 4, 3), | |
4778 | DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400", | |
4779 | "mout_aclk_cam0_400", DIV_CAM00, 0, 3), | |
4780 | ||
4781 | /* DIV_CAM01 */ | |
4782 | DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d", | |
4783 | DIV_CAM01, 20, 2), | |
4784 | DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b", | |
4785 | DIV_CAM01, 16, 3), | |
4786 | DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b", | |
4787 | DIV_CAM01, 12, 2), | |
4788 | DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b", | |
4789 | DIV_CAM01, 8, 3), | |
4790 | DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a", | |
4791 | DIV_CAM01, 4, 2), | |
4792 | DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b", | |
4793 | DIV_CAM01, 0, 3), | |
4794 | ||
4795 | /* DIV_CAM02 */ | |
4796 | DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b", | |
4797 | DIV_CAM02, 20, 3), | |
4798 | DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b", | |
4799 | DIV_CAM02, 16, 3), | |
4800 | DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1", | |
4801 | DIV_CAM02, 12, 2), | |
4802 | DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b", | |
4803 | DIV_CAM02, 8, 3), | |
4804 | DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0", | |
4805 | DIV_CAM02, 4, 2), | |
4806 | DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b", | |
4807 | DIV_CAM02, 0, 3), | |
4808 | ||
4809 | /* DIV_CAM03 */ | |
4810 | DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c", | |
4811 | "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3), | |
4812 | DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c", | |
4813 | "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2), | |
4814 | DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT, | |
4815 | "div_sclk_pixelasync_lite_c_init", | |
4816 | "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3), | |
4817 | }; | |
4818 | ||
4819 | static struct samsung_gate_clock cam0_gate_clks[] __initdata = { | |
4820 | /* ENABLE_ACLK_CAM00 */ | |
4821 | GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00, | |
4822 | 6, 0, 0), | |
4823 | GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00, | |
4824 | 5, 0, 0), | |
4825 | GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00, | |
4826 | 4, 0, 0), | |
4827 | GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00, | |
4828 | 3, 0, 0), | |
4829 | GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d", | |
4830 | ENABLE_ACLK_CAM00, 2, 0, 0), | |
4831 | GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b", | |
4832 | ENABLE_ACLK_CAM00, 1, 0, 0), | |
4833 | GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a", | |
4834 | ENABLE_ACLK_CAM00, 0, 0, 0), | |
4835 | ||
4836 | /* ENABLE_ACLK_CAM01 */ | |
4837 | GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200", | |
4838 | ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0), | |
4839 | GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400", | |
4840 | ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0), | |
4841 | GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400", | |
4842 | ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0), | |
4843 | GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400", | |
4844 | ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0), | |
4845 | GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1", | |
4846 | ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0), | |
4847 | GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1", | |
4848 | ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0), | |
4849 | GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0", | |
4850 | ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0), | |
4851 | GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0", | |
4852 | ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0), | |
4853 | GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d", | |
4854 | "div_pclk_lite_d", ENABLE_ACLK_CAM01, | |
4855 | 23, CLK_IGNORE_UNUSED, 0), | |
4856 | GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d", | |
4857 | "div_aclk_cam0_200", ENABLE_ACLK_CAM01, | |
4858 | 22, CLK_IGNORE_UNUSED, 0), | |
4859 | GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b", | |
4860 | "div_pclk_lite_b", ENABLE_ACLK_CAM01, | |
4861 | 21, CLK_IGNORE_UNUSED, 0), | |
4862 | GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b", | |
4863 | "div_aclk_cam0_200", ENABLE_ACLK_CAM01, | |
4864 | 20, CLK_IGNORE_UNUSED, 0), | |
4865 | GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a", | |
4866 | "div_pclk_lite_a", ENABLE_ACLK_CAM01, | |
4867 | 19, CLK_IGNORE_UNUSED, 0), | |
4868 | GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a", | |
4869 | "div_aclk_cam0_200", ENABLE_ACLK_CAM01, | |
4870 | 18, CLK_IGNORE_UNUSED, 0), | |
4871 | GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p", | |
4872 | "div_aclk_cam0_200", ENABLE_ACLK_CAM01, | |
4873 | 17, CLK_IGNORE_UNUSED, 0), | |
4874 | GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1", | |
4875 | "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, | |
4876 | 16, CLK_IGNORE_UNUSED, 0), | |
4877 | GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1", | |
4878 | "div_aclk_3aa1", ENABLE_ACLK_CAM01, | |
4879 | 15, CLK_IGNORE_UNUSED, 0), | |
4880 | GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0", | |
4881 | "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, | |
4882 | 14, CLK_IGNORE_UNUSED, 0), | |
4883 | GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0", | |
4884 | "div_aclk_3aa0", ENABLE_ACLK_CAM01, | |
4885 | 13, CLK_IGNORE_UNUSED, 0), | |
4886 | GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d", | |
4887 | "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, | |
4888 | 12, CLK_IGNORE_UNUSED, 0), | |
4889 | GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d", | |
4890 | "div_aclk_lite_d", ENABLE_ACLK_CAM01, | |
4891 | 11, CLK_IGNORE_UNUSED, 0), | |
4892 | GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b", | |
4893 | "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, | |
4894 | 10, CLK_IGNORE_UNUSED, 0), | |
4895 | GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b", | |
4896 | "div_aclk_lite_b", ENABLE_ACLK_CAM01, | |
4897 | 9, CLK_IGNORE_UNUSED, 0), | |
4898 | GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a", | |
4899 | "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, | |
4900 | 8, CLK_IGNORE_UNUSED, 0), | |
4901 | GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a", | |
4902 | "div_aclk_lite_a", ENABLE_ACLK_CAM01, | |
4903 | 7, CLK_IGNORE_UNUSED, 0), | |
4904 | GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp", | |
4905 | "div_pclk_cam0_50", ENABLE_ACLK_CAM01, | |
4906 | 6, CLK_IGNORE_UNUSED, 0), | |
4907 | GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200", | |
4908 | ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0), | |
4909 | GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200", | |
4910 | ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0), | |
4911 | GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200", | |
4912 | ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0), | |
4913 | GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400", | |
4914 | ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0), | |
4915 | GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200", | |
4916 | ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0), | |
4917 | GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400", | |
4918 | ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0), | |
4919 | ||
4920 | /* ENABLE_ACLK_CAM02 */ | |
4921 | GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400", | |
4922 | ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0), | |
4923 | GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400", | |
4924 | ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0), | |
4925 | GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400", | |
4926 | ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0), | |
4927 | GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400", | |
4928 | ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0), | |
4929 | GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400", | |
4930 | ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0), | |
4931 | GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400", | |
4932 | ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0), | |
4933 | GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400", | |
4934 | ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0), | |
4935 | GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400", | |
4936 | ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0), | |
4937 | GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400", | |
4938 | ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0), | |
4939 | GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400", | |
4940 | ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0), | |
4941 | ||
4942 | /* ENABLE_PCLK_CAM0 */ | |
4943 | GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200", | |
4944 | ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0), | |
4945 | GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200", | |
4946 | ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0), | |
4947 | GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200", | |
4948 | ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0), | |
4949 | GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200", | |
4950 | ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0), | |
4951 | GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200", | |
4952 | ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0), | |
4953 | GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50", | |
4954 | ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0), | |
4955 | GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50", | |
4956 | ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0), | |
4957 | GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50", | |
4958 | ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0), | |
4959 | GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50", | |
4960 | ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0), | |
4961 | GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50", | |
4962 | ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0), | |
4963 | GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50", | |
4964 | ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0), | |
4965 | GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50", | |
4966 | ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0), | |
4967 | GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50", | |
4968 | ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0), | |
4969 | GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d", | |
4970 | "div_pclk_cam0_50", ENABLE_PCLK_CAM0, | |
4971 | 12, CLK_IGNORE_UNUSED, 0), | |
4972 | GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b", | |
4973 | "div_pclk_cam0_50", ENABLE_PCLK_CAM0, | |
4974 | 11, CLK_IGNORE_UNUSED, 0), | |
4975 | GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a", | |
4976 | "div_pclk_cam0_50", ENABLE_PCLK_CAM0, | |
4977 | 10, CLK_IGNORE_UNUSED, 0), | |
4978 | GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50", | |
4979 | ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0), | |
4980 | GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50", | |
4981 | ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0), | |
4982 | GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local", | |
4983 | "div_aclk_cam0_200", ENABLE_PCLK_CAM0, | |
4984 | 7, CLK_IGNORE_UNUSED, 0), | |
4985 | GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200", | |
4986 | ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0), | |
4987 | GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200", | |
4988 | ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0), | |
4989 | GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1", | |
4990 | ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0), | |
4991 | GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0", | |
4992 | ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0), | |
4993 | GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d", | |
4994 | ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0), | |
4995 | GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b", | |
4996 | ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0), | |
4997 | GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a", | |
4998 | ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0), | |
4999 | ||
5000 | /* ENABLE_SCLK_CAM0 */ | |
5001 | GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4", | |
5002 | "mout_phyclk_rxbyteclkhs0_s4_user", | |
5003 | ENABLE_SCLK_CAM0, 8, 0, 0), | |
5004 | GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a", | |
5005 | "mout_phyclk_rxbyteclkhs0_s2a_user", | |
5006 | ENABLE_SCLK_CAM0, 7, 0, 0), | |
5007 | GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt", | |
5008 | "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0), | |
5009 | GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1", | |
5010 | "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0), | |
5011 | GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0", | |
5012 | "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0), | |
5013 | GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0", | |
5014 | "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0), | |
5015 | GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c", | |
5016 | "div_sclk_pixelasync_lite_c", | |
5017 | ENABLE_SCLK_CAM0, 2, 0, 0), | |
5018 | GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init", | |
5019 | "div_sclk_pixelasync_lite_c_init", | |
5020 | ENABLE_SCLK_CAM0, 1, 0, 0), | |
5021 | GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init", | |
5022 | "div_sclk_pixelasync_lite_c", | |
5023 | ENABLE_SCLK_CAM0, 0, 0, 0), | |
5024 | }; | |
5025 | ||
5026 | static struct samsung_cmu_info cam0_cmu_info __initdata = { | |
5027 | .mux_clks = cam0_mux_clks, | |
5028 | .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks), | |
5029 | .div_clks = cam0_div_clks, | |
5030 | .nr_div_clks = ARRAY_SIZE(cam0_div_clks), | |
5031 | .gate_clks = cam0_gate_clks, | |
5032 | .nr_gate_clks = ARRAY_SIZE(cam0_gate_clks), | |
5033 | .fixed_clks = cam0_fixed_clks, | |
5034 | .nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks), | |
5035 | .nr_clk_ids = CAM0_NR_CLK, | |
5036 | .clk_regs = cam0_clk_regs, | |
5037 | .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs), | |
5038 | }; | |
5039 | ||
5040 | static void __init exynos5433_cmu_cam0_init(struct device_node *np) | |
5041 | { | |
5042 | samsung_cmu_register_one(np, &cam0_cmu_info); | |
5043 | } | |
5044 | CLK_OF_DECLARE(exynos5433_cmu_cam0, "samsung,exynos5433-cmu-cam0", | |
5045 | exynos5433_cmu_cam0_init); | |
a5958a93 CC |
5046 | |
5047 | /* | |
5048 | * Register offset definitions for CMU_CAM1 | |
5049 | */ | |
5050 | #define MUX_SEL_CAM10 0x0200 | |
5051 | #define MUX_SEL_CAM11 0x0204 | |
5052 | #define MUX_SEL_CAM12 0x0208 | |
5053 | #define MUX_ENABLE_CAM10 0x0300 | |
5054 | #define MUX_ENABLE_CAM11 0x0304 | |
5055 | #define MUX_ENABLE_CAM12 0x0308 | |
5056 | #define MUX_STAT_CAM10 0x0400 | |
5057 | #define MUX_STAT_CAM11 0x0404 | |
5058 | #define MUX_STAT_CAM12 0x0408 | |
5059 | #define MUX_IGNORE_CAM11 0x0504 | |
5060 | #define DIV_CAM10 0x0600 | |
5061 | #define DIV_CAM11 0x0604 | |
5062 | #define DIV_STAT_CAM10 0x0700 | |
5063 | #define DIV_STAT_CAM11 0x0704 | |
5064 | #define ENABLE_ACLK_CAM10 0X0800 | |
5065 | #define ENABLE_ACLK_CAM11 0X0804 | |
5066 | #define ENABLE_ACLK_CAM12 0X0808 | |
5067 | #define ENABLE_PCLK_CAM1 0X0900 | |
5068 | #define ENABLE_SCLK_CAM1 0X0a00 | |
5069 | #define ENABLE_IP_CAM10 0X0b00 | |
5070 | #define ENABLE_IP_CAM11 0X0b04 | |
5071 | #define ENABLE_IP_CAM12 0X0b08 | |
5072 | ||
5073 | static unsigned long cam1_clk_regs[] __initdata = { | |
5074 | MUX_SEL_CAM10, | |
5075 | MUX_SEL_CAM11, | |
5076 | MUX_SEL_CAM12, | |
5077 | MUX_ENABLE_CAM10, | |
5078 | MUX_ENABLE_CAM11, | |
5079 | MUX_ENABLE_CAM12, | |
5080 | MUX_STAT_CAM10, | |
5081 | MUX_STAT_CAM11, | |
5082 | MUX_STAT_CAM12, | |
5083 | MUX_IGNORE_CAM11, | |
5084 | DIV_CAM10, | |
5085 | DIV_CAM11, | |
5086 | DIV_STAT_CAM10, | |
5087 | DIV_STAT_CAM11, | |
5088 | ENABLE_ACLK_CAM10, | |
5089 | ENABLE_ACLK_CAM11, | |
5090 | ENABLE_ACLK_CAM12, | |
5091 | ENABLE_PCLK_CAM1, | |
5092 | ENABLE_SCLK_CAM1, | |
5093 | ENABLE_IP_CAM10, | |
5094 | ENABLE_IP_CAM11, | |
5095 | ENABLE_IP_CAM12, | |
5096 | }; | |
5097 | ||
5098 | PNAME(mout_sclk_isp_uart_user_p) = { "oscclk", "sclk_isp_uart_cam1", }; | |
5099 | PNAME(mout_sclk_isp_spi1_user_p) = { "oscclk", "sclk_isp_spi1_cam1", }; | |
5100 | PNAME(mout_sclk_isp_spi0_user_p) = { "oscclk", "sclk_isp_spi0_cam1", }; | |
5101 | ||
5102 | PNAME(mout_aclk_cam1_333_user_p) = { "oscclk", "aclk_cam1_333", }; | |
5103 | PNAME(mout_aclk_cam1_400_user_p) = { "oscclk", "aclk_cam1_400", }; | |
5104 | PNAME(mout_aclk_cam1_552_user_p) = { "oscclk", "aclk_cam1_552", }; | |
5105 | ||
5106 | PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk", | |
5107 | "phyclk_rxbyteclkhs0_s2b_phy", }; | |
5108 | ||
5109 | PNAME(mout_aclk_csis2_b_p) = { "mout_aclk_csis2_a", | |
5110 | "mout_aclk_cam1_333_user", }; | |
5111 | PNAME(mout_aclk_csis2_a_p) = { "mout_aclk_cam1_552_user", | |
5112 | "mout_aclk_cam1_400_user", }; | |
5113 | ||
5114 | PNAME(mout_aclk_fd_b_p) = { "mout_aclk_fd_a", | |
5115 | "mout_aclk_cam1_333_user", }; | |
5116 | PNAME(mout_aclk_fd_a_p) = { "mout_aclk_cam1_552_user", | |
5117 | "mout_aclk_cam1_400_user", }; | |
5118 | ||
5119 | PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a", | |
5120 | "mout_aclk_cam1_333_user", }; | |
5121 | PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user", | |
5122 | "mout_aclk_cam1_400_user", }; | |
5123 | ||
5124 | static struct samsung_fixed_rate_clock cam1_fixed_clks[] __initdata = { | |
5125 | FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL, | |
5126 | CLK_IS_ROOT, 100000000), | |
5127 | }; | |
5128 | ||
5129 | static struct samsung_mux_clock cam1_mux_clks[] __initdata = { | |
5130 | /* MUX_SEL_CAM10 */ | |
5131 | MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user", | |
5132 | mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1), | |
5133 | MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user", | |
5134 | mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1), | |
5135 | MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user", | |
5136 | mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1), | |
5137 | MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user", | |
5138 | mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1), | |
5139 | MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user", | |
5140 | mout_aclk_cam1_400_user_p, MUX_SEL_CAM01, 4, 1), | |
5141 | MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user", | |
5142 | mout_aclk_cam1_552_user_p, MUX_SEL_CAM01, 0, 1), | |
5143 | ||
5144 | /* MUX_SEL_CAM11 */ | |
5145 | MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER, | |
5146 | "mout_phyclk_rxbyteclkhs0_s2b_user", | |
5147 | mout_phyclk_rxbyteclkhs0_s2b_user_p, | |
5148 | MUX_SEL_CAM11, 0, 1), | |
5149 | ||
5150 | /* MUX_SEL_CAM12 */ | |
5151 | MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p, | |
5152 | MUX_SEL_CAM12, 20, 1), | |
5153 | MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p, | |
5154 | MUX_SEL_CAM12, 16, 1), | |
5155 | MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p, | |
5156 | MUX_SEL_CAM12, 12, 1), | |
5157 | MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p, | |
5158 | MUX_SEL_CAM12, 8, 1), | |
5159 | MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p, | |
5160 | MUX_SEL_CAM12, 4, 1), | |
5161 | MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p, | |
5162 | MUX_SEL_CAM12, 0, 1), | |
5163 | }; | |
5164 | ||
5165 | static struct samsung_div_clock cam1_div_clks[] __initdata = { | |
5166 | /* DIV_CAM10 */ | |
5167 | DIV(CLK_DIV_SCLK_ISP_WPWM, "div_sclk_isp_wpwm", | |
5168 | "div_pclk_cam1_83", DIV_CAM10, 16, 2), | |
5169 | DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83", | |
5170 | "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2), | |
5171 | DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166", | |
5172 | "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2), | |
5173 | DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1", | |
5174 | "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3), | |
5175 | DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user", | |
5176 | DIV_CAM10, 0, 3), | |
5177 | ||
5178 | /* DIV_CAM11 */ | |
5179 | DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b", | |
5180 | DIV_CAM11, 16, 3), | |
5181 | DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2), | |
5182 | DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3), | |
5183 | DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c", | |
5184 | DIV_CAM11, 4, 2), | |
5185 | DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b", | |
5186 | DIV_CAM11, 0, 3), | |
5187 | }; | |
5188 | ||
5189 | static struct samsung_gate_clock cam1_gate_clks[] __initdata = { | |
5190 | /* ENABLE_ACLK_CAM10 */ | |
5191 | GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user", | |
5192 | ENABLE_ACLK_CAM10, 4, 0, 0), | |
5193 | GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd", | |
5194 | ENABLE_ACLK_CAM10, 3, 0, 0), | |
5195 | GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c", | |
5196 | ENABLE_ACLK_CAM10, 1, 0, 0), | |
5197 | GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2", | |
5198 | ENABLE_ACLK_CAM10, 0, 0, 0), | |
5199 | ||
5200 | /* ENABLE_ACLK_CAM11 */ | |
5201 | GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd", | |
5202 | ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0), | |
5203 | GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166", | |
5204 | ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0), | |
5205 | GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c", | |
5206 | "div_pclk_lite_c", ENABLE_ACLK_CAM11, | |
5207 | 27, CLK_IGNORE_UNUSED, 0), | |
5208 | GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c", | |
5209 | "div_pclk_cam1_166", ENABLE_ACLK_CAM11, | |
5210 | 26, CLK_IGNORE_UNUSED, 0), | |
5211 | GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2", | |
5212 | "div_pclk_cam1_83", ENABLE_ACLK_CAM11, | |
5213 | 25, CLK_IGNORE_UNUSED, 0), | |
5214 | GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1", | |
5215 | "div_pclk_cam1_83", ENABLE_ACLK_CAM11, | |
5216 | 24, CLK_IGNORE_UNUSED, 0), | |
5217 | GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5", | |
5218 | "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, | |
5219 | 23, CLK_IGNORE_UNUSED, 0), | |
5220 | GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5", | |
5221 | "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11, | |
5222 | 22, CLK_IGNORE_UNUSED, 0), | |
5223 | GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2", | |
5224 | "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, | |
5225 | 21, CLK_IGNORE_UNUSED, 0), | |
5226 | GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1", | |
5227 | "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, | |
5228 | 20, CLK_IGNORE_UNUSED, 0), | |
5229 | GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0", | |
5230 | "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, | |
5231 | 19, CLK_IGNORE_UNUSED, 0), | |
5232 | GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex", | |
5233 | "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, | |
5234 | 18, CLK_IGNORE_UNUSED, 0), | |
5235 | GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p", | |
5236 | "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, | |
5237 | 17, CLK_IGNORE_UNUSED, 0), | |
5238 | GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p", | |
5239 | "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, | |
5240 | 16, CLK_IGNORE_UNUSED, 0), | |
5241 | GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd", | |
5242 | "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, | |
5243 | 15, CLK_IGNORE_UNUSED, 0), | |
5244 | GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd", | |
5245 | ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0), | |
5246 | GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c", | |
5247 | "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, | |
5248 | 13, CLK_IGNORE_UNUSED, 0), | |
5249 | GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c", | |
5250 | "div_aclk_lite_c", ENABLE_ACLK_CAM11, | |
5251 | 12, CLK_IGNORE_UNUSED, 0), | |
5252 | GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83", | |
5253 | ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0), | |
5254 | GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83", | |
5255 | ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0), | |
5256 | GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p", | |
5257 | "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, | |
5258 | 9, CLK_IGNORE_UNUSED, 0), | |
5259 | GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83", | |
5260 | ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0), | |
5261 | GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166", | |
5262 | ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0), | |
5263 | GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166", | |
5264 | ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0), | |
5265 | GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user", | |
5266 | ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0), | |
5267 | GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user", | |
5268 | ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0), | |
5269 | GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user", | |
5270 | ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0), | |
5271 | GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user", | |
5272 | ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0), | |
5273 | GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user", | |
5274 | ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0), | |
5275 | GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user", | |
5276 | ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0), | |
5277 | ||
5278 | /* ENABLE_ACLK_CAM12 */ | |
5279 | GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu", | |
5280 | "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, | |
5281 | 10, CLK_IGNORE_UNUSED, 0), | |
5282 | GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user", | |
5283 | ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0), | |
5284 | GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c", | |
5285 | "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, | |
5286 | 8, CLK_IGNORE_UNUSED, 0), | |
5287 | GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user", | |
5288 | ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0), | |
5289 | GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user", | |
5290 | ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0), | |
5291 | GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user", | |
5292 | ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0), | |
5293 | GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h", | |
5294 | "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12, | |
5295 | 4, CLK_IGNORE_UNUSED, 0), | |
5296 | GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p", | |
5297 | "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12, | |
5298 | 3, CLK_IGNORE_UNUSED, 0), | |
5299 | GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p", | |
5300 | "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, | |
5301 | 2, CLK_IGNORE_UNUSED, 0), | |
5302 | GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user", | |
5303 | ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0), | |
5304 | GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c", | |
5305 | "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, | |
5306 | 0, CLK_IGNORE_UNUSED, 0), | |
5307 | ||
5308 | /* ENABLE_PCLK_CAM1 */ | |
5309 | GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166", | |
5310 | ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0), | |
5311 | GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166", | |
5312 | ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0), | |
5313 | GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166", | |
5314 | ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0), | |
5315 | GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83", | |
5316 | ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0), | |
5317 | GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83", | |
5318 | ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0), | |
5319 | GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83", | |
5320 | ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0), | |
5321 | GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166", | |
5322 | ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0), | |
5323 | GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex", | |
5324 | "div_pclk_cam1_83", ENABLE_PCLK_CAM1, | |
5325 | 20, CLK_IGNORE_UNUSED, 0), | |
5326 | GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p", | |
5327 | "div_pclk_cam1_83", ENABLE_PCLK_CAM1, | |
5328 | 19, CLK_IGNORE_UNUSED, 0), | |
5329 | GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83", | |
5330 | ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0), | |
5331 | GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c", | |
5332 | "div_pclk_cam1_83", ENABLE_PCLK_CAM1, | |
5333 | 17, CLK_IGNORE_UNUSED, 0), | |
5334 | GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83", | |
5335 | ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0), | |
5336 | GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83", | |
5337 | ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0), | |
5338 | GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local", | |
5339 | "div_pclk_cam1_166", ENABLE_PCLK_CAM1, | |
5340 | 14, CLK_IGNORE_UNUSED, 0), | |
5341 | GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83", | |
5342 | ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0), | |
5343 | GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83", | |
5344 | ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0), | |
5345 | GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83", | |
5346 | ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0), | |
5347 | GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83", | |
5348 | ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0), | |
5349 | GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83", | |
5350 | ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0), | |
5351 | GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83", | |
5352 | ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0), | |
5353 | GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83", | |
5354 | ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0), | |
5355 | GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83", | |
5356 | ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0), | |
5357 | GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83", | |
5358 | ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0), | |
5359 | GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83", | |
5360 | ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0), | |
5361 | GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_wpwm", "div_pclk_cam1_83", | |
5362 | ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0), | |
5363 | GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd", | |
5364 | ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0), | |
5365 | GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c", | |
5366 | ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0), | |
5367 | GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166", | |
5368 | ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0), | |
5369 | ||
5370 | /* ENABLE_SCLK_CAM1 */ | |
5371 | GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1, | |
5372 | 15, 0, 0), | |
5373 | GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1, | |
5374 | 14, 0, 0), | |
5375 | GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1, | |
5376 | 13, 0, 0), | |
5377 | GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1, | |
5378 | 12, 0, 0), | |
5379 | GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b", | |
5380 | "mout_phyclk_rxbyteclkhs0_s2b_user", | |
5381 | ENABLE_SCLK_CAM1, 11, 0, 0), | |
5382 | GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c", | |
5383 | ENABLE_SCLK_CAM1, 10, 0, 0), | |
5384 | GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd", | |
5385 | ENABLE_SCLK_CAM1, 9, 0, 0), | |
5386 | GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1", | |
5387 | ENABLE_SCLK_CAM1, 7, 0, 0), | |
5388 | GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user", | |
5389 | ENABLE_SCLK_CAM1, 6, 0, 0), | |
5390 | GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user", | |
5391 | ENABLE_SCLK_CAM1, 5, 0, 0), | |
5392 | GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user", | |
5393 | ENABLE_SCLK_CAM1, 4, 0, 0), | |
5394 | GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_wpwm", "div_sclk_isp_wpwm", | |
5395 | ENABLE_SCLK_CAM1, 3, 0, 0), | |
5396 | GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1", | |
5397 | ENABLE_SCLK_CAM1, 2, 0, 0), | |
5398 | GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1", | |
5399 | ENABLE_SCLK_CAM1, 1, 0, 0), | |
5400 | GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user", | |
5401 | ENABLE_SCLK_CAM1, 0, 0, 0), | |
5402 | }; | |
5403 | ||
5404 | static struct samsung_cmu_info cam1_cmu_info __initdata = { | |
5405 | .mux_clks = cam1_mux_clks, | |
5406 | .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks), | |
5407 | .div_clks = cam1_div_clks, | |
5408 | .nr_div_clks = ARRAY_SIZE(cam1_div_clks), | |
5409 | .gate_clks = cam1_gate_clks, | |
5410 | .nr_gate_clks = ARRAY_SIZE(cam1_gate_clks), | |
5411 | .fixed_clks = cam1_fixed_clks, | |
5412 | .nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks), | |
5413 | .nr_clk_ids = CAM1_NR_CLK, | |
5414 | .clk_regs = cam1_clk_regs, | |
5415 | .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs), | |
5416 | }; | |
5417 | ||
5418 | static void __init exynos5433_cmu_cam1_init(struct device_node *np) | |
5419 | { | |
5420 | samsung_cmu_register_one(np, &cam1_cmu_info); | |
5421 | } | |
5422 | CLK_OF_DECLARE(exynos5433_cmu_cam1, "samsung,exynos5433-cmu-cam1", | |
5423 | exynos5433_cmu_cam1_init); |