projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
clk: samsung: add new clocks for DMC for Exynos5422 SoC
[linux-2.6-block.git] / drivers / clk / samsung / clk-exynos5420.c
CommitLineData
1609027f
CK		 1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Authors: Thomas Abraham <thomas.ab@samsung.com>
4 * Chander Kashyap <k.chander@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Common Clock Framework support for Exynos5420 SoC.
11*/
12
cba9d2fa 13#include <dt-bindings/clock/exynos5420.h>
6f1ed07a 14#include <linux/slab.h>
1609027f
CK		 15#include <linux/clk-provider.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18
19#include "clk.h"
bee4f87f 20#include "clk-cpu.h"
ec4016ff 21#include "clk-exynos5-subcmu.h"
1609027f 22
c898c6b7
YSB		 23#define APLL_LOCK 0x0
24#define APLL_CON0 0x100
1609027f
CK		 25#define SRC_CPU 0x200
26#define DIV_CPU0 0x500
27#define DIV_CPU1 0x504
28#define GATE_BUS_CPU 0x700
29#define GATE_SCLK_CPU 0x800
77342432 30#define CLKOUT_CMU_CPU 0xa00
e9d52956 31#define SRC_MASK_CPERI 0x4300
5b73721b 32#define GATE_IP_G2D 0x8800
c898c6b7
YSB		 33#define CPLL_LOCK 0x10020
34#define DPLL_LOCK 0x10030
35#define EPLL_LOCK 0x10040
36#define RPLL_LOCK 0x10050
37#define IPLL_LOCK 0x10060
38#define SPLL_LOCK 0x10070
53cb6342 39#define VPLL_LOCK 0x10080
c898c6b7
YSB		 40#define MPLL_LOCK 0x10090
41#define CPLL_CON0 0x10120
42#define DPLL_CON0 0x10128
43#define EPLL_CON0 0x10130
77342432
SAB		 44#define EPLL_CON1 0x10134
45#define EPLL_CON2 0x10138
c898c6b7 46#define RPLL_CON0 0x10140
77342432
SAB		 47#define RPLL_CON1 0x10144
48#define RPLL_CON2 0x10148
c898c6b7
YSB		 49#define IPLL_CON0 0x10150
50#define SPLL_CON0 0x10160
51#define VPLL_CON0 0x10170
52#define MPLL_CON0 0x10180
1609027f
CK		 53#define SRC_TOP0 0x10200
54#define SRC_TOP1 0x10204
55#define SRC_TOP2 0x10208
56#define SRC_TOP3 0x1020c
57#define SRC_TOP4 0x10210
58#define SRC_TOP5 0x10214
59#define SRC_TOP6 0x10218
60#define SRC_TOP7 0x1021c
6520e968
AA		 61#define SRC_TOP8 0x10220 /* 5800 specific */
62#define SRC_TOP9 0x10224 /* 5800 specific */
1609027f
CK		 63#define SRC_DISP10 0x1022c
64#define SRC_MAU 0x10240
65#define SRC_FSYS 0x10244
66#define SRC_PERIC0 0x10250
67#define SRC_PERIC1 0x10254
3a767b35 68#define SRC_ISP 0x10270
6520e968 69#define SRC_CAM 0x10274 /* 5800 specific */
1609027f
CK		 70#define SRC_TOP10 0x10280
71#define SRC_TOP11 0x10284
72#define SRC_TOP12 0x10288
6520e968 73#define SRC_TOP13 0x1028c /* 5800 specific */
e9d52956
VS		 74#define SRC_MASK_TOP0 0x10300
75#define SRC_MASK_TOP1 0x10304
424b673a 76#define SRC_MASK_TOP2 0x10308
31116a64 77#define SRC_MASK_TOP7 0x1031c
424b673a 78#define SRC_MASK_DISP10 0x1032c
31116a64 79#define SRC_MASK_MAU 0x10334
1609027f
CK		 80#define SRC_MASK_FSYS 0x10340
81#define SRC_MASK_PERIC0 0x10350
82#define SRC_MASK_PERIC1 0x10354
e9d52956 83#define SRC_MASK_ISP 0x10370
1609027f
CK		 84#define DIV_TOP0 0x10500
85#define DIV_TOP1 0x10504
86#define DIV_TOP2 0x10508
6520e968
AA		 87#define DIV_TOP8 0x10520 /* 5800 specific */
88#define DIV_TOP9 0x10524 /* 5800 specific */
1609027f
CK		 89#define DIV_DISP10 0x1052c
90#define DIV_MAU 0x10544
91#define DIV_FSYS0 0x10548
92#define DIV_FSYS1 0x1054c
93#define DIV_FSYS2 0x10550
94#define DIV_PERIC0 0x10558
95#define DIV_PERIC1 0x1055c
96#define DIV_PERIC2 0x10560
97#define DIV_PERIC3 0x10564
98#define DIV_PERIC4 0x10568
6520e968 99#define DIV_CAM 0x10574 /* 5800 specific */
3a767b35
SAB		 100#define SCLK_DIV_ISP0 0x10580
101#define SCLK_DIV_ISP1 0x10584
02932381 102#define DIV2_RATIO0 0x10590
1d87db4d 103#define DIV4_RATIO 0x105a0
1609027f 104#define GATE_BUS_TOP 0x10700
e9d52956 105#define GATE_BUS_DISP1 0x10728
0a22c306 106#define GATE_BUS_GEN 0x1073c
1609027f 107#define GATE_BUS_FSYS0 0x10740
6b5ae463 108#define GATE_BUS_FSYS2 0x10748
1609027f
CK		 109#define GATE_BUS_PERIC 0x10750
110#define GATE_BUS_PERIC1 0x10754
111#define GATE_BUS_PERIS0 0x10760
112#define GATE_BUS_PERIS1 0x10764
6575fa76 113#define GATE_BUS_NOC 0x10770
3a767b35 114#define GATE_TOP_SCLK_ISP 0x10870
1609027f
CK		 115#define GATE_IP_GSCL0 0x10910
116#define GATE_IP_GSCL1 0x10920
6520e968 117#define GATE_IP_CAM 0x10924 /* 5800 specific */
1609027f
CK		 118#define GATE_IP_MFC 0x1092c
119#define GATE_IP_DISP1 0x10928
120#define GATE_IP_G3D 0x10930
121#define GATE_IP_GEN 0x10934
6b5ae463 122#define GATE_IP_FSYS 0x10944
faec151b 123#define GATE_IP_PERIC 0x10950
0a22c306 124#define GATE_IP_PERIS 0x10960
1609027f
CK		 125#define GATE_IP_MSCL 0x10970
126#define GATE_TOP_SCLK_GSCL 0x10820
127#define GATE_TOP_SCLK_DISP1 0x10828
128#define GATE_TOP_SCLK_MAU 0x1083c
129#define GATE_TOP_SCLK_FSYS 0x10840
130#define GATE_TOP_SCLK_PERIC 0x10850
424b673a 131#define TOP_SPARE2 0x10b08
c898c6b7
YSB		 132#define BPLL_LOCK 0x20010
133#define BPLL_CON0 0x20110
e867e8fa
CC		 134#define SRC_CDREX 0x20200
135#define DIV_CDREX0 0x20500
136#define DIV_CDREX1 0x20504
2f57b95c
LL		 137#define GATE_BUS_CDREX0 0x20700
138#define GATE_BUS_CDREX1 0x20704
c898c6b7
YSB		 139#define KPLL_LOCK 0x28000
140#define KPLL_CON0 0x28100
1609027f
CK		 141#define SRC_KFC 0x28200
142#define DIV_KFC0 0x28500
143
6520e968
AA		 144/* Exynos5x SoC type */
145enum exynos5x_soc {
146 EXYNOS5420,
147 EXYNOS5800,
148};
149
c898c6b7 150/* list of PLLs */
6520e968 151enum exynos5x_plls {
c898c6b7
YSB		 152 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
153 bpll, kpll,
154 nr_plls /* number of PLLs */
155};
156
388c7885 157static void __iomem *reg_base;
6520e968 158static enum exynos5x_soc exynos5x_soc;
388c7885 159
1609027f
CK		 160/*
161 * list of controller registers to be saved and restored during a
162 * suspend/resume cycle.
163 */
ad98c64f 164static const unsigned long exynos5x_clk_regs[] __initconst = {
1609027f
CK		 165 SRC_CPU,
166 DIV_CPU0,
167 DIV_CPU1,
168 GATE_BUS_CPU,
169 GATE_SCLK_CPU,
77342432
SAB		 170 CLKOUT_CMU_CPU,
171 EPLL_CON0,
172 EPLL_CON1,
173 EPLL_CON2,
174 RPLL_CON0,
175 RPLL_CON1,
176 RPLL_CON2,
1609027f
CK		 177 SRC_TOP0,
178 SRC_TOP1,
179 SRC_TOP2,
180 SRC_TOP3,
181 SRC_TOP4,
182 SRC_TOP5,
183 SRC_TOP6,
184 SRC_TOP7,
185 SRC_DISP10,
186 SRC_MAU,
187 SRC_FSYS,
188 SRC_PERIC0,
189 SRC_PERIC1,
190 SRC_TOP10,
191 SRC_TOP11,
192 SRC_TOP12,
424b673a 193 SRC_MASK_TOP2,
31116a64 194 SRC_MASK_TOP7,
1609027f
CK		 195 SRC_MASK_DISP10,
196 SRC_MASK_FSYS,
197 SRC_MASK_PERIC0,
198 SRC_MASK_PERIC1,
e9d52956
VS		 199 SRC_MASK_TOP0,
200 SRC_MASK_TOP1,
201 SRC_MASK_MAU,
202 SRC_MASK_ISP,
3a767b35 203 SRC_ISP,
1609027f
CK		 204 DIV_TOP0,
205 DIV_TOP1,
206 DIV_TOP2,
207 DIV_DISP10,
208 DIV_MAU,
209 DIV_FSYS0,
210 DIV_FSYS1,
211 DIV_FSYS2,
212 DIV_PERIC0,
213 DIV_PERIC1,
214 DIV_PERIC2,
215 DIV_PERIC3,
216 DIV_PERIC4,
3a767b35
SAB		 217 SCLK_DIV_ISP0,
218 SCLK_DIV_ISP1,
02932381 219 DIV2_RATIO0,
1d87db4d 220 DIV4_RATIO,
e9d52956 221 GATE_BUS_DISP1,
1609027f 222 GATE_BUS_TOP,
0a22c306 223 GATE_BUS_GEN,
1609027f 224 GATE_BUS_FSYS0,
6b5ae463 225 GATE_BUS_FSYS2,
1609027f
CK		 226 GATE_BUS_PERIC,
227 GATE_BUS_PERIC1,
228 GATE_BUS_PERIS0,
229 GATE_BUS_PERIS1,
6575fa76 230 GATE_BUS_NOC,
3a767b35 231 GATE_TOP_SCLK_ISP,
1609027f
CK		 232 GATE_IP_GSCL0,
233 GATE_IP_GSCL1,
234 GATE_IP_MFC,
235 GATE_IP_DISP1,
236 GATE_IP_G3D,
237 GATE_IP_GEN,
6b5ae463 238 GATE_IP_FSYS,
faec151b 239 GATE_IP_PERIC,
0a22c306 240 GATE_IP_PERIS,
1609027f
CK		 241 GATE_IP_MSCL,
242 GATE_TOP_SCLK_GSCL,
243 GATE_TOP_SCLK_DISP1,
244 GATE_TOP_SCLK_MAU,
245 GATE_TOP_SCLK_FSYS,
246 GATE_TOP_SCLK_PERIC,
424b673a 247 TOP_SPARE2,
e867e8fa
CC		 248 SRC_CDREX,
249 DIV_CDREX0,
250 DIV_CDREX1,
1609027f
CK		 251 SRC_KFC,
252 DIV_KFC0,
2f57b95c
LL		 253 GATE_BUS_CDREX0,
254 GATE_BUS_CDREX1,
1609027f
CK		 255};
256
ad98c64f 257static const unsigned long exynos5800_clk_regs[] __initconst = {
6520e968
AA		 258 SRC_TOP8,
259 SRC_TOP9,
260 SRC_CAM,
261 SRC_TOP1,
262 DIV_TOP8,
263 DIV_TOP9,
264 DIV_CAM,
265 GATE_IP_CAM,
266};
267
e9d52956
VS		 268static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
269 { .offset = SRC_MASK_CPERI, .value = 0xffffffff, },
270 { .offset = SRC_MASK_TOP0, .value = 0x11111111, },
271 { .offset = SRC_MASK_TOP1, .value = 0x11101111, },
272 { .offset = SRC_MASK_TOP2, .value = 0x11111110, },
273 { .offset = SRC_MASK_TOP7, .value = 0x00111100, },
274 { .offset = SRC_MASK_DISP10, .value = 0x11111110, },
275 { .offset = SRC_MASK_MAU, .value = 0x10000000, },
276 { .offset = SRC_MASK_FSYS, .value = 0x11111110, },
277 { .offset = SRC_MASK_PERIC0, .value = 0x11111110, },
278 { .offset = SRC_MASK_PERIC1, .value = 0x11111100, },
279 { .offset = SRC_MASK_ISP, .value = 0x11111000, },
97372e5a 280 { .offset = GATE_BUS_TOP, .value = 0xffffffff, },
e9d52956
VS		 281 { .offset = GATE_BUS_DISP1, .value = 0xffffffff, },
282 { .offset = GATE_IP_PERIC, .value = 0xffffffff, },
b3322802 283 { .offset = GATE_IP_PERIS, .value = 0xffffffff, },
e9d52956
VS		 284};
285
1609027f 286/* list of all parent clocks */
dbd713bb
SAB		 287PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
288 "mout_sclk_mpll", "mout_sclk_spll"};
289PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
290PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
291PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
292PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
293PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
294PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
295PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
296PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
297PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
298PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
299PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
300PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
301PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
302
303PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
304 "mout_sclk_mpll"};
305PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
306 "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
307 "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
308PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
309PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
310PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
311
424b673a 312PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
dbd713bb 313PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};
b31ca2a0
SAB		 314PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"};
315PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"};
dbd713bb
SAB		 316
317PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
6b5ae463
SAB		 318PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
319PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"};
dbd713bb
SAB		 320PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};
321
322PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
323PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
6575fa76
SAB		 324PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
325PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
326
327PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
328PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
329PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
330
3a767b35
SAB		 331PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
332PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
333
334PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
335 "mout_sclk_spll"};
336PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
337
338PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
339PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
dbd713bb
SAB		 340
341PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
424b673a 342PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
dbd713bb
SAB		 343
344PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
345PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"};
346
347PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
348PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
349
350PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
351PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
352
353PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
354PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
3a767b35 355PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
dbd713bb
SAB		 356
357PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
358PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
359
360PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
361PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"};
362
363PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
424b673a 364PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
dbd713bb 365PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
424b673a 366PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
dbd713bb
SAB		 367
368PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
369PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
370
371PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
372PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
373
374PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
375PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
376
377PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
378PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
379
380PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
381 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
382 "mout_sclk_epll", "mout_sclk_rpll"};
383PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
384 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
385 "mout_sclk_epll", "mout_sclk_rpll"};
386PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
387 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
388 "mout_sclk_epll", "mout_sclk_rpll"};
389PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
390 "dout_audio2", "spdif_extclk", "mout_sclk_ipll",
391 "mout_sclk_epll", "mout_sclk_rpll"};
392PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
393PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
394 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
395 "mout_sclk_epll", "mout_sclk_rpll"};
31116a64
SAB		 396PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
397 "mout_sclk_mpll", "mout_sclk_spll"};
e867e8fa
CC		 398PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"};
399
6520e968
AA		 400/* List of parents specific to exynos5800 */
401PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" };
402PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
403 "mout_sclk_mpll", "ff_dout_spll2" };
404PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
405 "mout_sclk_mpll", "ff_dout_spll2",
406 "mout_epll2", "mout_sclk_ipll" };
407PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
408 "mout_sclk_mpll", "ff_dout_spll2",
409 "mout_epll2" };
410PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
411 "mout_sclk_mpll", "mout_sclk_spll" };
412PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll",
413 "mout_sclk_mpll", "ff_dout_spll2" };
414PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
415 "mout_sclk_mpll", "mout_sclk_spll",
416 "mout_epll2", "mout_sclk_ipll" };
e867e8fa
CC		 417PNAME(mout_mx_mspll_ccore_p) = {"sclk_bpll", "mout_sclk_dpll",
418 "mout_sclk_mpll", "ff_dout_spll2",
419 "mout_sclk_spll", "mout_sclk_epll"};
6520e968
AA		 420PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll",
421 "mout_sclk_mpll",
422 "ff_dout_spll2" };
423PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" };
424PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" };
425PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" };
426PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" };
427PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" };
428PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
429PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" };
430PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" };
8a9cf26e 431PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" };
2f57b95c
LL		 432PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
433 "mout_sclk_mpll", "ff_dout_spll2",
434 "mout_sclk_spll", "mout_sclk_epll"};
1609027f
CK		 435
436/* fixed rate clocks generated outside the soc */
6520e968
AA		 437static struct samsung_fixed_rate_clock
438 exynos5x_fixed_rate_ext_clks[] __initdata = {
728f288d 439 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
1609027f
CK		 440};
441
442/* fixed rate clocks generated inside the soc */
ad98c64f 443static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = {
728f288d
SB		 444 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
445 FRATE(0, "sclk_pwi", NULL, 0, 24000000),
446 FRATE(0, "sclk_usbh20", NULL, 0, 48000000),
447 FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000),
448 FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000),
1609027f
CK		 449};
450
ad98c64f
KK		 451static const struct samsung_fixed_factor_clock
452 exynos5x_fixed_factor_clks[] __initconst = {
b31ca2a0
SAB		 453 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
454 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
1609027f
CK		 455};
456
ad98c64f
KK		 457static const struct samsung_fixed_factor_clock
458 exynos5800_fixed_factor_clks[] __initconst = {
6520e968 459 FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
2f57b95c 460 FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
6520e968 461};
31116a64 462
ad98c64f 463static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
6520e968
AA		 464 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
465 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
466 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
467 MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
468
469 MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
470 MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
471 MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
472 MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
473 MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
474
475 MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
476 MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
477 MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
478 MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
479 MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
480 MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
481
2f57b95c
LL		 482 MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy",
483 mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3),
484
e867e8fa 485 MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
2f57b95c 486 mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3),
599cebea
SN		 487 MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
488 SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),
2f57b95c 489 MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
6520e968
AA		 490 MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
491
492 MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
493 MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
494 MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
495 MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
496
599cebea
SN		 497 MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
498 SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),
6520e968
AA		 499 MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
500 SRC_TOP9, 16, 1),
501 MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
502 SRC_TOP9, 20, 1),
503 MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p,
504 SRC_TOP9, 24, 1),
505 MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
506 SRC_TOP9, 28, 1),
507
508 MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
509 MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
510 SRC_TOP13, 20, 1),
511 MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
512 SRC_TOP13, 24, 1),
513 MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p,
514 SRC_TOP13, 28, 1),
515
516 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
517};
1609027f 518
ad98c64f 519static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
81fed6e3
CC		 520 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
521 "mout_aclk400_wcore", DIV_TOP0, 16, 3),
6520e968
AA		 522 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
523 DIV_TOP8, 16, 3),
524 DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
525 DIV_TOP8, 20, 3),
526 DIV(0, "dout_aclk432_cam", "mout_aclk432_cam",
527 DIV_TOP8, 24, 3),
528 DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler",
529 DIV_TOP8, 28, 3),
530
531 DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3),
532 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
533};
534
ad98c64f 535static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = {
6520e968
AA		 536 GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
537 GATE_BUS_TOP, 24, 0, 0),
538 GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
318fa46c 539 GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),
41097f25 540 GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll",
599cebea 541 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
6520e968
AA		 542};
543
ad98c64f 544static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
58ff8d03 545 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
6520e968
AA		 546 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
547 TOP_SPARE2, 4, 1),
1609027f 548
3a767b35 549 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
36ba4824 550 MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
6575fa76
SAB		 551 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
552 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
dbd713bb
SAB		 553
554 MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
3a767b35 555 MUX(0, "mout_aclk333_432_isp", mout_group4_p,
6520e968 556 SRC_TOP1, 4, 2),
3a767b35 557 MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
dbd713bb 558 MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
dbd713bb
SAB		 559 MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
560
424b673a 561 MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
dbd713bb
SAB		 562 MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
563 MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
dbd713bb
SAB		 564 MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
565 MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
566 MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
567
e867e8fa
CC		 568 MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
569 mout_group5_5800_p, SRC_TOP7, 16, 2),
06255a92
SN		 570 MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
571 CLK_SET_RATE_PARENT, 0),
6520e968
AA		 572
573 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
574};
575
ad98c64f 576static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
81fed6e3
CC		 577 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
578 "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
6520e968
AA		 579};
580
41097f25 581static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
d32dd2a1 582 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
41097f25 583 GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
599cebea 584 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
41097f25
SN		 585};
586
ad98c64f 587static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
6520e968
AA		 588 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
589 SRC_TOP7, 4, 1),
590 MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
591 MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
592
bee4f87f
TA		 593 MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
594 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
6520e968 595 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
bee4f87f
TA		 596 MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
597 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
6520e968
AA		 598 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
599
600 MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
601 MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
602 MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
603 MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
604
605 MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
606 MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
607
608 MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
609
3a767b35
SAB		 610 MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
611 SRC_TOP3, 0, 1),
dbd713bb 612 MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
1609027f 613 SRC_TOP3, 4, 1),
88560100
JMC		 614 MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1",
615 mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1),
dbd713bb 616 MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
1609027f 617 SRC_TOP3, 12, 1),
6575fa76
SAB		 618 MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
619 SRC_TOP3, 16, 1),
620 MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
621 SRC_TOP3, 20, 1),
6b5ae463
SAB		 622 MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
623 SRC_TOP3, 24, 1),
dbd713bb 624 MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
1609027f
CK		 625 SRC_TOP3, 28, 1),
626
dbd713bb 627 MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
1609027f 628 SRC_TOP4, 0, 1),
3a767b35
SAB		 629 MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
630 SRC_TOP4, 4, 1),
faec151b
SAB		 631 MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
632 SRC_TOP4, 8, 1),
3a767b35
SAB		 633 MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
634 SRC_TOP4, 12, 1),
635 MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
636 SRC_TOP4, 16, 1),
dbd713bb
SAB		 637 MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
638 MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
c0fb262b
AK		 639 MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
640 SRC_TOP4, 28, 1),
dbd713bb 641
88560100
JMC		 642 MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1",
643 mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
faec151b
SAB		 644 MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
645 SRC_TOP5, 4, 1),
3fac5941
SAB		 646 MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
647 SRC_TOP5, 8, 1),
648 MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
649 SRC_TOP5, 12, 1),
650 MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
651 SRC_TOP5, 16, 1),
dbd713bb 652 MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
1609027f 653 SRC_TOP5, 20, 1),
88560100
JMC		 654 MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
655 mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
c0feb268
MS		 656 MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl",
657 mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
1609027f 658
dbd713bb
SAB		 659 MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
660 MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
2f57b95c 661 MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
dbd713bb
SAB		 662 MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
663 MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
599cebea
SN		 664 MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
665 CLK_SET_RATE_PARENT, 0),
dbd713bb
SAB		 666 MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
667 MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
668
3a767b35
SAB		 669 MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
670 SRC_TOP10, 0, 1),
dbd713bb
SAB		 671 MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
672 SRC_TOP10, 4, 1),
88560100
JMC		 673 MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
674 SRC_TOP10, 8, 1),
dbd713bb 675 MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
1609027f 676 SRC_TOP10, 12, 1),
6575fa76
SAB		 677 MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
678 SRC_TOP10, 16, 1),
679 MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
680 SRC_TOP10, 20, 1),
6b5ae463
SAB		 681 MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
682 SRC_TOP10, 24, 1),
dbd713bb
SAB		 683 MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
684 SRC_TOP10, 28, 1),
3a767b35 685
dbd713bb 686 MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
1609027f 687 SRC_TOP11, 0, 1),
3a767b35
SAB		 688 MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
689 SRC_TOP11, 4, 1),
dbd713bb 690 MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
3a767b35
SAB		 691 MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
692 SRC_TOP11, 12, 1),
dbd713bb
SAB		 693 MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
694 MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
c0fb262b
AK		 695 MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
696 SRC_TOP11, 28, 1),
dbd713bb 697
88560100
JMC		 698 MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",
699 mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1),
dbd713bb
SAB		 700 MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
701 SRC_TOP12, 8, 1),
702 MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
703 SRC_TOP12, 12, 1),
704 MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
705 MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
706 SRC_TOP12, 20, 1),
88560100
JMC		 707 MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
708 mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
c0feb268
MS		 709 MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl",
710 mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
1609027f
CK		 711
712 /* DISP1 Block */
dbd713bb
SAB		 713 MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
714 MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
715 MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
716 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
424b673a 717 MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
6575fa76 718
424b673a 719 MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
1609027f 720
e867e8fa
CC		 721 /* CDREX block */
722 MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p,
723 SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0),
724 MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1,
725 CLK_SET_RATE_PARENT, 0),
726
1609027f 727 /* MAU Block */
31116a64 728 MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
1609027f
CK		 729
730 /* FSYS Block */
dbd713bb
SAB		 731 MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
732 MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
733 MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
734 MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
735 MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
736 MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
6b5ae463 737 MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
1609027f
CK		 738
739 /* PERIC Block */
dbd713bb
SAB		 740 MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
741 MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
742 MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
743 MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
744 MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
745 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
746 MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
747 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
748 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
749 MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
750 MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
751 MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
3a767b35
SAB		 752
753 /* ISP Block */
754 MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
755 MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
756 MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
757 MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
758 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
1609027f
CK		 759};
760
ad98c64f 761static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
cba9d2fa
AH		 762 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
763 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
764 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
dbd713bb 765 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
cba9d2fa
AH		 766 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
767
81fed6e3
CC		 768 DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp",
769 DIV_TOP0, 0, 3),
770 DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl",
771 DIV_TOP0, 4, 3),
772 DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200",
773 DIV_TOP0, 8, 3),
774 DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2",
775 DIV_TOP0, 12, 3),
776 DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
777 DIV_TOP0, 20, 3),
778 DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys",
779 DIV_TOP0, 24, 3),
780 DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",
781 DIV_TOP0, 28, 3),
782 DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl",
783 "mout_aclk333_432_gscl", DIV_TOP1, 0, 3),
784 DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp",
785 "mout_aclk333_432_isp", DIV_TOP1, 4, 3),
786 DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66",
787 DIV_TOP1, 8, 6),
788 DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0",
789 "mout_aclk333_432_isp0", DIV_TOP1, 16, 3),
790 DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266",
791 DIV_TOP1, 20, 3),
792 DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166",
793 DIV_TOP1, 24, 3),
794 DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333",
795 DIV_TOP1, 28, 3),
796
797 DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d",
798 DIV_TOP2, 8, 3),
799 DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d",
800 DIV_TOP2, 12, 3),
801 DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
802 16, 3),
803 DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg",
804 DIV_TOP2, 20, 3),
805 DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1",
806 "mout_aclk300_disp1", DIV_TOP2, 24, 3),
807 DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl",
808 DIV_TOP2, 28, 3),
1609027f
CK		 809
810 /* DISP1 Block */
424b673a 811 DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
cba9d2fa
AH		 812 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
813 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
814 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
81fed6e3
CC		 815 DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1",
816 "mout_aclk400_disp1", DIV_TOP2, 4, 3),
1609027f 817
e867e8fa 818 /* CDREX Block */
2f57b95c
LL		 819 /*
820 * The three clocks below are controlled using the same register and
821 * bits. They are put into one because there is a need of
822 * synchronization between the BUS and DREXs (two external memory
823 * interfaces).
824 * They are put here to show this HW assumption and for clock
825 * information summary completeness.
826 */
827 DIV_F(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",
828 DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
829 DIV_F(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0",
830 DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
831 DIV_F(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0",
832 DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
833
e867e8fa
CC		 834 DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex",
835 DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0),
836 DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0",
837 DIV_CDREX0, 16, 3),
838 DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0",
839 DIV_CDREX0, 8, 3),
840 DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex",
841 DIV_CDREX0, 3, 5),
842
843 DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex",
844 DIV_CDREX1, 8, 3),
845
1609027f 846 /* Audio Block */
cba9d2fa
AH		 847 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
848 DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
1609027f
CK		 849
850 /* USB3.0 */
cba9d2fa
AH		 851 DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
852 DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
853 DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
854 DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
1609027f
CK		 855
856 /* MMC */
cba9d2fa
AH		 857 DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
858 DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
859 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
1609027f 860
cba9d2fa 861 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
6b5ae463 862 DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
1609027f
CK		 863
864 /* UART and PWM */
cba9d2fa
AH		 865 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
866 DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
867 DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
868 DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
869 DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
1609027f
CK		 870
871 /* SPI */
cba9d2fa
AH		 872 DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
873 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
874 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
1609027f 875
1d87db4d 876
1609027f 877 /* PCM */
cba9d2fa
AH		 878 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
879 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
1609027f
CK		 880
881 /* Audio - I2S */
cba9d2fa
AH		 882 DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
883 DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
884 DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
885 DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
886 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
1609027f
CK		 887
888 /* SPI Pre-Ratio */
faec151b
SAB		 889 DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
890 DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
891 DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
3a767b35 892
02932381 893 /* GSCL Block */
02932381
SAB		 894 DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
895
4549d93d
SAB		 896 /* MSCL Block */
897 DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
898
0a22c306
SAB		 899 /* PSGEN */
900 DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
901 DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
902
3a767b35
SAB		 903 /* ISP Block */
904 DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
905 DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
906 DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
907 DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
908 DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
909 DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
910 DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
911 DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
912 CLK_SET_RATE_PARENT, 0),
913 DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
914 CLK_SET_RATE_PARENT, 0),
1609027f
CK		 915};
916
ad98c64f 917static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
5b73721b 918 /* G2D */
3fac5941 919 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
5b73721b 920 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
3fac5941
SAB		 921 GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
922 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
923 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
5b73721b 924
1609027f 925 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
318fa46c 926 GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0),
1609027f
CK		 927 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
928 GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
929
930 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
931 GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
932 GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
318fa46c 933 GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0),
1609027f
CK		 934 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
935 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
3a767b35
SAB		 936 GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
937 GATE_BUS_TOP, 5, 0, 0),
1609027f 938 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
318fa46c 939 GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0),
1609027f
CK		 940 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
941 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
3a767b35
SAB		 942 GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
943 GATE_BUS_TOP, 8, 0, 0),
b31ca2a0 944 GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
1609027f 945 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
faec151b 946 GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
1609027f 947 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
3a767b35
SAB		 948 GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
949 GATE_BUS_TOP, 13, 0, 0),
1609027f
CK		 950 GATE(0, "aclk166", "mout_user_aclk166",
951 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
34cba900 952 GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",
318fa46c 953 GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0),
3a767b35
SAB		 954 GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
955 GATE_BUS_TOP, 16, 0, 0),
02932381 956 GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
c07c1a0f 957 GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0),
424b673a 958 GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
318fa46c 959 GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0),
b31ca2a0
SAB		 960 GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
961 GATE_BUS_TOP, 28, 0, 0),
962 GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",
963 GATE_BUS_TOP, 29, 0, 0),
424b673a
SAB		 964
965 GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
318fa46c 966 SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0),
1609027f
CK		 967
968 /* sclk */
cba9d2fa 969 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
1609027f 970 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
cba9d2fa 971 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
1609027f 972 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
cba9d2fa 973 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
1609027f 974 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
cba9d2fa 975 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
1609027f 976 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
faec151b 977 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
1609027f 978 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
faec151b 979 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre",
1609027f 980 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
faec151b 981 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre",
1609027f 982 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
cba9d2fa 983 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
1609027f 984 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
cba9d2fa 985 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
1609027f 986 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
cba9d2fa 987 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
1609027f 988 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
cba9d2fa 989 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
1609027f 990 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
cba9d2fa 991 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
1609027f 992 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
cba9d2fa 993 GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
1609027f
CK		 994 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
995
cba9d2fa 996 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
1609027f 997 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
cba9d2fa 998 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
1609027f 999 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
cba9d2fa 1000 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
1609027f 1001 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
cba9d2fa 1002 GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
1609027f 1003 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
cba9d2fa 1004 GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
1609027f 1005 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
cba9d2fa 1006 GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
1609027f 1007 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
cba9d2fa 1008 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
1609027f
CK		 1009 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
1010
1609027f 1011 /* Display */
cba9d2fa 1012 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
424b673a 1013 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
cba9d2fa 1014 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
424b673a 1015 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
cba9d2fa 1016 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
424b673a 1017 GATE_TOP_SCLK_DISP1, 9, 0, 0),
cba9d2fa 1018 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
424b673a 1019 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
cba9d2fa 1020 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
424b673a 1021 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
1609027f
CK		 1022
1023 /* Maudio Block */
cba9d2fa 1024 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
1609027f 1025 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
cba9d2fa 1026 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
1609027f 1027 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
6b5ae463
SAB		 1028
1029 /* FSYS Block */
cba9d2fa
AH		 1030 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
1031 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
1032 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
1033 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
6b5ae463
SAB		 1034 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
1035 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
1036 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
1037 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
cba9d2fa 1038 GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
6b5ae463
SAB		 1039 GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
1040 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
1041 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
1042 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
1043 GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
1044 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
1609027f 1045
faec151b 1046 /* PERIC Block */
44ff0254
DA		 1047 GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",
1048 GATE_IP_PERIC, 0, 0, 0),
1049 GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
1050 GATE_IP_PERIC, 1, 0, 0),
1051 GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",
1052 GATE_IP_PERIC, 2, 0, 0),
1053 GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric",
1054 GATE_IP_PERIC, 3, 0, 0),
1055 GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric",
1056 GATE_IP_PERIC, 6, 0, 0),
1057 GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric",
1058 GATE_IP_PERIC, 7, 0, 0),
1059 GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric",
1060 GATE_IP_PERIC, 8, 0, 0),
1061 GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric",
1062 GATE_IP_PERIC, 9, 0, 0),
1063 GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric",
1064 GATE_IP_PERIC, 10, 0, 0),
1065 GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric",
1066 GATE_IP_PERIC, 11, 0, 0),
1067 GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric",
1068 GATE_IP_PERIC, 12, 0, 0),
1069 GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric",
1070 GATE_IP_PERIC, 13, 0, 0),
1071 GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric",
1072 GATE_IP_PERIC, 14, 0, 0),
1073 GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric",
1074 GATE_IP_PERIC, 15, 0, 0),
1075 GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric",
1076 GATE_IP_PERIC, 16, 0, 0),
1077 GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric",
1078 GATE_IP_PERIC, 17, 0, 0),
1079 GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric",
1080 GATE_IP_PERIC, 18, 0, 0),
1081 GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric",
1082 GATE_IP_PERIC, 20, 0, 0),
1083 GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric",
1084 GATE_IP_PERIC, 21, 0, 0),
1085 GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric",
1086 GATE_IP_PERIC, 22, 0, 0),
1087 GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric",
1088 GATE_IP_PERIC, 23, 0, 0),
1089 GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric",
1090 GATE_IP_PERIC, 24, 0, 0),
1091 GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric",
1092 GATE_IP_PERIC, 26, 0, 0),
1093 GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric",
1094 GATE_IP_PERIC, 28, 0, 0),
1095 GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric",
1096 GATE_IP_PERIC, 30, 0, 0),
1097 GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric",
1098 GATE_IP_PERIC, 31, 0, 0),
1099
1100 GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric",
1101 GATE_BUS_PERIC, 22, 0, 0),
1609027f 1102
0a22c306 1103 /* PERIS Block */
cba9d2fa 1104 GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
0a22c306 1105 GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
cba9d2fa 1106 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
0a22c306
SAB		 1107 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1108 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
1109 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
1110 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
1111 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
1112 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
1113 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
1114 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
1115 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
1116 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
1117 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
1118 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
1119 GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
1120 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
1121 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
1122 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
1123 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
1124
0a22c306
SAB		 1125 /* GEN Block */
1126 GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
1127 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
1128 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
1129 GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
1130 GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
1131 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
1132 GATE_IP_GEN, 6, 0, 0),
1133 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
1134 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
1135 GATE_IP_GEN, 9, 0, 0),
1136
1137 /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */
1138 GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
1139 GATE_BUS_GEN, 28, 0, 0),
1140 GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
cba9d2fa 1141
02932381
SAB		 1142 /* GSCL Block */
1143 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
1144 GATE_TOP_SCLK_GSCL, 6, 0, 0),
1145 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
1146 GATE_TOP_SCLK_GSCL, 7, 0, 0),
1147
02932381
SAB		 1148 GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl",
1149 GATE_IP_GSCL0, 4, 0, 0),
1150 GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl",
1151 GATE_IP_GSCL0, 5, 0, 0),
1152 GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl",
1153 GATE_IP_GSCL0, 6, 0, 0),
1154
1155 GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
1156 GATE_IP_GSCL1, 2, 0, 0),
1157 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
1609027f 1158 GATE_IP_GSCL1, 3, 0, 0),
02932381 1159 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
1609027f 1160 GATE_IP_GSCL1, 4, 0, 0),
02932381
SAB		 1161 GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0),
1162 GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0),
1163 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
1609027f 1164 GATE_IP_GSCL1, 16, 0, 0),
cba9d2fa 1165 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
1609027f
CK		 1166 GATE_IP_GSCL1, 17, 0, 0),
1167
02932381
SAB		 1168 /* MSCL Block */
1169 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
1170 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
1171 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
4549d93d 1172 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
02932381 1173 GATE_IP_MSCL, 8, 0, 0),
4549d93d 1174 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
02932381 1175 GATE_IP_MSCL, 9, 0, 0),
4549d93d 1176 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
02932381
SAB		 1177 GATE_IP_MSCL, 10, 0, 0),
1178
3a767b35
SAB		 1179 /* ISP */
1180 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
1181 GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
1182 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
1183 GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
1184 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
1185 GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
1186 GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
1187 GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
1188 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
1189 GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
1190 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
1191 GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
1192 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
1193 GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
1194
ec4016ff 1195 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
2f57b95c
LL		 1196
1197 /* CDREX */
1198 GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex",
1199 GATE_BUS_CDREX0, 0, 0, 0),
1200 GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex",
1201 GATE_BUS_CDREX0, 1, 0, 0),
1202 GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy",
1203 SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0),
1204
1205 GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1",
1206 GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0),
1207 GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1",
1208 GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0),
1209 GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1",
1210 GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0),
1211 GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1",
1212 GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0),
1213
1214 GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex",
1215 GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0),
1216 GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex",
1217 GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0),
1218 GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex",
1219 GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0),
1220 GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex",
1221 GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0),
ec4016ff
MS		 1222};
1223
1224static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = {
1225 DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
1226};
1227
1228static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = {
1229 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
1230 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
1231 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
1232 GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
1233 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
1234 GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
1235 GATE_IP_DISP1, 7, 0, 0),
1236 GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
1237 GATE_IP_DISP1, 8, 0, 0),
1238 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1",
1239 GATE_IP_DISP1, 9, 0, 0),
1240};
1241
1242static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = {
1243 { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */
1244 { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */
1245 { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */
1246 { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */
1247 { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */
1248};
1249
1250static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = {
1251 DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
1252 DIV2_RATIO0, 4, 2),
1253};
1254
1255static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = {
1256 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
1257 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
1258 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
1259 GATE_IP_GSCL1, 6, 0, 0),
1260 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
1261 GATE_IP_GSCL1, 7, 0, 0),
1262};
1263
1264static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
1265 { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */
1266 { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */
1267 { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */
1268 { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */
1269};
1270
1271static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = {
1272 DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
1273};
1274
1275static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = {
cba9d2fa 1276 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
1d87db4d
SAB		 1277 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
1278 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
ec4016ff 1279};
cba9d2fa 1280
ec4016ff
MS		 1281static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = {
1282 { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */
1283 { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */
1284 { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */
1285};
1286
1287static const struct exynos5_subcmu_info exynos5x_subcmus[] = {
1288 {
1289 .div_clks = exynos5x_disp_div_clks,
1290 .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks),
1291 .gate_clks = exynos5x_disp_gate_clks,
1292 .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks),
1293 .suspend_regs = exynos5x_disp_suspend_regs,
1294 .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs),
1295 .pd_name = "DISP",
1296 }, {
1297 .div_clks = exynos5x_gsc_div_clks,
1298 .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks),
1299 .gate_clks = exynos5x_gsc_gate_clks,
1300 .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks),
1301 .suspend_regs = exynos5x_gsc_suspend_regs,
1302 .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs),
1303 .pd_name = "GSC",
1304 }, {
1305 .div_clks = exynos5x_mfc_div_clks,
1306 .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks),
1307 .gate_clks = exynos5x_mfc_gate_clks,
1308 .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks),
1309 .suspend_regs = exynos5x_mfc_suspend_regs,
1310 .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs),
1311 .pd_name = "MFC",
1312 },
1609027f
CK		 1313};
1314
ebd217e1 1315static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
1d5013f1
AH		 1316 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
1317 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
1318 PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
1319 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
1320 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1321 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1322 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1323 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1324 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1),
1325 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
1326 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
1327 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 2, 1),
1328 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
1329 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
1330 PLL_35XX_RATE(24 * MHZ, 600000000, 200, 2, 2),
1331 PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),
1332 PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),
1333 PLL_35XX_RATE(24 * MHZ, 300000000, 200, 2, 3),
1334 PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
ca5b4029
TA		 1335};
1336
8b4a7acf
LL		 1337static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = {
1338 PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1),
1339 PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1),
1340 PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
1341 PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2),
1342 PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2),
1343 PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3),
1344 PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3),
1345 PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3),
1346};
1347
9842452a 1348static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
1d5013f1
AH		 1349 PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
1350 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
1351 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
1352 PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671),
1353 PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
1354 PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
1355 PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671),
1356 PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719),
1357 PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
948e0684
SN		 1358 PLL_36XX_RATE(24 * MHZ, 73728000U, 98, 2, 4, 19923),
1359 PLL_36XX_RATE(24 * MHZ, 67737602U, 90, 2, 4, 20762),
1d5013f1
AH		 1360 PLL_36XX_RATE(24 * MHZ, 65536003U, 131, 3, 4, 4719),
1361 PLL_36XX_RATE(24 * MHZ, 49152000U, 197, 3, 5, -25690),
948e0684 1362 PLL_36XX_RATE(24 * MHZ, 45158401U, 90, 3, 4, 20762),
1d5013f1 1363 PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719),
9842452a
SN		 1364};
1365
6520e968 1366static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
cba9d2fa 1367 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
3ff6e0d8 1368 APLL_CON0, NULL),
cba9d2fa 1369 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
cdf64eee 1370 CPLL_CON0, NULL),
cba9d2fa 1371 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
3ff6e0d8 1372 DPLL_CON0, NULL),
9842452a 1373 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
3ff6e0d8 1374 EPLL_CON0, NULL),
cba9d2fa 1375 [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
3ff6e0d8 1376 RPLL_CON0, NULL),
cba9d2fa 1377 [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
3ff6e0d8 1378 IPLL_CON0, NULL),
cba9d2fa 1379 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
3ff6e0d8 1380 SPLL_CON0, NULL),
cba9d2fa 1381 [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
3ff6e0d8 1382 VPLL_CON0, NULL),
cba9d2fa 1383 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
3ff6e0d8 1384 MPLL_CON0, NULL),
cba9d2fa 1385 [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
3ff6e0d8 1386 BPLL_CON0, NULL),
cba9d2fa 1387 [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
3ff6e0d8 1388 KPLL_CON0, NULL),
c898c6b7
YSB		 1389};
1390
bee4f87f
TA		 1391#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \
1392 ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
1393 ((cpud) << 4)))
1394
1395static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
1396 { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
1397 { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
1398 { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
1399 { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
1400 { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
1401 { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
1402 { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
1403 { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
1404 { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), },
1405 { 900000, E5420_EGL_DIV0(3, 6, 6, 2), },
1406 { 800000, E5420_EGL_DIV0(3, 5, 5, 2), },
1407 { 700000, E5420_EGL_DIV0(3, 5, 5, 2), },
1408 { 600000, E5420_EGL_DIV0(3, 4, 4, 2), },
1409 { 500000, E5420_EGL_DIV0(3, 3, 3, 2), },
1410 { 400000, E5420_EGL_DIV0(3, 3, 3, 2), },
1411 { 300000, E5420_EGL_DIV0(3, 3, 3, 2), },
1412 { 200000, E5420_EGL_DIV0(3, 3, 3, 2), },
1413 { 0 },
1414};
1415
54abbdb4
BZ		 1416static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
1417 { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
1418 { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
1419 { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
1420 { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
1421 { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
1422 { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
1423 { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
1424 { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
1425 { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
1426 { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
1427 { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
1428 { 900000, E5420_EGL_DIV0(3, 7, 6, 2), },
1429 { 800000, E5420_EGL_DIV0(3, 7, 5, 2), },
1430 { 700000, E5420_EGL_DIV0(3, 7, 5, 2), },
1431 { 600000, E5420_EGL_DIV0(3, 7, 4, 2), },
1432 { 500000, E5420_EGL_DIV0(3, 7, 3, 2), },
1433 { 400000, E5420_EGL_DIV0(3, 7, 3, 2), },
1434 { 300000, E5420_EGL_DIV0(3, 7, 3, 2), },
1435 { 200000, E5420_EGL_DIV0(3, 7, 3, 2), },
1436 { 0 },
1437};
1438
bee4f87f
TA		 1439#define E5420_KFC_DIV(kpll, pclk, aclk) \
1440 ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
1441
1442static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
54abbdb4 1443 { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
bee4f87f
TA		 1444 { 1300000, E5420_KFC_DIV(3, 5, 2), },
1445 { 1200000, E5420_KFC_DIV(3, 5, 2), },
1446 { 1100000, E5420_KFC_DIV(3, 5, 2), },
1447 { 1000000, E5420_KFC_DIV(3, 5, 2), },
1448 { 900000, E5420_KFC_DIV(3, 5, 2), },
1449 { 800000, E5420_KFC_DIV(3, 5, 2), },
1450 { 700000, E5420_KFC_DIV(3, 4, 2), },
1451 { 600000, E5420_KFC_DIV(3, 4, 2), },
1452 { 500000, E5420_KFC_DIV(3, 4, 2), },
1453 { 400000, E5420_KFC_DIV(3, 3, 2), },
1454 { 300000, E5420_KFC_DIV(3, 3, 2), },
1455 { 200000, E5420_KFC_DIV(3, 3, 2), },
1456 { 0 },
1457};
1458
305cfab0 1459static const struct of_device_id ext_clk_match[] __initconst = {
1609027f
CK		 1460 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
1461 { },
1462};
1463
1464/* register exynos5420 clocks */
6520e968
AA		 1465static void __init exynos5x_clk_init(struct device_node *np,
1466 enum exynos5x_soc soc)
1609027f 1467{
976face4
RS		 1468 struct samsung_clk_provider *ctx;
1469
1609027f
CK		 1470 if (np) {
1471 reg_base = of_iomap(np, 0);
1472 if (!reg_base)
1473 panic("%s: failed to map registers\n", __func__);
1474 } else {
1475 panic("%s: unable to determine soc\n", __func__);
1476 }
1477
6520e968
AA		 1478 exynos5x_soc = soc;
1479
976face4 1480 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
976face4 1481
6520e968
AA		 1482 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
1483 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
1609027f 1484 ext_clk_match);
ca5b4029
TA		 1485
1486 if (_get_rate("fin_pll") == 24 * MHZ) {
1487 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
9842452a 1488 exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
ca5b4029
TA		 1489 exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1490 }
1491
8b4a7acf
LL		 1492 if (soc == EXYNOS5420)
1493 exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1494 else
1495 exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table;
1496
6520e968
AA		 1497 samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
1498 reg_base);
1499 samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
1500 ARRAY_SIZE(exynos5x_fixed_rate_clks));
1501 samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,
1502 ARRAY_SIZE(exynos5x_fixed_factor_clks));
1503 samsung_clk_register_mux(ctx, exynos5x_mux_clks,
1504 ARRAY_SIZE(exynos5x_mux_clks));
1505 samsung_clk_register_div(ctx, exynos5x_div_clks,
1506 ARRAY_SIZE(exynos5x_div_clks));
1507 samsung_clk_register_gate(ctx, exynos5x_gate_clks,
1508 ARRAY_SIZE(exynos5x_gate_clks));
1509
1510 if (soc == EXYNOS5420) {
1511 samsung_clk_register_mux(ctx, exynos5420_mux_clks,
1512 ARRAY_SIZE(exynos5420_mux_clks));
1513 samsung_clk_register_div(ctx, exynos5420_div_clks,
1514 ARRAY_SIZE(exynos5420_div_clks));
41097f25
SN		 1515 samsung_clk_register_gate(ctx, exynos5420_gate_clks,
1516 ARRAY_SIZE(exynos5420_gate_clks));
6520e968
AA		 1517 } else {
1518 samsung_clk_register_fixed_factor(
1519 ctx, exynos5800_fixed_factor_clks,
1520 ARRAY_SIZE(exynos5800_fixed_factor_clks));
1521 samsung_clk_register_mux(ctx, exynos5800_mux_clks,
1522 ARRAY_SIZE(exynos5800_mux_clks));
1523 samsung_clk_register_div(ctx, exynos5800_div_clks,
1524 ARRAY_SIZE(exynos5800_div_clks));
1525 samsung_clk_register_gate(ctx, exynos5800_gate_clks,
1526 ARRAY_SIZE(exynos5800_gate_clks));
1527 }
388c7885 1528
54abbdb4
BZ		 1529 if (soc == EXYNOS5420) {
1530 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1531 mout_cpu_p[0], mout_cpu_p[1], 0x200,
1532 exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
1533 } else {
1534 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1535 mout_cpu_p[0], mout_cpu_p[1], 0x200,
1536 exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
1537 }
bee4f87f
TA		 1538 exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
1539 mout_kfc_p[0], mout_kfc_p[1], 0x28200,
1540 exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
1541
2d77f77c
MS		 1542 samsung_clk_extended_sleep_init(reg_base,
1543 exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs),
1544 exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc));
1545 if (soc == EXYNOS5800)
1546 samsung_clk_sleep_init(reg_base, exynos5800_clk_regs,
1547 ARRAY_SIZE(exynos5800_clk_regs));
ec4016ff
MS		 1548 exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus),
1549 exynos5x_subcmus);
d5e136a2
SN		 1550
1551 samsung_clk_of_add_provider(np, ctx);
1609027f 1552}
6520e968
AA		 1553
1554static void __init exynos5420_clk_init(struct device_node *np)
1555{
1556 exynos5x_clk_init(np, EXYNOS5420);
1557}
ec4016ff
MS		 1558CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock",
1559 exynos5420_clk_init);
6520e968
AA		 1560
1561static void __init exynos5800_clk_init(struct device_node *np)
1562{
1563 exynos5x_clk_init(np, EXYNOS5800);
1564}
ec4016ff
MS		 1565CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock",
1566 exynos5800_clk_init);
Linux 6.x block layer and io_uring tree(s)