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Merge tag 'spi-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
[linux-2.6-block.git] / drivers / clk / samsung / clk-exynos5250.c
CommitLineData
6e3ad268
TA		 1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Common Clock Framework support for Exynos5250 SoC.
11*/
12
2fe8f00c 13#include <dt-bindings/clock/exynos5250.h>
6e3ad268
TA		 14#include <linux/clk-provider.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
c3b6c1d7 17#include <linux/syscore_ops.h>
6e3ad268 18
6e3ad268 19#include "clk.h"
d7cc4c81 20#include "clk-cpu.h"
6e3ad268 21
8dac3530
YSB		 22#define APLL_LOCK 0x0
23#define APLL_CON0 0x100
6e3ad268
TA		 24#define SRC_CPU 0x200
25#define DIV_CPU0 0x500
9a8f3995
ADK		 26#define PWR_CTRL1 0x1020
27#define PWR_CTRL2 0x1024
8dac3530
YSB		 28#define MPLL_LOCK 0x4000
29#define MPLL_CON0 0x4100
6e3ad268 30#define SRC_CORE1 0x4204
3bf34666 31#define GATE_IP_ACP 0x8800
bfed1074
CK		 32#define GATE_IP_ISP0 0xc800
33#define GATE_IP_ISP1 0xc804
8dac3530
YSB		 34#define CPLL_LOCK 0x10020
35#define EPLL_LOCK 0x10030
36#define VPLL_LOCK 0x10040
37#define GPLL_LOCK 0x10050
38#define CPLL_CON0 0x10120
39#define EPLL_CON0 0x10130
40#define VPLL_CON0 0x10140
41#define GPLL_CON0 0x10150
6e3ad268 42#define SRC_TOP0 0x10210
20b82ae2 43#define SRC_TOP1 0x10214
6e3ad268 44#define SRC_TOP2 0x10218
796d1f4c 45#define SRC_TOP3 0x1021c
6e3ad268
TA		 46#define SRC_GSCL 0x10220
47#define SRC_DISP1_0 0x1022c
48#define SRC_MAU 0x10240
49#define SRC_FSYS 0x10244
50#define SRC_GEN 0x10248
51#define SRC_PERIC0 0x10250
52#define SRC_PERIC1 0x10254
53#define SRC_MASK_GSCL 0x10320
54#define SRC_MASK_DISP1_0 0x1032c
55#define SRC_MASK_MAU 0x10334
56#define SRC_MASK_FSYS 0x10340
57#define SRC_MASK_GEN 0x10344
58#define SRC_MASK_PERIC0 0x10350
59#define SRC_MASK_PERIC1 0x10354
60#define DIV_TOP0 0x10510
61#define DIV_TOP1 0x10514
62#define DIV_GSCL 0x10520
63#define DIV_DISP1_0 0x1052c
64#define DIV_GEN 0x1053c
65#define DIV_MAU 0x10544
66#define DIV_FSYS0 0x10548
67#define DIV_FSYS1 0x1054c
68#define DIV_FSYS2 0x10550
69#define DIV_PERIC0 0x10558
70#define DIV_PERIC1 0x1055c
71#define DIV_PERIC2 0x10560
72#define DIV_PERIC3 0x10564
73#define DIV_PERIC4 0x10568
74#define DIV_PERIC5 0x1056c
75#define GATE_IP_GSCL 0x10920
2786c962 76#define GATE_IP_DISP1 0x10928
6e3ad268 77#define GATE_IP_MFC 0x1092c
20b82ae2 78#define GATE_IP_G3D 0x10930
6e3ad268
TA		 79#define GATE_IP_GEN 0x10934
80#define GATE_IP_FSYS 0x10944
81#define GATE_IP_PERIC 0x10950
82#define GATE_IP_PERIS 0x10960
8dac3530
YSB		 83#define BPLL_LOCK 0x20010
84#define BPLL_CON0 0x20110
6e3ad268
TA		 85#define SRC_CDREX 0x20200
86#define PLL_DIV2_SEL 0x20a24
87
9a8f3995
ADK		 88/*Below definitions are used for PWR_CTRL settings*/
89#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
90#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
91#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
92#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
93#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
94#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
95#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
96#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
97
98#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
99#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
100#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
101#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
102#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
103#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
104
8dac3530
YSB		 105/* list of PLLs to be registered */
106enum exynos5250_plls {
107 apll, mpll, cpll, epll, vpll, gpll, bpll,
108 nr_plls /* number of PLLs */
109};
110
c3b6c1d7
TF		 111static void __iomem *reg_base;
112
113#ifdef CONFIG_PM_SLEEP
114static struct samsung_clk_reg_dump *exynos5250_save;
115
6e3ad268
TA		 116/*
117 * list of controller registers to be saved and restored during a
118 * suspend/resume cycle.
119 */
b6993ecb 120static unsigned long exynos5250_clk_regs[] __initdata = {
6e3ad268
TA		 121 SRC_CPU,
122 DIV_CPU0,
9a8f3995
ADK		 123 PWR_CTRL1,
124 PWR_CTRL2,
6e3ad268
TA		 125 SRC_CORE1,
126 SRC_TOP0,
20b82ae2 127 SRC_TOP1,
6e3ad268 128 SRC_TOP2,
796d1f4c 129 SRC_TOP3,
6e3ad268
TA		 130 SRC_GSCL,
131 SRC_DISP1_0,
132 SRC_MAU,
133 SRC_FSYS,
134 SRC_GEN,
135 SRC_PERIC0,
136 SRC_PERIC1,
137 SRC_MASK_GSCL,
138 SRC_MASK_DISP1_0,
139 SRC_MASK_MAU,
140 SRC_MASK_FSYS,
141 SRC_MASK_GEN,
142 SRC_MASK_PERIC0,
143 SRC_MASK_PERIC1,
144 DIV_TOP0,
145 DIV_TOP1,
146 DIV_GSCL,
147 DIV_DISP1_0,
148 DIV_GEN,
149 DIV_MAU,
150 DIV_FSYS0,
151 DIV_FSYS1,
152 DIV_FSYS2,
153 DIV_PERIC0,
154 DIV_PERIC1,
155 DIV_PERIC2,
156 DIV_PERIC3,
157 DIV_PERIC4,
158 DIV_PERIC5,
159 GATE_IP_GSCL,
160 GATE_IP_MFC,
20b82ae2 161 GATE_IP_G3D,
6e3ad268
TA		 162 GATE_IP_GEN,
163 GATE_IP_FSYS,
164 GATE_IP_PERIC,
165 GATE_IP_PERIS,
166 SRC_CDREX,
167 PLL_DIV2_SEL,
17d4cacc 168 GATE_IP_DISP1,
406c5989 169 GATE_IP_ACP,
bfed1074
CK		 170 GATE_IP_ISP0,
171 GATE_IP_ISP1,
6e3ad268
TA		 172};
173
c3b6c1d7
TF		 174static int exynos5250_clk_suspend(void)
175{
176 samsung_clk_save(reg_base, exynos5250_save,
177 ARRAY_SIZE(exynos5250_clk_regs));
178
179 return 0;
180}
181
182static void exynos5250_clk_resume(void)
183{
184 samsung_clk_restore(reg_base, exynos5250_save,
185 ARRAY_SIZE(exynos5250_clk_regs));
186}
187
188static struct syscore_ops exynos5250_clk_syscore_ops = {
189 .suspend = exynos5250_clk_suspend,
190 .resume = exynos5250_clk_resume,
191};
192
193static void exynos5250_clk_sleep_init(void)
194{
195 exynos5250_save = samsung_clk_alloc_reg_dump(exynos5250_clk_regs,
196 ARRAY_SIZE(exynos5250_clk_regs));
197 if (!exynos5250_save) {
198 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
199 __func__);
200 return;
201 }
202
203 register_syscore_ops(&exynos5250_clk_syscore_ops);
204}
205#else
206static void exynos5250_clk_sleep_init(void) {}
207#endif
208
6e3ad268
TA		 209/* list of all parent clock list */
210PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
38ee3754 211PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
6e3ad268
TA		 212PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
213PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
214PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
215PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" };
216PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
217PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
218PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
219PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
20b82ae2 220PNAME(mout_gpll_p) = { "fin_pll", "fout_gpll" };
38ee3754
TF		 221PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" };
222PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" };
223PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" };
224PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" };
20b82ae2 225PNAME(mout_aclk400_p) = { "mout_aclk400_g3d_mid", "mout_gpll" };
3818f117 226PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
796d1f4c 227PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
96987ded 228PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
bfed1074 229PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" };
6e3ad268 230PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
38ee3754 231PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" };
6e3ad268
TA		 232PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
233 "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
38ee3754 234 "mout_mpll_user", "mout_epll", "mout_vpll",
256dd646
TF		 235 "mout_cpll", "none", "none",
236 "none", "none", "none",
237 "none" };
6e3ad268 238PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
bfeb9f27 239 "sclk_uhostphy", "fin_pll",
38ee3754 240 "mout_mpll_user", "mout_epll", "mout_vpll",
256dd646
TF		 241 "mout_cpll", "none", "none",
242 "none", "none", "none",
243 "none" };
6e3ad268 244PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
bfeb9f27 245 "sclk_uhostphy", "fin_pll",
38ee3754 246 "mout_mpll_user", "mout_epll", "mout_vpll",
256dd646
TF		 247 "mout_cpll", "none", "none",
248 "none", "none", "none",
249 "none" };
6e3ad268 250PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
bfeb9f27 251 "sclk_uhostphy", "fin_pll",
38ee3754 252 "mout_mpll_user", "mout_epll", "mout_vpll",
256dd646
TF		 253 "mout_cpll", "none", "none",
254 "none", "none", "none",
255 "none" };
6e3ad268
TA		 256PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
257 "spdif_extclk" };
258
259/* fixed rate clocks generated outside the soc */
b95e71c6 260static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
2fe8f00c 261 FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
6e3ad268
TA		 262};
263
264/* fixed rate clocks generated inside the soc */
b95e71c6 265static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
2fe8f00c
AH		 266 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
267 FRATE(0, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
268 FRATE(0, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
269 FRATE(0, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),
6e3ad268
TA		 270};
271
b95e71c6 272static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
2fe8f00c
AH		 273 FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
274 FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
6e3ad268
TA		 275};
276
8bc2eeb8 277static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = {
2fe8f00c 278 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
8bc2eeb8
VS		 279};
280
b95e71c6 281static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
2786c962
TF		 282 /*
283 * NOTE: Following table is sorted by (clock domain, register address,
284 * bitfield shift) triplet in ascending order. When adding new entries,
285 * please make sure that the order is kept, to avoid merge conflicts
286 * and make further work with defined data easier.
287 */
288
289 /*
290 * CMU_CPU
291 */
2fe8f00c 292 MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
e86ffc41 293 CLK_SET_RATE_PARENT, 0, "mout_apll"),
2fe8f00c 294 MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
2786c962
TF		 295
296 /*
297 * CMU_CORE
298 */
2fe8f00c 299 MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
2786c962
TF		 300
301 /*
302 * CMU_TOP
303 */
2fe8f00c
AH		 304 MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
305 MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
306 MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
20b82ae2
AK		 307 MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
308
bfed1074 309 MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1),
20b82ae2 310 MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1),
2fe8f00c
AH		 311
312 MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
313 MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1),
314 MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
315 MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
316 MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
20b82ae2 317 MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1),
2fe8f00c
AH		 318
319 MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1),
320 MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
bfed1074
CK		 321 MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p, SRC_TOP3, 16, 1),
322 MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p,
323 SRC_TOP3, 20, 1),
2fe8f00c
AH		 324 MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1),
325
326 MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
327 MUX(0, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
328 MUX(0, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
329 MUX(0, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
330 MUX(0, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
331
332 MUX(0, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
333 MUX(0, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
334 MUX(0, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
335 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
336
337 MUX(0, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
338
339 MUX(0, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
340 MUX(0, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
341 MUX(0, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
342 MUX(0, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
343 MUX(0, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
344 MUX(0, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
345
346 MUX(0, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
347
348 MUX(0, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
349 MUX(0, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
350 MUX(0, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
351 MUX(0, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
352 MUX(0, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
353
354 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
355 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
356 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
357 MUX(0, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
358 MUX(0, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
359 MUX(0, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
2786c962
TF		 360
361 /*
362 * CMU_CDREX
363 */
2fe8f00c 364 MUX(0, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
2786c962 365
2fe8f00c
AH		 366 MUX(0, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
367 MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
6e3ad268
TA		 368};
369
b95e71c6 370static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
2786c962
TF		 371 /*
372 * NOTE: Following table is sorted by (clock domain, register address,
373 * bitfield shift) triplet in ascending order. When adding new entries,
374 * please make sure that the order is kept, to avoid merge conflicts
375 * and make further work with defined data easier.
376 */
377
378 /*
379 * CMU_CPU
380 */
2fe8f00c
AH		 381 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
382 DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
383 DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"),
2786c962
TF		 384
385 /*
386 * CMU_TOP
387 */
2fe8f00c
AH		 388 DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3),
389 DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
390 DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
391 DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3),
392 DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
20b82ae2
AK		 393 DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0,
394 24, 3),
2fe8f00c 395
bfed1074 396 DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3),
2fe8f00c
AH		 397 DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
398
399 DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
400 DIV(0, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
401 DIV(0, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
402 DIV(0, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
403 DIV(0, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
404
405 DIV(0, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
406 DIV(0, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
407 DIV_F(0, "div_mipi1_pre", "div_mipi1",
2786c962 408 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
2fe8f00c
AH		 409 DIV(0, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
410 DIV(CLK_SCLK_PIXEL, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0, 28, 4),
2786c962 411
2fe8f00c 412 DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
2786c962 413
2fe8f00c 414 DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
35399dda 415 DIV(CLK_DIV_PCM0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
2786c962 416
2fe8f00c
AH		 417 DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
418 DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
2786c962 419
2fe8f00c
AH		 420 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
421 DIV_F(0, "div_mmc_pre0", "div_mmc0",
2786c962 422 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
2fe8f00c
AH		 423 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
424 DIV_F(0, "div_mmc_pre1", "div_mmc1",
2786c962
TF		 425 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
426
2fe8f00c
AH		 427 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
428 DIV_F(0, "div_mmc_pre2", "div_mmc2",
2786c962 429 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
2fe8f00c
AH		 430 DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
431 DIV_F(0, "div_mmc_pre3", "div_mmc3",
2786c962
TF		 432 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
433
2fe8f00c
AH		 434 DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
435 DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
436 DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
437 DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
2786c962 438
2fe8f00c
AH		 439 DIV(0, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
440 DIV_F(0, "div_spi_pre0", "div_spi0",
2786c962 441 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
2fe8f00c
AH		 442 DIV(0, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
443 DIV_F(0, "div_spi_pre1", "div_spi1",
2786c962
TF		 444 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
445
2fe8f00c
AH		 446 DIV(0, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
447 DIV_F(0, "div_spi_pre2", "div_spi2",
2786c962
TF		 448 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
449
2fe8f00c 450 DIV(0, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
2786c962 451
2fe8f00c
AH		 452 DIV(0, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
453 DIV(0, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
454 DIV(0, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
455 DIV(0, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
2786c962 456
2fe8f00c
AH		 457 DIV(CLK_DIV_I2S1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
458 DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
6e3ad268
TA		 459};
460
b95e71c6 461static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
2786c962
TF		 462 /*
463 * NOTE: Following table is sorted by (clock domain, register address,
464 * bitfield shift) triplet in ascending order. When adding new entries,
465 * please make sure that the order is kept, to avoid merge conflicts
466 * and make further work with defined data easier.
467 */
468
469 /*
470 * CMU_ACP
471 */
2fe8f00c 472 GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
5b73721b 473 GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
2fe8f00c
AH		 474 GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
475 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
2786c962
TF		 476
477 /*
478 * CMU_TOP
479 */
2fe8f00c 480 GATE(CLK_SCLK_CAM_BAYER, "sclk_cam_bayer", "div_cam_bayer",
2786c962 481 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
2fe8f00c 482 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0",
2786c962 483 SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
2fe8f00c 484 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
2786c962 485 SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
2fe8f00c 486 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "div_gscl_wa",
2786c962 487 SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
2fe8f00c 488 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "div_gscl_wb",
2786c962
TF		 489 SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
490
2fe8f00c 491 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1",
2786c962 492 SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
2fe8f00c 493 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi1",
2786c962 494 SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
2fe8f00c 495 GATE(CLK_SCLK_DP, "sclk_dp", "div_dp",
2786c962 496 SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
2fe8f00c 497 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
2786c962
TF		 498 SRC_MASK_DISP1_0, 20, 0, 0),
499
2fe8f00c 500 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
2786c962
TF		 501 SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
502
2fe8f00c 503 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
2786c962 504 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
2fe8f00c 505 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
2786c962 506 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2fe8f00c 507 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
2786c962 508 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
2fe8f00c 509 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3",
2786c962 510 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
2fe8f00c 511 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
2786c962 512 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
2fe8f00c 513 GATE(CLK_SCLK_USB3, "sclk_usb3", "div_usb3",
2786c962
TF		 514 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
515
2fe8f00c 516 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
2786c962
TF		 517 SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
518
2fe8f00c 519 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
2786c962 520 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
2fe8f00c 521 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
2786c962 522 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
2fe8f00c 523 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
2786c962 524 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
2fe8f00c 525 GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
2786c962 526 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
2fe8f00c 527 GATE(CLK_SCLK_PWM, "sclk_pwm", "div_pwm",
2786c962
TF		 528 SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
529
2fe8f00c 530 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
2786c962 531 SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
2fe8f00c 532 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
2786c962 533 SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
2fe8f00c 534 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
2786c962 535 SRC_MASK_PERIC1, 4, 0, 0),
2fe8f00c 536 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0",
2786c962 537 SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
2fe8f00c 538 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1",
2786c962 539 SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
2fe8f00c 540 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2",
2786c962
TF		 541 SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
542
2fe8f00c
AH		 543 GATE(CLK_GSCL0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0,
544 0),
545 GATE(CLK_GSCL1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0,
546 0),
547 GATE(CLK_GSCL2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0,
548 0),
549 GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0,
550 0),
551 GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
552 GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
553 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub",
796d1f4c 554 GATE_IP_GSCL, 7, 0, 0),
2fe8f00c 555 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "mout_aclk266_gscl_sub",
796d1f4c 556 GATE_IP_GSCL, 8, 0, 0),
2fe8f00c 557 GATE(CLK_SMMU_GSCL2, "smmu_gscl2", "mout_aclk266_gscl_sub",
796d1f4c 558 GATE_IP_GSCL, 9, 0, 0),
2fe8f00c 559 GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub",
796d1f4c 560 GATE_IP_GSCL, 10, 0, 0),
38ee3754 561
2fe8f00c
AH		 562 GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0,
563 0),
564 GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0,
565 0),
566 GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0,
567 0),
568 GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0),
569 GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0,
570 0),
571 GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0,
572 0),
573
574 GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0),
575 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0,
576 0),
577 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
578 0),
20b82ae2
AK		 579 GATE(CLK_G3D, "g3d", "div_aclk400_g3d", GATE_IP_G3D, 0,
580 CLK_SET_RATE_PARENT, 0),
2fe8f00c
AH		 581 GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),
582 GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),
583 GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0),
584 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "div_aclk266", GATE_IP_GEN, 6, 0,
585 0),
586 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0),
587 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "div_aclk266", GATE_IP_GEN, 9, 0, 0),
588
589 GATE(CLK_PDMA0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0),
590 GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0),
591 GATE(CLK_SATA, "sata", "div_aclk200", GATE_IP_FSYS, 6, 0, 0),
592 GATE(CLK_USBOTG, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0),
593 GATE(CLK_MIPI_HSI, "mipi_hsi", "div_aclk200", GATE_IP_FSYS, 8, 0, 0),
594 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0),
595 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0),
596 GATE(CLK_SDMMC2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0),
597 GATE(CLK_SDMMC3, "sdmmc3", "div_aclk200", GATE_IP_FSYS, 15, 0, 0),
598 GATE(CLK_SROMC, "sromc", "div_aclk200", GATE_IP_FSYS, 17, 0, 0),
599 GATE(CLK_USB2, "usb2", "div_aclk200", GATE_IP_FSYS, 18, 0, 0),
600 GATE(CLK_USB3, "usb3", "div_aclk200", GATE_IP_FSYS, 19, 0, 0),
601 GATE(CLK_SATA_PHYCTRL, "sata_phyctrl", "div_aclk200",
38ee3754 602 GATE_IP_FSYS, 24, 0, 0),
2fe8f00c
AH		 603 GATE(CLK_SATA_PHYI2C, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS, 25, 0,
604 0),
605
606 GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0),
607 GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0),
608 GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0),
609 GATE(CLK_UART3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0),
610 GATE(CLK_UART4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0),
611 GATE(CLK_I2C0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0),
612 GATE(CLK_I2C1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0),
613 GATE(CLK_I2C2, "i2c2", "div_aclk66", GATE_IP_PERIC, 8, 0, 0),
614 GATE(CLK_I2C3, "i2c3", "div_aclk66", GATE_IP_PERIC, 9, 0, 0),
615 GATE(CLK_I2C4, "i2c4", "div_aclk66", GATE_IP_PERIC, 10, 0, 0),
616 GATE(CLK_I2C5, "i2c5", "div_aclk66", GATE_IP_PERIC, 11, 0, 0),
617 GATE(CLK_I2C6, "i2c6", "div_aclk66", GATE_IP_PERIC, 12, 0, 0),
618 GATE(CLK_I2C7, "i2c7", "div_aclk66", GATE_IP_PERIC, 13, 0, 0),
619 GATE(CLK_I2C_HDMI, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC, 14, 0, 0),
620 GATE(CLK_ADC, "adc", "div_aclk66", GATE_IP_PERIC, 15, 0, 0),
621 GATE(CLK_SPI0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0),
622 GATE(CLK_SPI1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0),
623 GATE(CLK_SPI2, "spi2", "div_aclk66", GATE_IP_PERIC, 18, 0, 0),
624 GATE(CLK_I2S1, "i2s1", "div_aclk66", GATE_IP_PERIC, 20, 0, 0),
625 GATE(CLK_I2S2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0),
626 GATE(CLK_PCM1, "pcm1", "div_aclk66", GATE_IP_PERIC, 22, 0, 0),
627 GATE(CLK_PCM2, "pcm2", "div_aclk66", GATE_IP_PERIC, 23, 0, 0),
628 GATE(CLK_PWM, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0),
629 GATE(CLK_SPDIF, "spdif", "div_aclk66", GATE_IP_PERIC, 26, 0, 0),
630 GATE(CLK_AC97, "ac97", "div_aclk66", GATE_IP_PERIC, 27, 0, 0),
631 GATE(CLK_HSI2C0, "hsi2c0", "div_aclk66", GATE_IP_PERIC, 28, 0, 0),
632 GATE(CLK_HSI2C1, "hsi2c1", "div_aclk66", GATE_IP_PERIC, 29, 0, 0),
633 GATE(CLK_HSI2C2, "hsi2c2", "div_aclk66", GATE_IP_PERIC, 30, 0, 0),
634 GATE(CLK_HSI2C3, "hsi2c3", "div_aclk66", GATE_IP_PERIC, 31, 0, 0),
635
636 GATE(CLK_CHIPID, "chipid", "div_aclk66", GATE_IP_PERIS, 0, 0, 0),
637 GATE(CLK_SYSREG, "sysreg", "div_aclk66",
2feed5ae 638 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
2fe8f00c
AH		 639 GATE(CLK_PMU, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED,
640 0),
641 GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66",
2786c962 642 GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
2fe8f00c 643 GATE(CLK_CMU_CORE, "cmu_core", "div_aclk66",
2786c962 644 GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
2fe8f00c 645 GATE(CLK_CMU_MEM, "cmu_mem", "div_aclk66",
2786c962 646 GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
2fe8f00c
AH		 647 GATE(CLK_TZPC0, "tzpc0", "div_aclk66", GATE_IP_PERIS, 6, 0, 0),
648 GATE(CLK_TZPC1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0),
649 GATE(CLK_TZPC2, "tzpc2", "div_aclk66", GATE_IP_PERIS, 8, 0, 0),
650 GATE(CLK_TZPC3, "tzpc3", "div_aclk66", GATE_IP_PERIS, 9, 0, 0),
651 GATE(CLK_TZPC4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0),
652 GATE(CLK_TZPC5, "tzpc5", "div_aclk66", GATE_IP_PERIS, 11, 0, 0),
653 GATE(CLK_TZPC6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0),
654 GATE(CLK_TZPC7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0),
655 GATE(CLK_TZPC8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0),
656 GATE(CLK_TZPC9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0),
657 GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0),
658 GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0),
659 GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
660 GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
661 GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
bfed1074 662 GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
0b1643b3 663 GATE_IP_DISP1, 9, 0, 0),
bfed1074
CK		 664 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",
665 GATE_IP_DISP1, 8, 0, 0),
666 GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
667 GATE(CLK_SMMU_FIMC_ISP, "smmu_fimc_isp", "mout_aclk_266_isp_sub",
668 GATE_IP_ISP0, 8, 0, 0),
669 GATE(CLK_SMMU_FIMC_DRC, "smmu_fimc_drc", "mout_aclk_266_isp_sub",
670 GATE_IP_ISP0, 9, 0, 0),
671 GATE(CLK_SMMU_FIMC_FD, "smmu_fimc_fd", "mout_aclk_266_isp_sub",
672 GATE_IP_ISP0, 10, 0, 0),
673 GATE(CLK_SMMU_FIMC_SCC, "smmu_fimc_scc", "mout_aclk_266_isp_sub",
674 GATE_IP_ISP0, 11, 0, 0),
675 GATE(CLK_SMMU_FIMC_SCP, "smmu_fimc_scp", "mout_aclk_266_isp_sub",
676 GATE_IP_ISP0, 12, 0, 0),
677 GATE(CLK_SMMU_FIMC_MCU, "smmu_fimc_mcu", "mout_aclk_400_isp_sub",
678 GATE_IP_ISP0, 13, 0, 0),
679 GATE(CLK_SMMU_FIMC_ODC, "smmu_fimc_odc", "mout_aclk_266_isp_sub",
680 GATE_IP_ISP1, 4, 0, 0),
681 GATE(CLK_SMMU_FIMC_DIS0, "smmu_fimc_dis0", "mout_aclk_266_isp_sub",
682 GATE_IP_ISP1, 5, 0, 0),
683 GATE(CLK_SMMU_FIMC_DIS1, "smmu_fimc_dis1", "mout_aclk_266_isp_sub",
684 GATE_IP_ISP1, 6, 0, 0),
685 GATE(CLK_SMMU_FIMC_3DNR, "smmu_fimc_3dnr", "mout_aclk_266_isp_sub",
686 GATE_IP_ISP1, 7, 0, 0),
6e3ad268
TA		 687};
688
b6993ecb 689static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
d2127ac4
VS		 690 /* sorted in descending order */
691 /* PLL_36XX_RATE(rate, m, p, s, k) */
692 PLL_36XX_RATE(266000000, 266, 3, 3, 0),
693 /* Not in UM, but need for eDP on snow */
694 PLL_36XX_RATE(70500000, 94, 2, 4, 0),
695 { },
696};
697
b6993ecb 698static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = {
d2127ac4
VS		 699 /* sorted in descending order */
700 /* PLL_36XX_RATE(rate, m, p, s, k) */
701 PLL_36XX_RATE(192000000, 64, 2, 2, 0),
702 PLL_36XX_RATE(180633600, 90, 3, 2, 20762),
703 PLL_36XX_RATE(180000000, 90, 3, 2, 0),
704 PLL_36XX_RATE(73728000, 98, 2, 4, 19923),
705 PLL_36XX_RATE(67737600, 90, 2, 4, 20762),
706 PLL_36XX_RATE(49152000, 98, 3, 4, 19923),
707 PLL_36XX_RATE(45158400, 90, 3, 4, 20762),
708 PLL_36XX_RATE(32768000, 131, 3, 5, 4719),
709 { },
710};
711
f521ac8b
AB		 712static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = {
713 /* sorted in descending order */
714 /* PLL_35XX_RATE(rate, m, p, s) */
715 PLL_35XX_RATE(1700000000, 425, 6, 0),
716 PLL_35XX_RATE(1600000000, 200, 3, 0),
717 PLL_35XX_RATE(1500000000, 250, 4, 0),
718 PLL_35XX_RATE(1400000000, 175, 3, 0),
719 PLL_35XX_RATE(1300000000, 325, 6, 0),
720 PLL_35XX_RATE(1200000000, 200, 4, 0),
721 PLL_35XX_RATE(1100000000, 275, 6, 0),
722 PLL_35XX_RATE(1000000000, 125, 3, 0),
723 PLL_35XX_RATE(900000000, 150, 4, 0),
724 PLL_35XX_RATE(800000000, 100, 3, 0),
725 PLL_35XX_RATE(700000000, 175, 3, 1),
726 PLL_35XX_RATE(600000000, 200, 4, 1),
727 PLL_35XX_RATE(500000000, 125, 3, 1),
728 PLL_35XX_RATE(400000000, 100, 3, 1),
729 PLL_35XX_RATE(300000000, 200, 4, 2),
730 PLL_35XX_RATE(200000000, 100, 3, 2),
731};
732
b6993ecb 733static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
2fe8f00c
AH		 734 [apll] = PLL_A(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
735 APLL_LOCK, APLL_CON0, "fout_apll", NULL),
736 [mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
737 MPLL_LOCK, MPLL_CON0, "fout_mpll", NULL),
738 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
3ff6e0d8 739 BPLL_CON0, NULL),
2fe8f00c 740 [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
3ff6e0d8 741 GPLL_CON0, NULL),
2fe8f00c 742 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
3ff6e0d8 743 CPLL_CON0, NULL),
2fe8f00c 744 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
3ff6e0d8 745 EPLL_CON0, NULL),
2fe8f00c 746 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
3ff6e0d8 747 VPLL_LOCK, VPLL_CON0, NULL),
8dac3530
YSB		 748};
749
d7cc4c81
TA		 750#define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud) \
751 ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
752 ((periph) << 12) | ((acp) << 8) | ((cpud) << 4)))
753#define E5250_CPU_DIV1(hpm, copy) \
754 (((hpm) << 4) | (copy))
755
756static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {
757 { 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
758 { 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
759 { 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
760 { 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
761 { 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
762 { 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
763 { 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
764 { 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
765 { 900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
766 { 800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
767 { 700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
768 { 600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
769 { 500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
770 { 400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
771 { 300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
772 { 200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
773 { 0 },
774};
775
305cfab0 776static const struct of_device_id ext_clk_match[] __initconst = {
6e3ad268
TA		 777 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
778 { },
779};
780
781/* register exynox5250 clocks */
b95e71c6 782static void __init exynos5250_clk_init(struct device_node *np)
6e3ad268 783{
976face4 784 struct samsung_clk_provider *ctx;
9a8f3995 785 unsigned int tmp;
976face4 786
6e3ad268
TA		 787 if (np) {
788 reg_base = of_iomap(np, 0);
789 if (!reg_base)
790 panic("%s: failed to map registers\n", __func__);
791 } else {
792 panic("%s: unable to determine soc\n", __func__);
793 }
794
976face4
RS		 795 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
796 if (!ctx)
797 panic("%s: unable to allocate context.\n", __func__);
798 samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
6e3ad268
TA		 799 ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
800 ext_clk_match);
976face4 801 samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,
8bc2eeb8 802 ARRAY_SIZE(exynos5250_pll_pmux_clks));
d2127ac4 803
f521ac8b 804 if (_get_rate("fin_pll") == 24 * MHZ) {
d2127ac4 805 exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
f521ac8b
AB		 806 exynos5250_plls[apll].rate_table = apll_24mhz_tbl;
807 }
d2127ac4 808
22e9e758 809 if (_get_rate("mout_vpllsrc") == 24 * MHZ)
d2127ac4
VS		 810 exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
811
976face4
RS		 812 samsung_clk_register_pll(ctx, exynos5250_plls,
813 ARRAY_SIZE(exynos5250_plls),
814 reg_base);
815 samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks,
6e3ad268 816 ARRAY_SIZE(exynos5250_fixed_rate_clks));
976face4 817 samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks,
6e3ad268 818 ARRAY_SIZE(exynos5250_fixed_factor_clks));
976face4 819 samsung_clk_register_mux(ctx, exynos5250_mux_clks,
6e3ad268 820 ARRAY_SIZE(exynos5250_mux_clks));
976face4 821 samsung_clk_register_div(ctx, exynos5250_div_clks,
6e3ad268 822 ARRAY_SIZE(exynos5250_div_clks));
976face4 823 samsung_clk_register_gate(ctx, exynos5250_gate_clks,
6e3ad268 824 ARRAY_SIZE(exynos5250_gate_clks));
d7cc4c81
TA		 825 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
826 mout_cpu_p[0], mout_cpu_p[1], 0x200,
827 exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),
828 CLK_CPU_HAS_DIV1);
6e3ad268 829
9a8f3995
ADK		 830 /*
831 * Enable arm clock down (in idle) and set arm divider
832 * ratios in WFI/WFE state.
833 */
834 tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO |
835 PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
836 PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
837 PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
838 __raw_writel(tmp, reg_base + PWR_CTRL1);
839
840 /*
841 * Enable arm clock up (on exiting idle). Set arm divider
842 * ratios when not in idle along with the standby duration
843 * ratios.
844 */
845 tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |
846 PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL |
847 PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
848 __raw_writel(tmp, reg_base + PWR_CTRL2);
849
c3b6c1d7
TF		 850 exynos5250_clk_sleep_init();
851
d5e136a2
SN		 852 samsung_clk_of_add_provider(np, ctx);
853
6e3ad268 854 pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
38ee3754 855 _get_rate("div_arm2"));
6e3ad268
TA		 856}
857CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
Linux 6.x block layer and io_uring tree(s)