[linux-2.6-block.git] / drivers / clk / samsung / clk-exynos-audss.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 * Author: Padmavathi Venna <padma.v@samsung.com>
 *
 * Common Clock Framework support for Audio Subsystem Clock Controller.
*/

#include <linux/slab.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>

#include <dt-bindings/clock/exynos-audss-clk.h>

static DEFINE_SPINLOCK(lock);
static void __iomem *reg_base;
static struct clk_hw_onecell_data *clk_data;
/*
 * On Exynos5420 this will be a clock which has to be enabled before any
 * access to audss registers. Typically a child of EPLL.
 *
 * On other platforms this will be -ENODEV.
 */
static struct clk *epll;

#define ASS_CLK_SRC 0x0
#define ASS_CLK_DIV 0x4
#define ASS_CLK_GATE 0x8

static unsigned long reg_save[][2] = {
	{ ASS_CLK_SRC,  0 },
	{ ASS_CLK_DIV,  0 },
	{ ASS_CLK_GATE, 0 },
};

static int __maybe_unused exynos_audss_clk_suspend(struct device *dev)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
		reg_save[i][1] = readl(reg_base + reg_save[i][0]);

	return 0;
}

static int __maybe_unused exynos_audss_clk_resume(struct device *dev)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
		writel(reg_save[i][1], reg_base + reg_save[i][0]);

	return 0;
}

struct exynos_audss_clk_drvdata {
	unsigned int has_adma_clk:1;
	unsigned int has_mst_clk:1;
	unsigned int enable_epll:1;
	unsigned int num_clks;
};

static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
	.num_clks	= EXYNOS_AUDSS_MAX_CLKS - 1,
	.enable_epll	= 1,
};

static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
	.num_clks	= EXYNOS_AUDSS_MAX_CLKS - 1,
	.has_mst_clk	= 1,
};

static const struct exynos_audss_clk_drvdata exynos5420_drvdata = {
	.num_clks	= EXYNOS_AUDSS_MAX_CLKS,
	.has_adma_clk	= 1,
	.enable_epll	= 1,
};

static const struct of_device_id exynos_audss_clk_of_match[] = {
	{
		.compatible	= "samsung,exynos4210-audss-clock",
		.data		= &exynos4210_drvdata,
	}, {
		.compatible	= "samsung,exynos5250-audss-clock",
		.data		= &exynos4210_drvdata,
	}, {
		.compatible	= "samsung,exynos5410-audss-clock",
		.data		= &exynos5410_drvdata,
	}, {
		.compatible	= "samsung,exynos5420-audss-clock",
		.data		= &exynos5420_drvdata,
	},
	{ },
};
MODULE_DEVICE_TABLE(of, exynos_audss_clk_of_match);

static void exynos_audss_clk_teardown(void)
{
	int i;

	for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
		if (!IS_ERR(clk_data->hws[i]))
			clk_hw_unregister_mux(clk_data->hws[i]);
	}

	for (; i < EXYNOS_SRP_CLK; i++) {
		if (!IS_ERR(clk_data->hws[i]))
			clk_hw_unregister_divider(clk_data->hws[i]);
	}

	for (; i < clk_data->num; i++) {
		if (!IS_ERR(clk_data->hws[i]))
			clk_hw_unregister_gate(clk_data->hws[i]);
	}
}

/* register exynos_audss clocks */
static int exynos_audss_clk_probe(struct platform_device *pdev)
{
	const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
	const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
	const char *sclk_pcm_p = "sclk_pcm0";
	struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
	const struct exynos_audss_clk_drvdata *variant;
	struct clk_hw **clk_table;
	struct device *dev = &pdev->dev;
	int i, ret = 0;

	variant = of_device_get_match_data(&pdev->dev);
	if (!variant)
		return -EINVAL;

	reg_base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(reg_base))
		return PTR_ERR(reg_base);

	epll = ERR_PTR(-ENODEV);

	clk_data = devm_kzalloc(dev,
				struct_size(clk_data, hws,
					    EXYNOS_AUDSS_MAX_CLKS),
				GFP_KERNEL);
	if (!clk_data)
		return -ENOMEM;

	clk_data->num = variant->num_clks;
	clk_table = clk_data->hws;

	pll_ref = devm_clk_get(dev, "pll_ref");
	pll_in = devm_clk_get(dev, "pll_in");
	if (!IS_ERR(pll_ref))
		mout_audss_p[0] = __clk_get_name(pll_ref);
	if (!IS_ERR(pll_in)) {
		mout_audss_p[1] = __clk_get_name(pll_in);

		if (variant->enable_epll) {
			epll = pll_in;

			ret = clk_prepare_enable(epll);
			if (ret) {
				dev_err(dev,
					"failed to prepare the epll clock\n");
				return ret;
			}
		}
	}

	/*
	 * Enable runtime PM here to allow the clock core using runtime PM
	 * for the registered clocks. Additionally, we increase the runtime
	 * PM usage count before registering the clocks, to prevent the
	 * clock core from runtime suspending the device.
	 */
	pm_runtime_get_noresume(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);

	clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss",
				mout_audss_p, ARRAY_SIZE(mout_audss_p),
				CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);

	cdclk = devm_clk_get(dev, "cdclk");
	sclk_audio = devm_clk_get(dev, "sclk_audio");
	if (!IS_ERR(cdclk))
		mout_i2s_p[1] = __clk_get_name(cdclk);
	if (!IS_ERR(sclk_audio))
		mout_i2s_p[2] = __clk_get_name(sclk_audio);
	clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s",
				mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
				CLK_SET_RATE_NO_REPARENT,
				reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);

	clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp",
				"mout_audss", CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);

	clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev,
				"dout_aud_bus", "dout_srp", CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);

	clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s",
				"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
				&lock);

	clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk",
				"dout_srp", CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_GATE, 0, 0, &lock);

	clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus",
				"dout_aud_bus", CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_GATE, 2, 0, &lock);

	clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s",
				"dout_i2s", CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_GATE, 3, 0, &lock);

	clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(dev, "pcm_bus",
				 "sclk_pcm", CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_GATE, 4, 0, &lock);

	sclk_pcm_in = devm_clk_get(dev, "sclk_pcm_in");
	if (!IS_ERR(sclk_pcm_in))
		sclk_pcm_p = __clk_get_name(sclk_pcm_in);
	clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(dev, "sclk_pcm",
				sclk_pcm_p, CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_GATE, 5, 0, &lock);

	if (variant->has_adma_clk) {
		clk_table[EXYNOS_ADMA] = clk_hw_register_gate(dev, "adma",
				"dout_srp", CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_GATE, 9, 0, &lock);
	}

	for (i = 0; i < clk_data->num; i++) {
		if (IS_ERR(clk_table[i])) {
			dev_err(dev, "failed to register clock %d\n", i);
			ret = PTR_ERR(clk_table[i]);
			goto unregister;
		}
	}

	ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
				     clk_data);
	if (ret) {
		dev_err(dev, "failed to add clock provider\n");
		goto unregister;
	}

	pm_runtime_put_sync(dev);

	return 0;

unregister:
	exynos_audss_clk_teardown();
	pm_runtime_put_sync(dev);
	pm_runtime_disable(dev);

	if (!IS_ERR(epll))
		clk_disable_unprepare(epll);

	return ret;
}

static void exynos_audss_clk_remove(struct platform_device *pdev)
{
	of_clk_del_provider(pdev->dev.of_node);

	exynos_audss_clk_teardown();
	pm_runtime_disable(&pdev->dev);

	if (!IS_ERR(epll))
		clk_disable_unprepare(epll);
}

static const struct dev_pm_ops exynos_audss_clk_pm_ops = {
	SET_RUNTIME_PM_OPS(exynos_audss_clk_suspend, exynos_audss_clk_resume,
			   NULL)
	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
				     pm_runtime_force_resume)
};

static struct platform_driver exynos_audss_clk_driver = {
	.driver	= {
		.name = "exynos-audss-clk",
		.of_match_table = exynos_audss_clk_of_match,
		.pm = &exynos_audss_clk_pm_ops,
	},
	.probe = exynos_audss_clk_probe,
	.remove = exynos_audss_clk_remove,
};

module_platform_driver(exynos_audss_clk_driver);

MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:exynos-audss-clk");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
1241ef94 PV	2	/*
	3	* Copyright (c) 2013 Samsung Electronics Co., Ltd.
	4	* Author: Padmavathi Venna <padma.v@samsung.com>
	5	*
1241ef94 PV	6	* Common Clock Framework support for Audio Subsystem Clock Controller.
	7	*/
	8
6f1ed07a	9	#include <linux/slab.h>
1241ef94	10	#include <linux/io.h>
6f1ed07a	11	#include <linux/clk.h>
1241ef94	12	#include <linux/clk-provider.h>
a96cbb14	13	#include <linux/of.h>
b37a4224 AB	14	#include <linux/module.h>
b37a4224 AB	15	#include <linux/platform_device.h>
ae432a9b	16	#include <linux/pm_runtime.h>
1241ef94	17
602408e3	18	#include <dt-bindings/clock/exynos-audss-clk.h>
1241ef94 PV	19
1241ef94 PV	20	static DEFINE_SPINLOCK(lock);
1241ef94	21	static void __iomem *reg_base;
5b2c3da1	22	static struct clk_hw_onecell_data *clk_data;
f1e9203e KK	23	/*
	24	* On Exynos5420 this will be a clock which has to be enabled before any
	25	* access to audss registers. Typically a child of EPLL.
	26	*
	27	* On other platforms this will be -ENODEV.
	28	*/
	29	static struct clk *epll;
1241ef94 PV	30
	31	#define ASS_CLK_SRC 0x0
	32	#define ASS_CLK_DIV 0x4
	33	#define ASS_CLK_GATE 0x8
	34
	35	static unsigned long reg_save[][2] = {
c17a6163 SN	36	{ ASS_CLK_SRC, 0 },
	37	{ ASS_CLK_DIV, 0 },
	38	{ ASS_CLK_GATE, 0 },
1241ef94 PV	39	};
1241ef94 PV	40
ae432a9b	41	static int __maybe_unused exynos_audss_clk_suspend(struct device *dev)
1241ef94 PV	42	{
	43	int i;
	44
	45	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
	46	reg_save[i][1] = readl(reg_base + reg_save[i][0]);
	47
	48	return 0;
	49	}
	50
ae432a9b	51	static int __maybe_unused exynos_audss_clk_resume(struct device *dev)
1241ef94 PV	52	{
	53	int i;
	54
	55	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
	56	writel(reg_save[i][1], reg_base + reg_save[i][0]);
1241ef94	57
a5b16dfa MS	58	return 0;
a5b16dfa MS	59	}
1241ef94	60
7c3ca061 SN	61	struct exynos_audss_clk_drvdata {
7c3ca061 SN	62	unsigned int has_adma_clk:1;
2ec865b7	63	unsigned int has_mst_clk:1;
7c3ca061 SN	64	unsigned int enable_epll:1;
	65	unsigned int num_clks;
	66	};
	67
	68	static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
	69	.num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
5bb4053b	70	.enable_epll = 1,
7c3ca061 SN	71	};
7c3ca061 SN	72
2ec865b7 SN	73	static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
	74	.num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
	75	.has_mst_clk = 1,
	76	};
	77
7c3ca061 SN	78	static const struct exynos_audss_clk_drvdata exynos5420_drvdata = {
	79	.num_clks = EXYNOS_AUDSS_MAX_CLKS,
	80	.has_adma_clk = 1,
	81	.enable_epll = 1,
	82	};
	83
3538a2cf	84	static const struct of_device_id exynos_audss_clk_of_match[] = {
7c3ca061 SN	85	{
	86	.compatible = "samsung,exynos4210-audss-clock",
	87	.data = &exynos4210_drvdata,
	88	}, {
	89	.compatible = "samsung,exynos5250-audss-clock",
	90	.data = &exynos4210_drvdata,
2ec865b7 SN	91	}, {
	92	.compatible = "samsung,exynos5410-audss-clock",
	93	.data = &exynos5410_drvdata,
7c3ca061 SN	94	}, {
	95	.compatible = "samsung,exynos5420-audss-clock",
	96	.data = &exynos5420_drvdata,
	97	},
	98	{ },
3538a2cf	99	};
34b89b29	100	MODULE_DEVICE_TABLE(of, exynos_audss_clk_of_match);
3538a2cf	101
27c76c43 KK	102	static void exynos_audss_clk_teardown(void)
	103	{
	104	int i;
	105
	106	for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
5b2c3da1 MS	107	if (!IS_ERR(clk_data->hws[i]))
5b2c3da1 MS	108	clk_hw_unregister_mux(clk_data->hws[i]);
27c76c43 KK	109	}
	110
	111	for (; i < EXYNOS_SRP_CLK; i++) {
5b2c3da1 MS	112	if (!IS_ERR(clk_data->hws[i]))
5b2c3da1 MS	113	clk_hw_unregister_divider(clk_data->hws[i]);
27c76c43 KK	114	}
27c76c43 KK	115
5b2c3da1 MS	116	for (; i < clk_data->num; i++) {
	117	if (!IS_ERR(clk_data->hws[i]))
	118	clk_hw_unregister_gate(clk_data->hws[i]);
27c76c43 KK	119	}
	120	}
	121
1241ef94	122	/* register exynos_audss clocks */
b37a4224	123	static int exynos_audss_clk_probe(struct platform_device *pdev)
1241ef94	124	{
547f3350 AB	125	const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
	126	const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
	127	const char *sclk_pcm_p = "sclk_pcm0";
	128	struct clk pll_ref, pll_in, cdclk, sclk_audio, *sclk_pcm_in;
7c3ca061	129	const struct exynos_audss_clk_drvdata *variant;
5b2c3da1	130	struct clk_hw **clk_table;
232d7e47	131	struct device *dev = &pdev->dev;
7c3ca061	132	int i, ret = 0;
3538a2cf	133
7c3ca061 SN	134	variant = of_device_get_match_data(&pdev->dev);
7c3ca061 SN	135	if (!variant)
3538a2cf	136	return -EINVAL;
b37a4224	137
c5c1a0ac	138	reg_base = devm_platform_ioremap_resource(pdev, 0);
073f698d	139	if (IS_ERR(reg_base))
b37a4224	140	return PTR_ERR(reg_base);
7c3ca061	141
f1e9203e	142	epll = ERR_PTR(-ENODEV);
1241ef94	143
232d7e47	144	clk_data = devm_kzalloc(dev,
0ed2dd03 KC	145	struct_size(clk_data, hws,
0ed2dd03 KC	146	EXYNOS_AUDSS_MAX_CLKS),
1241ef94	147	GFP_KERNEL);
5b2c3da1	148	if (!clk_data)
b37a4224	149	return -ENOMEM;
1241ef94	150
5b2c3da1 MS	151	clk_data->num = variant->num_clks;
5b2c3da1 MS	152	clk_table = clk_data->hws;
1241ef94	153
232d7e47 MS	154	pll_ref = devm_clk_get(dev, "pll_ref");
232d7e47 MS	155	pll_in = devm_clk_get(dev, "pll_in");
547f3350 AB	156	if (!IS_ERR(pll_ref))
547f3350 AB	157	mout_audss_p[0] = __clk_get_name(pll_ref);
f1e9203e	158	if (!IS_ERR(pll_in)) {
547f3350	159	mout_audss_p[1] = __clk_get_name(pll_in);
f1e9203e	160
7c3ca061	161	if (variant->enable_epll) {
f1e9203e KK	162	epll = pll_in;
	163
	164	ret = clk_prepare_enable(epll);
	165	if (ret) {
232d7e47	166	dev_err(dev,
c17a6163	167	"failed to prepare the epll clock\n");
f1e9203e KK	168	return ret;
	169	}
	170	}
	171	}
ae432a9b MS	172
	173	/*
	174	* Enable runtime PM here to allow the clock core using runtime PM
	175	* for the registered clocks. Additionally, we increase the runtime
	176	* PM usage count before registering the clocks, to prevent the
	177	* clock core from runtime suspending the device.
	178	*/
	179	pm_runtime_get_noresume(dev);
	180	pm_runtime_set_active(dev);
	181	pm_runtime_enable(dev);
	182
	183	clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss",
819c1de3	184	mout_audss_p, ARRAY_SIZE(mout_audss_p),
7df45a53	185	CLK_SET_RATE_NO_REPARENT \| CLK_SET_RATE_PARENT,
1241ef94 PV	186	reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
1241ef94 PV	187
232d7e47 MS	188	cdclk = devm_clk_get(dev, "cdclk");
232d7e47 MS	189	sclk_audio = devm_clk_get(dev, "sclk_audio");
547f3350 AB	190	if (!IS_ERR(cdclk))
	191	mout_i2s_p[1] = __clk_get_name(cdclk);
	192	if (!IS_ERR(sclk_audio))
	193	mout_i2s_p[2] = __clk_get_name(sclk_audio);
ae432a9b	194	clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s",
819c1de3 JH	195	mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
819c1de3 JH	196	CLK_SET_RATE_NO_REPARENT,
1241ef94 PV	197	reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
1241ef94 PV	198
ae432a9b	199	clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp",
7df45a53 SN	200	"mout_audss", CLK_SET_RATE_PARENT,
7df45a53 SN	201	reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
1241ef94	202
ae432a9b	203	clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev,
7df45a53	204	"dout_aud_bus", "dout_srp", CLK_SET_RATE_PARENT,
1241ef94 PV	205	reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
1241ef94 PV	206
ae432a9b	207	clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s",
1241ef94 PV	208	"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
	209	&lock);
	210
ae432a9b	211	clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk",
1241ef94 PV	212	"dout_srp", CLK_SET_RATE_PARENT,
	213	reg_base + ASS_CLK_GATE, 0, 0, &lock);
	214
ae432a9b	215	clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus",
1241ef94 PV	216	"dout_aud_bus", CLK_SET_RATE_PARENT,
	217	reg_base + ASS_CLK_GATE, 2, 0, &lock);
	218
ae432a9b	219	clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s",
1241ef94 PV	220	"dout_i2s", CLK_SET_RATE_PARENT,
	221	reg_base + ASS_CLK_GATE, 3, 0, &lock);
	222
ae432a9b	223	clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(dev, "pcm_bus",
1241ef94 PV	224	"sclk_pcm", CLK_SET_RATE_PARENT,
	225	reg_base + ASS_CLK_GATE, 4, 0, &lock);
	226
232d7e47	227	sclk_pcm_in = devm_clk_get(dev, "sclk_pcm_in");
547f3350 AB	228	if (!IS_ERR(sclk_pcm_in))
547f3350 AB	229	sclk_pcm_p = __clk_get_name(sclk_pcm_in);
ae432a9b	230	clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(dev, "sclk_pcm",
547f3350	231	sclk_pcm_p, CLK_SET_RATE_PARENT,
1241ef94 PV	232	reg_base + ASS_CLK_GATE, 5, 0, &lock);
1241ef94 PV	233
7c3ca061	234	if (variant->has_adma_clk) {
ae432a9b	235	clk_table[EXYNOS_ADMA] = clk_hw_register_gate(dev, "adma",
3538a2cf AB	236	"dout_srp", CLK_SET_RATE_PARENT,
	237	reg_base + ASS_CLK_GATE, 9, 0, &lock);
	238	}
	239
5b2c3da1	240	for (i = 0; i < clk_data->num; i++) {
b37a4224	241	if (IS_ERR(clk_table[i])) {
232d7e47	242	dev_err(dev, "failed to register clock %d\n", i);
b37a4224 AB	243	ret = PTR_ERR(clk_table[i]);
	244	goto unregister;
	245	}
	246	}
	247
232d7e47	248	ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
5b2c3da1	249	clk_data);
b37a4224	250	if (ret) {
232d7e47	251	dev_err(dev, "failed to add clock provider\n");
b37a4224 AB	252	goto unregister;
	253	}
	254
ae432a9b MS	255	pm_runtime_put_sync(dev);
ae432a9b MS	256
b37a4224 AB	257	return 0;
	258
	259	unregister:
27c76c43	260	exynos_audss_clk_teardown();
ae432a9b MS	261	pm_runtime_put_sync(dev);
ae432a9b MS	262	pm_runtime_disable(dev);
b37a4224	263
f1e9203e KK	264	if (!IS_ERR(epll))
	265	clk_disable_unprepare(epll);
	266
b37a4224 AB	267	return ret;
	268	}
	269
e853fb18	270	static void exynos_audss_clk_remove(struct platform_device *pdev)
b37a4224	271	{
b37a4224 AB	272	of_clk_del_provider(pdev->dev.of_node);
b37a4224 AB	273
27c76c43	274	exynos_audss_clk_teardown();
ae432a9b	275	pm_runtime_disable(&pdev->dev);
b37a4224	276
f1e9203e KK	277	if (!IS_ERR(epll))
f1e9203e KK	278	clk_disable_unprepare(epll);
1241ef94	279	}
b37a4224	280
a5b16dfa	281	static const struct dev_pm_ops exynos_audss_clk_pm_ops = {
ae432a9b MS	282	SET_RUNTIME_PM_OPS(exynos_audss_clk_suspend, exynos_audss_clk_resume,
	283	NULL)
	284	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
	285	pm_runtime_force_resume)
a5b16dfa MS	286	};
a5b16dfa MS	287
b37a4224 AB	288	static struct platform_driver exynos_audss_clk_driver = {
	289	.driver = {
	290	.name = "exynos-audss-clk",
b37a4224	291	.of_match_table = exynos_audss_clk_of_match,
a5b16dfa	292	.pm = &exynos_audss_clk_pm_ops,
b37a4224 AB	293	},
b37a4224 AB	294	.probe = exynos_audss_clk_probe,
f00b45db	295	.remove = exynos_audss_clk_remove,
b37a4224 AB	296	};
b37a4224 AB	297
4d252fd5	298	module_platform_driver(exynos_audss_clk_driver);
b37a4224 AB	299
	300	MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
	301	MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
	302	MODULE_LICENSE("GPL v2");
	303	MODULE_ALIAS("platform:exynos-audss-clk");