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a245fecb HS |
1 | /* |
2 | * Copyright (c) 2014 MundoReader S.L. | |
3 | * Author: Heiko Stuebner <heiko@sntech.de> | |
4 | * | |
9c4d6e55 XZ |
5 | * Copyright (c) 2015 Rockchip Electronics Co. Ltd. |
6 | * Author: Xing Zheng <zhengxing@rock-chips.com> | |
7 | * | |
a245fecb HS |
8 | * based on |
9 | * | |
10 | * samsung/clk.h | |
11 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
12 | * Copyright (c) 2013 Linaro Ltd. | |
13 | * Author: Thomas Abraham <thomas.ab@samsung.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | */ | |
25 | ||
26 | #ifndef CLK_ROCKCHIP_CLK_H | |
27 | #define CLK_ROCKCHIP_CLK_H | |
28 | ||
29 | #include <linux/io.h> | |
f684ff8b SB |
30 | |
31 | struct clk; | |
a245fecb HS |
32 | |
33 | #define HIWORD_UPDATE(val, mask, shift) \ | |
34 | ((val) << (shift) | (mask) << ((shift) + 16)) | |
35 | ||
307a2e9a | 36 | /* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */ |
2d7884a7 | 37 | #define RK2928_PLL_CON(x) ((x) * 0x4) |
a245fecb | 38 | #define RK2928_MODE_CON 0x40 |
2d7884a7 HS |
39 | #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) |
40 | #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0) | |
a245fecb HS |
41 | #define RK2928_GLB_SRST_FST 0x100 |
42 | #define RK2928_GLB_SRST_SND 0x104 | |
2d7884a7 | 43 | #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110) |
a245fecb HS |
44 | #define RK2928_MISC_CON 0x134 |
45 | ||
5190c08b XZ |
46 | #define RK3036_SDMMC_CON0 0x144 |
47 | #define RK3036_SDMMC_CON1 0x148 | |
48 | #define RK3036_SDIO_CON0 0x14c | |
49 | #define RK3036_SDIO_CON1 0x150 | |
50 | #define RK3036_EMMC_CON0 0x154 | |
51 | #define RK3036_EMMC_CON1 0x158 | |
52 | ||
307a2e9a JC |
53 | #define RK3228_GLB_SRST_FST 0x1f0 |
54 | #define RK3228_GLB_SRST_SND 0x1f4 | |
55 | #define RK3228_SDMMC_CON0 0x1c0 | |
56 | #define RK3228_SDMMC_CON1 0x1c4 | |
57 | #define RK3228_SDIO_CON0 0x1c8 | |
58 | #define RK3228_SDIO_CON1 0x1cc | |
59 | #define RK3228_EMMC_CON0 0x1d8 | |
60 | #define RK3228_EMMC_CON1 0x1dc | |
61 | ||
b9e4ba54 HS |
62 | #define RK3288_PLL_CON(x) RK2928_PLL_CON(x) |
63 | #define RK3288_MODE_CON 0x50 | |
2d7884a7 HS |
64 | #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60) |
65 | #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160) | |
b9e4ba54 HS |
66 | #define RK3288_GLB_SRST_FST 0x1b0 |
67 | #define RK3288_GLB_SRST_SND 0x1b4 | |
2d7884a7 | 68 | #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8) |
b9e4ba54 | 69 | #define RK3288_MISC_CON 0x1e8 |
89bf26cb AS |
70 | #define RK3288_SDMMC_CON0 0x200 |
71 | #define RK3288_SDMMC_CON1 0x204 | |
72 | #define RK3288_SDIO0_CON0 0x208 | |
73 | #define RK3288_SDIO0_CON1 0x20c | |
74 | #define RK3288_SDIO1_CON0 0x210 | |
75 | #define RK3288_SDIO1_CON1 0x214 | |
76 | #define RK3288_EMMC_CON0 0x218 | |
77 | #define RK3288_EMMC_CON1 0x21c | |
b9e4ba54 | 78 | |
3536c97a HS |
79 | #define RK3368_PLL_CON(x) RK2928_PLL_CON(x) |
80 | #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100) | |
81 | #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200) | |
82 | #define RK3368_GLB_SRST_FST 0x280 | |
83 | #define RK3368_GLB_SRST_SND 0x284 | |
84 | #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300) | |
85 | #define RK3368_MISC_CON 0x380 | |
86 | #define RK3368_SDMMC_CON0 0x400 | |
87 | #define RK3368_SDMMC_CON1 0x404 | |
88 | #define RK3368_SDIO0_CON0 0x408 | |
89 | #define RK3368_SDIO0_CON1 0x40c | |
90 | #define RK3368_SDIO1_CON0 0x410 | |
91 | #define RK3368_SDIO1_CON1 0x414 | |
92 | #define RK3368_EMMC_CON0 0x418 | |
93 | #define RK3368_EMMC_CON1 0x41c | |
94 | ||
90c59025 | 95 | enum rockchip_pll_type { |
9c4d6e55 | 96 | pll_rk3036, |
90c59025 HS |
97 | pll_rk3066, |
98 | }; | |
99 | ||
9c4d6e55 XZ |
100 | #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ |
101 | _postdiv2, _dsmpd, _frac) \ | |
102 | { \ | |
103 | .rate = _rate##U, \ | |
104 | .fbdiv = _fbdiv, \ | |
105 | .postdiv1 = _postdiv1, \ | |
106 | .refdiv = _refdiv, \ | |
107 | .postdiv2 = _postdiv2, \ | |
108 | .dsmpd = _dsmpd, \ | |
109 | .frac = _frac, \ | |
110 | } | |
111 | ||
90c59025 HS |
112 | #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \ |
113 | { \ | |
114 | .rate = _rate##U, \ | |
115 | .nr = _nr, \ | |
116 | .nf = _nf, \ | |
117 | .no = _no, \ | |
2bbfe001 | 118 | .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \ |
90c59025 HS |
119 | } |
120 | ||
2bbfe001 | 121 | #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \ |
49ed9ee4 KY |
122 | { \ |
123 | .rate = _rate##U, \ | |
124 | .nr = _nr, \ | |
125 | .nf = _nf, \ | |
126 | .no = _no, \ | |
2bbfe001 | 127 | .nb = _nb, \ |
49ed9ee4 KY |
128 | } |
129 | ||
90c59025 HS |
130 | struct rockchip_pll_rate_table { |
131 | unsigned long rate; | |
132 | unsigned int nr; | |
133 | unsigned int nf; | |
134 | unsigned int no; | |
2bbfe001 | 135 | unsigned int nb; |
9c4d6e55 XZ |
136 | /* for RK3036 */ |
137 | unsigned int fbdiv; | |
138 | unsigned int postdiv1; | |
139 | unsigned int refdiv; | |
140 | unsigned int postdiv2; | |
141 | unsigned int dsmpd; | |
142 | unsigned int frac; | |
90c59025 HS |
143 | }; |
144 | ||
145 | /** | |
146 | * struct rockchip_pll_clock: information about pll clock | |
147 | * @id: platform specific id of the clock. | |
148 | * @name: name of this pll clock. | |
149 | * @parent_name: name of the parent clock. | |
150 | * @flags: optional flags for basic clock. | |
151 | * @con_offset: offset of the register for configuring the PLL. | |
152 | * @mode_offset: offset of the register for configuring the PLL-mode. | |
153 | * @mode_shift: offset inside the mode-register for the mode of this pll. | |
154 | * @lock_shift: offset inside the lock register for the lock status. | |
155 | * @type: Type of PLL to be registered. | |
4f8a7c54 | 156 | * @pll_flags: hardware-specific flags |
90c59025 | 157 | * @rate_table: Table of usable pll rates |
0bb66d3b HS |
158 | * |
159 | * Flags: | |
160 | * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the | |
161 | * rate_table parameters and ajust them if necessary. | |
90c59025 HS |
162 | */ |
163 | struct rockchip_pll_clock { | |
164 | unsigned int id; | |
165 | const char *name; | |
4a1caed3 | 166 | const char *const *parent_names; |
90c59025 HS |
167 | u8 num_parents; |
168 | unsigned long flags; | |
169 | int con_offset; | |
170 | int mode_offset; | |
171 | int mode_shift; | |
172 | int lock_shift; | |
173 | enum rockchip_pll_type type; | |
4f8a7c54 | 174 | u8 pll_flags; |
90c59025 HS |
175 | struct rockchip_pll_rate_table *rate_table; |
176 | }; | |
177 | ||
0bb66d3b HS |
178 | #define ROCKCHIP_PLL_SYNC_RATE BIT(0) |
179 | ||
90c59025 | 180 | #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ |
4f8a7c54 | 181 | _lshift, _pflags, _rtable) \ |
90c59025 HS |
182 | { \ |
183 | .id = _id, \ | |
184 | .type = _type, \ | |
185 | .name = _name, \ | |
186 | .parent_names = _pnames, \ | |
187 | .num_parents = ARRAY_SIZE(_pnames), \ | |
188 | .flags = CLK_GET_RATE_NOCACHE | _flags, \ | |
189 | .con_offset = _con, \ | |
190 | .mode_offset = _mode, \ | |
191 | .mode_shift = _mshift, \ | |
192 | .lock_shift = _lshift, \ | |
4f8a7c54 | 193 | .pll_flags = _pflags, \ |
90c59025 HS |
194 | .rate_table = _rtable, \ |
195 | } | |
196 | ||
197 | struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, | |
4a1caed3 UKK |
198 | const char *name, const char *const *parent_names, |
199 | u8 num_parents, void __iomem *base, int con_offset, | |
200 | int grf_lock_offset, int lock_shift, int reg_mode, | |
201 | int mode_shift, struct rockchip_pll_rate_table *rate_table, | |
4f8a7c54 | 202 | u8 clk_pll_flags, spinlock_t *lock); |
90c59025 | 203 | |
f6fba5f6 HS |
204 | struct rockchip_cpuclk_clksel { |
205 | int reg; | |
206 | u32 val; | |
207 | }; | |
208 | ||
209 | #define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2 | |
210 | struct rockchip_cpuclk_rate_table { | |
211 | unsigned long prate; | |
212 | struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; | |
213 | }; | |
214 | ||
215 | /** | |
216 | * struct rockchip_cpuclk_reg_data: describes register offsets and masks of the cpuclock | |
217 | * @core_reg: register offset of the core settings register | |
218 | * @div_core_shift: core divider offset used to divide the pll value | |
219 | * @div_core_mask: core divider mask | |
220 | * @mux_core_shift: offset of the core multiplexer | |
221 | */ | |
222 | struct rockchip_cpuclk_reg_data { | |
223 | int core_reg; | |
224 | u8 div_core_shift; | |
225 | u32 div_core_mask; | |
226 | int mux_core_reg; | |
227 | u8 mux_core_shift; | |
228 | }; | |
229 | ||
230 | struct clk *rockchip_clk_register_cpuclk(const char *name, | |
4a1caed3 | 231 | const char *const *parent_names, u8 num_parents, |
f6fba5f6 HS |
232 | const struct rockchip_cpuclk_reg_data *reg_data, |
233 | const struct rockchip_cpuclk_rate_table *rates, | |
234 | int nrates, void __iomem *reg_base, spinlock_t *lock); | |
235 | ||
89bf26cb | 236 | struct clk *rockchip_clk_register_mmc(const char *name, |
4a1caed3 | 237 | const char *const *parent_names, u8 num_parents, |
89bf26cb AS |
238 | void __iomem *reg, int shift); |
239 | ||
8a76f443 HS |
240 | #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0) |
241 | ||
242 | struct clk *rockchip_clk_register_inverter(const char *name, | |
243 | const char *const *parent_names, u8 num_parents, | |
244 | void __iomem *reg, int shift, int flags, | |
245 | spinlock_t *lock); | |
246 | ||
4a1caed3 | 247 | #define PNAME(x) static const char *const x[] __initconst |
a245fecb HS |
248 | |
249 | enum rockchip_clk_branch_type { | |
250 | branch_composite, | |
251 | branch_mux, | |
252 | branch_divider, | |
253 | branch_fraction_divider, | |
254 | branch_gate, | |
89bf26cb | 255 | branch_mmc, |
8a76f443 | 256 | branch_inverter, |
a245fecb HS |
257 | }; |
258 | ||
259 | struct rockchip_clk_branch { | |
260 | unsigned int id; | |
261 | enum rockchip_clk_branch_type branch_type; | |
262 | const char *name; | |
4a1caed3 | 263 | const char *const *parent_names; |
a245fecb HS |
264 | u8 num_parents; |
265 | unsigned long flags; | |
266 | int muxdiv_offset; | |
267 | u8 mux_shift; | |
268 | u8 mux_width; | |
269 | u8 mux_flags; | |
270 | u8 div_shift; | |
271 | u8 div_width; | |
272 | u8 div_flags; | |
273 | struct clk_div_table *div_table; | |
274 | int gate_offset; | |
275 | u8 gate_shift; | |
276 | u8 gate_flags; | |
8ca1ca8f | 277 | struct rockchip_clk_branch *child; |
a245fecb HS |
278 | }; |
279 | ||
280 | #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\ | |
281 | df, go, gs, gf) \ | |
282 | { \ | |
283 | .id = _id, \ | |
284 | .branch_type = branch_composite, \ | |
285 | .name = cname, \ | |
286 | .parent_names = pnames, \ | |
287 | .num_parents = ARRAY_SIZE(pnames), \ | |
288 | .flags = f, \ | |
289 | .muxdiv_offset = mo, \ | |
290 | .mux_shift = ms, \ | |
291 | .mux_width = mw, \ | |
292 | .mux_flags = mf, \ | |
293 | .div_shift = ds, \ | |
294 | .div_width = dw, \ | |
295 | .div_flags = df, \ | |
296 | .gate_offset = go, \ | |
297 | .gate_shift = gs, \ | |
298 | .gate_flags = gf, \ | |
299 | } | |
300 | ||
301 | #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \ | |
302 | go, gs, gf) \ | |
303 | { \ | |
304 | .id = _id, \ | |
305 | .branch_type = branch_composite, \ | |
306 | .name = cname, \ | |
307 | .parent_names = (const char *[]){ pname }, \ | |
308 | .num_parents = 1, \ | |
309 | .flags = f, \ | |
310 | .muxdiv_offset = mo, \ | |
311 | .div_shift = ds, \ | |
312 | .div_width = dw, \ | |
313 | .div_flags = df, \ | |
314 | .gate_offset = go, \ | |
315 | .gate_shift = gs, \ | |
316 | .gate_flags = gf, \ | |
317 | } | |
318 | ||
319 | #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\ | |
320 | df, dt, go, gs, gf) \ | |
321 | { \ | |
322 | .id = _id, \ | |
323 | .branch_type = branch_composite, \ | |
324 | .name = cname, \ | |
325 | .parent_names = (const char *[]){ pname }, \ | |
326 | .num_parents = 1, \ | |
327 | .flags = f, \ | |
328 | .muxdiv_offset = mo, \ | |
329 | .div_shift = ds, \ | |
330 | .div_width = dw, \ | |
331 | .div_flags = df, \ | |
332 | .div_table = dt, \ | |
333 | .gate_offset = go, \ | |
334 | .gate_shift = gs, \ | |
335 | .gate_flags = gf, \ | |
336 | } | |
337 | ||
338 | #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \ | |
339 | go, gs, gf) \ | |
340 | { \ | |
341 | .id = _id, \ | |
342 | .branch_type = branch_composite, \ | |
343 | .name = cname, \ | |
344 | .parent_names = pnames, \ | |
345 | .num_parents = ARRAY_SIZE(pnames), \ | |
346 | .flags = f, \ | |
347 | .muxdiv_offset = mo, \ | |
348 | .mux_shift = ms, \ | |
349 | .mux_width = mw, \ | |
350 | .mux_flags = mf, \ | |
351 | .gate_offset = go, \ | |
352 | .gate_shift = gs, \ | |
353 | .gate_flags = gf, \ | |
354 | } | |
355 | ||
356 | #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \ | |
357 | ds, dw, df) \ | |
358 | { \ | |
359 | .id = _id, \ | |
360 | .branch_type = branch_composite, \ | |
361 | .name = cname, \ | |
362 | .parent_names = pnames, \ | |
363 | .num_parents = ARRAY_SIZE(pnames), \ | |
364 | .flags = f, \ | |
365 | .muxdiv_offset = mo, \ | |
366 | .mux_shift = ms, \ | |
367 | .mux_width = mw, \ | |
368 | .mux_flags = mf, \ | |
369 | .div_shift = ds, \ | |
370 | .div_width = dw, \ | |
371 | .div_flags = df, \ | |
372 | .gate_offset = -1, \ | |
373 | } | |
374 | ||
6f085072 HS |
375 | #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \ |
376 | mw, mf, ds, dw, df, dt) \ | |
377 | { \ | |
378 | .id = _id, \ | |
379 | .branch_type = branch_composite, \ | |
380 | .name = cname, \ | |
381 | .parent_names = pnames, \ | |
382 | .num_parents = ARRAY_SIZE(pnames), \ | |
383 | .flags = f, \ | |
384 | .muxdiv_offset = mo, \ | |
385 | .mux_shift = ms, \ | |
386 | .mux_width = mw, \ | |
387 | .mux_flags = mf, \ | |
388 | .div_shift = ds, \ | |
389 | .div_width = dw, \ | |
390 | .div_flags = df, \ | |
391 | .div_table = dt, \ | |
392 | .gate_offset = -1, \ | |
393 | } | |
394 | ||
a245fecb HS |
395 | #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\ |
396 | { \ | |
397 | .id = _id, \ | |
398 | .branch_type = branch_fraction_divider, \ | |
399 | .name = cname, \ | |
400 | .parent_names = (const char *[]){ pname }, \ | |
401 | .num_parents = 1, \ | |
402 | .flags = f, \ | |
403 | .muxdiv_offset = mo, \ | |
404 | .div_shift = 16, \ | |
405 | .div_width = 16, \ | |
406 | .div_flags = df, \ | |
407 | .gate_offset = go, \ | |
408 | .gate_shift = gs, \ | |
409 | .gate_flags = gf, \ | |
410 | } | |
411 | ||
8ca1ca8f HS |
412 | #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \ |
413 | { \ | |
414 | .id = _id, \ | |
415 | .branch_type = branch_fraction_divider, \ | |
416 | .name = cname, \ | |
417 | .parent_names = (const char *[]){ pname }, \ | |
418 | .num_parents = 1, \ | |
419 | .flags = f, \ | |
420 | .muxdiv_offset = mo, \ | |
421 | .div_shift = 16, \ | |
422 | .div_width = 16, \ | |
423 | .div_flags = df, \ | |
424 | .gate_offset = go, \ | |
425 | .gate_shift = gs, \ | |
426 | .gate_flags = gf, \ | |
5b738403 | 427 | .child = ch, \ |
8ca1ca8f HS |
428 | } |
429 | ||
a245fecb HS |
430 | #define MUX(_id, cname, pnames, f, o, s, w, mf) \ |
431 | { \ | |
432 | .id = _id, \ | |
433 | .branch_type = branch_mux, \ | |
434 | .name = cname, \ | |
435 | .parent_names = pnames, \ | |
436 | .num_parents = ARRAY_SIZE(pnames), \ | |
437 | .flags = f, \ | |
438 | .muxdiv_offset = o, \ | |
439 | .mux_shift = s, \ | |
440 | .mux_width = w, \ | |
441 | .mux_flags = mf, \ | |
442 | .gate_offset = -1, \ | |
443 | } | |
444 | ||
445 | #define DIV(_id, cname, pname, f, o, s, w, df) \ | |
446 | { \ | |
447 | .id = _id, \ | |
448 | .branch_type = branch_divider, \ | |
449 | .name = cname, \ | |
450 | .parent_names = (const char *[]){ pname }, \ | |
451 | .num_parents = 1, \ | |
452 | .flags = f, \ | |
453 | .muxdiv_offset = o, \ | |
454 | .div_shift = s, \ | |
455 | .div_width = w, \ | |
456 | .div_flags = df, \ | |
457 | .gate_offset = -1, \ | |
458 | } | |
459 | ||
460 | #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \ | |
461 | { \ | |
462 | .id = _id, \ | |
463 | .branch_type = branch_divider, \ | |
464 | .name = cname, \ | |
465 | .parent_names = (const char *[]){ pname }, \ | |
466 | .num_parents = 1, \ | |
467 | .flags = f, \ | |
468 | .muxdiv_offset = o, \ | |
469 | .div_shift = s, \ | |
470 | .div_width = w, \ | |
471 | .div_flags = df, \ | |
472 | .div_table = dt, \ | |
473 | } | |
474 | ||
475 | #define GATE(_id, cname, pname, f, o, b, gf) \ | |
476 | { \ | |
477 | .id = _id, \ | |
478 | .branch_type = branch_gate, \ | |
479 | .name = cname, \ | |
480 | .parent_names = (const char *[]){ pname }, \ | |
481 | .num_parents = 1, \ | |
482 | .flags = f, \ | |
483 | .gate_offset = o, \ | |
484 | .gate_shift = b, \ | |
485 | .gate_flags = gf, \ | |
486 | } | |
487 | ||
89bf26cb AS |
488 | #define MMC(_id, cname, pname, offset, shift) \ |
489 | { \ | |
490 | .id = _id, \ | |
491 | .branch_type = branch_mmc, \ | |
492 | .name = cname, \ | |
493 | .parent_names = (const char *[]){ pname }, \ | |
494 | .num_parents = 1, \ | |
495 | .muxdiv_offset = offset, \ | |
496 | .div_shift = shift, \ | |
497 | } | |
a245fecb | 498 | |
8a76f443 HS |
499 | #define INVERTER(_id, cname, pname, io, is, if) \ |
500 | { \ | |
501 | .id = _id, \ | |
502 | .branch_type = branch_inverter, \ | |
503 | .name = cname, \ | |
504 | .parent_names = (const char *[]){ pname }, \ | |
505 | .num_parents = 1, \ | |
506 | .muxdiv_offset = io, \ | |
507 | .div_shift = is, \ | |
508 | .div_flags = if, \ | |
509 | } | |
510 | ||
a245fecb HS |
511 | void rockchip_clk_init(struct device_node *np, void __iomem *base, |
512 | unsigned long nr_clks); | |
90c59025 | 513 | struct regmap *rockchip_clk_get_grf(void); |
a245fecb HS |
514 | void rockchip_clk_add_lookup(struct clk *clk, unsigned int id); |
515 | void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list, | |
516 | unsigned int nr_clk); | |
90c59025 HS |
517 | void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list, |
518 | unsigned int nr_pll, int grf_lock_offset); | |
f6fba5f6 | 519 | void rockchip_clk_register_armclk(unsigned int lookup_id, const char *name, |
4a1caed3 | 520 | const char *const *parent_names, u8 num_parents, |
f6fba5f6 HS |
521 | const struct rockchip_cpuclk_reg_data *reg_data, |
522 | const struct rockchip_cpuclk_rate_table *rates, | |
523 | int nrates); | |
692d8328 | 524 | void rockchip_clk_protect_critical(const char *const clocks[], int nclocks); |
dfff24bd | 525 | void rockchip_register_restart_notifier(unsigned int reg, void (*cb)(void)); |
a245fecb | 526 | |
85fa0c7f HS |
527 | #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0) |
528 | ||
529 | #ifdef CONFIG_RESET_CONTROLLER | |
530 | void rockchip_register_softrst(struct device_node *np, | |
531 | unsigned int num_regs, | |
532 | void __iomem *base, u8 flags); | |
533 | #else | |
534 | static inline void rockchip_register_softrst(struct device_node *np, | |
535 | unsigned int num_regs, | |
536 | void __iomem *base, u8 flags) | |
537 | { | |
538 | } | |
539 | #endif | |
540 | ||
a245fecb | 541 | #endif |