Commit | Line | Data |
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a245fecb HS |
1 | /* |
2 | * Copyright (c) 2014 MundoReader S.L. | |
3 | * Author: Heiko Stuebner <heiko@sntech.de> | |
4 | * | |
ef1d9fee XZ |
5 | * Copyright (c) 2016 Rockchip Electronics Co. Ltd. |
6 | * Author: Xing Zheng <zhengxing@rock-chips.com> | |
7 | * | |
a245fecb HS |
8 | * based on |
9 | * | |
10 | * samsung/clk.c | |
11 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
12 | * Copyright (c) 2013 Linaro Ltd. | |
13 | * Author: Thomas Abraham <thomas.ab@samsung.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | */ | |
25 | ||
26 | #include <linux/slab.h> | |
27 | #include <linux/clk.h> | |
28 | #include <linux/clk-provider.h> | |
62e59c4e | 29 | #include <linux/io.h> |
90c59025 HS |
30 | #include <linux/mfd/syscon.h> |
31 | #include <linux/regmap.h> | |
6f1294b5 | 32 | #include <linux/reboot.h> |
5d890c2d | 33 | #include <linux/rational.h> |
a245fecb HS |
34 | #include "clk.h" |
35 | ||
36 | /** | |
37 | * Register a clock branch. | |
38 | * Most clock branches have a form like | |
39 | * | |
40 | * src1 --|--\ | |
41 | * |M |--[GATE]-[DIV]- | |
42 | * src2 --|--/ | |
43 | * | |
44 | * sometimes without one of those components. | |
45 | */ | |
1a4b1819 | 46 | static struct clk *rockchip_clk_register_branch(const char *name, |
03ae1747 HS |
47 | const char *const *parent_names, u8 num_parents, |
48 | void __iomem *base, | |
a245fecb | 49 | int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, |
1f55660f | 50 | int div_offset, u8 div_shift, u8 div_width, u8 div_flags, |
a245fecb HS |
51 | struct clk_div_table *div_table, int gate_offset, |
52 | u8 gate_shift, u8 gate_flags, unsigned long flags, | |
53 | spinlock_t *lock) | |
54 | { | |
55 | struct clk *clk; | |
56 | struct clk_mux *mux = NULL; | |
57 | struct clk_gate *gate = NULL; | |
58 | struct clk_divider *div = NULL; | |
59 | const struct clk_ops *mux_ops = NULL, *div_ops = NULL, | |
60 | *gate_ops = NULL; | |
fd3cbbfb | 61 | int ret; |
a245fecb HS |
62 | |
63 | if (num_parents > 1) { | |
64 | mux = kzalloc(sizeof(*mux), GFP_KERNEL); | |
65 | if (!mux) | |
66 | return ERR_PTR(-ENOMEM); | |
67 | ||
68 | mux->reg = base + muxdiv_offset; | |
69 | mux->shift = mux_shift; | |
70 | mux->mask = BIT(mux_width) - 1; | |
71 | mux->flags = mux_flags; | |
72 | mux->lock = lock; | |
73 | mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops | |
74 | : &clk_mux_ops; | |
75 | } | |
76 | ||
77 | if (gate_offset >= 0) { | |
78 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); | |
fd3cbbfb SL |
79 | if (!gate) { |
80 | ret = -ENOMEM; | |
2467b674 | 81 | goto err_gate; |
fd3cbbfb | 82 | } |
a245fecb HS |
83 | |
84 | gate->flags = gate_flags; | |
85 | gate->reg = base + gate_offset; | |
86 | gate->bit_idx = gate_shift; | |
87 | gate->lock = lock; | |
88 | gate_ops = &clk_gate_ops; | |
89 | } | |
90 | ||
91 | if (div_width > 0) { | |
92 | div = kzalloc(sizeof(*div), GFP_KERNEL); | |
fd3cbbfb SL |
93 | if (!div) { |
94 | ret = -ENOMEM; | |
2467b674 | 95 | goto err_div; |
fd3cbbfb | 96 | } |
a245fecb HS |
97 | |
98 | div->flags = div_flags; | |
1f55660f FX |
99 | if (div_offset) |
100 | div->reg = base + div_offset; | |
101 | else | |
102 | div->reg = base + muxdiv_offset; | |
a245fecb HS |
103 | div->shift = div_shift; |
104 | div->width = div_width; | |
105 | div->lock = lock; | |
106 | div->table = div_table; | |
50359819 HS |
107 | div_ops = (div_flags & CLK_DIVIDER_READ_ONLY) |
108 | ? &clk_divider_ro_ops | |
109 | : &clk_divider_ops; | |
a245fecb HS |
110 | } |
111 | ||
112 | clk = clk_register_composite(NULL, name, parent_names, num_parents, | |
113 | mux ? &mux->hw : NULL, mux_ops, | |
114 | div ? &div->hw : NULL, div_ops, | |
115 | gate ? &gate->hw : NULL, gate_ops, | |
116 | flags); | |
117 | ||
fd3cbbfb SL |
118 | if (IS_ERR(clk)) { |
119 | ret = PTR_ERR(clk); | |
120 | goto err_composite; | |
121 | } | |
122 | ||
a245fecb | 123 | return clk; |
fd3cbbfb SL |
124 | err_composite: |
125 | kfree(div); | |
2467b674 SL |
126 | err_div: |
127 | kfree(gate); | |
128 | err_gate: | |
129 | kfree(mux); | |
fd3cbbfb | 130 | return ERR_PTR(ret); |
a245fecb HS |
131 | } |
132 | ||
8ca1ca8f HS |
133 | struct rockchip_clk_frac { |
134 | struct notifier_block clk_nb; | |
135 | struct clk_fractional_divider div; | |
136 | struct clk_gate gate; | |
137 | ||
138 | struct clk_mux mux; | |
139 | const struct clk_ops *mux_ops; | |
140 | int mux_frac_idx; | |
141 | ||
142 | bool rate_change_remuxed; | |
143 | int rate_change_idx; | |
144 | }; | |
145 | ||
146 | #define to_rockchip_clk_frac_nb(nb) \ | |
147 | container_of(nb, struct rockchip_clk_frac, clk_nb) | |
148 | ||
149 | static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb, | |
150 | unsigned long event, void *data) | |
151 | { | |
152 | struct clk_notifier_data *ndata = data; | |
153 | struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb); | |
154 | struct clk_mux *frac_mux = &frac->mux; | |
155 | int ret = 0; | |
156 | ||
157 | pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n", | |
158 | __func__, event, ndata->old_rate, ndata->new_rate); | |
159 | if (event == PRE_RATE_CHANGE) { | |
03ae1747 HS |
160 | frac->rate_change_idx = |
161 | frac->mux_ops->get_parent(&frac_mux->hw); | |
8ca1ca8f | 162 | if (frac->rate_change_idx != frac->mux_frac_idx) { |
03ae1747 HS |
163 | frac->mux_ops->set_parent(&frac_mux->hw, |
164 | frac->mux_frac_idx); | |
8ca1ca8f HS |
165 | frac->rate_change_remuxed = 1; |
166 | } | |
167 | } else if (event == POST_RATE_CHANGE) { | |
168 | /* | |
169 | * The POST_RATE_CHANGE notifier runs directly after the | |
170 | * divider clock is set in clk_change_rate, so we'll have | |
171 | * remuxed back to the original parent before clk_change_rate | |
172 | * reaches the mux itself. | |
173 | */ | |
174 | if (frac->rate_change_remuxed) { | |
03ae1747 HS |
175 | frac->mux_ops->set_parent(&frac_mux->hw, |
176 | frac->rate_change_idx); | |
8ca1ca8f HS |
177 | frac->rate_change_remuxed = 0; |
178 | } | |
179 | } | |
180 | ||
181 | return notifier_from_errno(ret); | |
182 | } | |
183 | ||
5d890c2d EZ |
184 | /** |
185 | * fractional divider must set that denominator is 20 times larger than | |
186 | * numerator to generate precise clock frequency. | |
187 | */ | |
1dfcfa72 | 188 | static void rockchip_fractional_approximation(struct clk_hw *hw, |
5d890c2d EZ |
189 | unsigned long rate, unsigned long *parent_rate, |
190 | unsigned long *m, unsigned long *n) | |
191 | { | |
192 | struct clk_fractional_divider *fd = to_clk_fd(hw); | |
193 | unsigned long p_rate, p_parent_rate; | |
194 | struct clk_hw *p_parent; | |
195 | unsigned long scale; | |
196 | ||
197 | p_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); | |
198 | if ((rate * 20 > p_rate) && (p_rate % rate != 0)) { | |
199 | p_parent = clk_hw_get_parent(clk_hw_get_parent(hw)); | |
200 | p_parent_rate = clk_hw_get_rate(p_parent); | |
201 | *parent_rate = p_parent_rate; | |
202 | } | |
203 | ||
204 | /* | |
205 | * Get rate closer to *parent_rate to guarantee there is no overflow | |
206 | * for m and n. In the result it will be the nearest rate left shifted | |
207 | * by (scale - fd->nwidth) bits. | |
208 | */ | |
209 | scale = fls_long(*parent_rate / rate - 1); | |
210 | if (scale > fd->nwidth) | |
211 | rate <<= scale - fd->nwidth; | |
212 | ||
213 | rational_best_approximation(rate, *parent_rate, | |
214 | GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), | |
215 | m, n); | |
216 | } | |
217 | ||
ef1d9fee XZ |
218 | static struct clk *rockchip_clk_register_frac_branch( |
219 | struct rockchip_clk_provider *ctx, const char *name, | |
4a1caed3 UKK |
220 | const char *const *parent_names, u8 num_parents, |
221 | void __iomem *base, int muxdiv_offset, u8 div_flags, | |
b2155a71 | 222 | int gate_offset, u8 gate_shift, u8 gate_flags, |
8ca1ca8f HS |
223 | unsigned long flags, struct rockchip_clk_branch *child, |
224 | spinlock_t *lock) | |
b2155a71 | 225 | { |
8ca1ca8f | 226 | struct rockchip_clk_frac *frac; |
b2155a71 HS |
227 | struct clk *clk; |
228 | struct clk_gate *gate = NULL; | |
229 | struct clk_fractional_divider *div = NULL; | |
230 | const struct clk_ops *div_ops = NULL, *gate_ops = NULL; | |
231 | ||
8ca1ca8f HS |
232 | if (muxdiv_offset < 0) |
233 | return ERR_PTR(-EINVAL); | |
234 | ||
235 | if (child && child->branch_type != branch_mux) { | |
236 | pr_err("%s: fractional child clock for %s can only be a mux\n", | |
237 | __func__, name); | |
238 | return ERR_PTR(-EINVAL); | |
239 | } | |
b2155a71 | 240 | |
8ca1ca8f HS |
241 | frac = kzalloc(sizeof(*frac), GFP_KERNEL); |
242 | if (!frac) | |
243 | return ERR_PTR(-ENOMEM); | |
244 | ||
245 | if (gate_offset >= 0) { | |
246 | gate = &frac->gate; | |
b2155a71 HS |
247 | gate->flags = gate_flags; |
248 | gate->reg = base + gate_offset; | |
249 | gate->bit_idx = gate_shift; | |
250 | gate->lock = lock; | |
251 | gate_ops = &clk_gate_ops; | |
252 | } | |
253 | ||
8ca1ca8f | 254 | div = &frac->div; |
b2155a71 HS |
255 | div->flags = div_flags; |
256 | div->reg = base + muxdiv_offset; | |
257 | div->mshift = 16; | |
5d49a6e1 AS |
258 | div->mwidth = 16; |
259 | div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift; | |
b2155a71 | 260 | div->nshift = 0; |
5d49a6e1 AS |
261 | div->nwidth = 16; |
262 | div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift; | |
b2155a71 | 263 | div->lock = lock; |
5d890c2d | 264 | div->approximation = rockchip_fractional_approximation; |
b2155a71 HS |
265 | div_ops = &clk_fractional_divider_ops; |
266 | ||
267 | clk = clk_register_composite(NULL, name, parent_names, num_parents, | |
268 | NULL, NULL, | |
269 | &div->hw, div_ops, | |
270 | gate ? &gate->hw : NULL, gate_ops, | |
8ca1ca8f HS |
271 | flags | CLK_SET_RATE_UNGATE); |
272 | if (IS_ERR(clk)) { | |
273 | kfree(frac); | |
274 | return clk; | |
275 | } | |
276 | ||
277 | if (child) { | |
278 | struct clk_mux *frac_mux = &frac->mux; | |
279 | struct clk_init_data init; | |
280 | struct clk *mux_clk; | |
a425702f | 281 | int ret; |
8ca1ca8f | 282 | |
a425702f YX |
283 | frac->mux_frac_idx = match_string(child->parent_names, |
284 | child->num_parents, name); | |
8ca1ca8f HS |
285 | frac->mux_ops = &clk_mux_ops; |
286 | frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb; | |
287 | ||
288 | frac_mux->reg = base + child->muxdiv_offset; | |
289 | frac_mux->shift = child->mux_shift; | |
290 | frac_mux->mask = BIT(child->mux_width) - 1; | |
291 | frac_mux->flags = child->mux_flags; | |
292 | frac_mux->lock = lock; | |
293 | frac_mux->hw.init = &init; | |
294 | ||
295 | init.name = child->name; | |
296 | init.flags = child->flags | CLK_SET_RATE_PARENT; | |
297 | init.ops = frac->mux_ops; | |
298 | init.parent_names = child->parent_names; | |
299 | init.num_parents = child->num_parents; | |
300 | ||
301 | mux_clk = clk_register(NULL, &frac_mux->hw); | |
fd3cbbfb SL |
302 | if (IS_ERR(mux_clk)) { |
303 | kfree(frac); | |
8ca1ca8f | 304 | return clk; |
fd3cbbfb | 305 | } |
8ca1ca8f | 306 | |
ef1d9fee | 307 | rockchip_clk_add_lookup(ctx, mux_clk, child->id); |
8ca1ca8f HS |
308 | |
309 | /* notifier on the fraction divider to catch rate changes */ | |
310 | if (frac->mux_frac_idx >= 0) { | |
a425702f YX |
311 | pr_debug("%s: found fractional parent in mux at pos %d\n", |
312 | __func__, frac->mux_frac_idx); | |
8ca1ca8f HS |
313 | ret = clk_notifier_register(clk, &frac->clk_nb); |
314 | if (ret) | |
315 | pr_err("%s: failed to register clock notifier for %s\n", | |
316 | __func__, name); | |
317 | } else { | |
318 | pr_warn("%s: could not find %s as parent of %s, rate changes may not work\n", | |
319 | __func__, name, child->name); | |
320 | } | |
321 | } | |
b2155a71 HS |
322 | |
323 | return clk; | |
324 | } | |
325 | ||
29a30c26 HS |
326 | static struct clk *rockchip_clk_register_factor_branch(const char *name, |
327 | const char *const *parent_names, u8 num_parents, | |
328 | void __iomem *base, unsigned int mult, unsigned int div, | |
329 | int gate_offset, u8 gate_shift, u8 gate_flags, | |
330 | unsigned long flags, spinlock_t *lock) | |
331 | { | |
332 | struct clk *clk; | |
333 | struct clk_gate *gate = NULL; | |
334 | struct clk_fixed_factor *fix = NULL; | |
335 | ||
336 | /* without gate, register a simple factor clock */ | |
337 | if (gate_offset == 0) { | |
338 | return clk_register_fixed_factor(NULL, name, | |
339 | parent_names[0], flags, mult, | |
340 | div); | |
341 | } | |
342 | ||
343 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); | |
344 | if (!gate) | |
345 | return ERR_PTR(-ENOMEM); | |
346 | ||
347 | gate->flags = gate_flags; | |
348 | gate->reg = base + gate_offset; | |
349 | gate->bit_idx = gate_shift; | |
350 | gate->lock = lock; | |
351 | ||
352 | fix = kzalloc(sizeof(*fix), GFP_KERNEL); | |
353 | if (!fix) { | |
354 | kfree(gate); | |
355 | return ERR_PTR(-ENOMEM); | |
356 | } | |
357 | ||
358 | fix->mult = mult; | |
359 | fix->div = div; | |
360 | ||
361 | clk = clk_register_composite(NULL, name, parent_names, num_parents, | |
362 | NULL, NULL, | |
363 | &fix->hw, &clk_fixed_factor_ops, | |
364 | &gate->hw, &clk_gate_ops, flags); | |
365 | if (IS_ERR(clk)) { | |
366 | kfree(fix); | |
367 | kfree(gate); | |
368 | } | |
369 | ||
370 | return clk; | |
371 | } | |
372 | ||
ef1d9fee XZ |
373 | struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np, |
374 | void __iomem *base, unsigned long nr_clks) | |
a245fecb | 375 | { |
ef1d9fee XZ |
376 | struct rockchip_clk_provider *ctx; |
377 | struct clk **clk_table; | |
378 | int i; | |
379 | ||
380 | ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL); | |
03ae1747 | 381 | if (!ctx) |
ef1d9fee | 382 | return ERR_PTR(-ENOMEM); |
a245fecb HS |
383 | |
384 | clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); | |
03ae1747 | 385 | if (!clk_table) |
ef1d9fee | 386 | goto err_free; |
ef1d9fee XZ |
387 | |
388 | for (i = 0; i < nr_clks; ++i) | |
389 | clk_table[i] = ERR_PTR(-ENOENT); | |
a245fecb | 390 | |
ef1d9fee XZ |
391 | ctx->reg_base = base; |
392 | ctx->clk_data.clks = clk_table; | |
393 | ctx->clk_data.clk_num = nr_clks; | |
394 | ctx->cru_node = np; | |
ef1d9fee XZ |
395 | spin_lock_init(&ctx->lock); |
396 | ||
6f339dc2 HS |
397 | ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node, |
398 | "rockchip,grf"); | |
399 | ||
ef1d9fee XZ |
400 | return ctx; |
401 | ||
402 | err_free: | |
403 | kfree(ctx); | |
404 | return ERR_PTR(-ENOMEM); | |
405 | } | |
406 | ||
407 | void __init rockchip_clk_of_add_provider(struct device_node *np, | |
408 | struct rockchip_clk_provider *ctx) | |
409 | { | |
ff1ae209 SL |
410 | if (of_clk_add_provider(np, of_clk_src_onecell_get, |
411 | &ctx->clk_data)) | |
412 | pr_err("%s: could not register clk provider\n", __func__); | |
a245fecb HS |
413 | } |
414 | ||
ef1d9fee XZ |
415 | void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, |
416 | struct clk *clk, unsigned int id) | |
a245fecb | 417 | { |
ef1d9fee XZ |
418 | if (ctx->clk_data.clks && id) |
419 | ctx->clk_data.clks[id] = clk; | |
a245fecb HS |
420 | } |
421 | ||
ef1d9fee XZ |
422 | void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, |
423 | struct rockchip_pll_clock *list, | |
90c59025 HS |
424 | unsigned int nr_pll, int grf_lock_offset) |
425 | { | |
426 | struct clk *clk; | |
427 | int idx; | |
428 | ||
429 | for (idx = 0; idx < nr_pll; idx++, list++) { | |
ef1d9fee | 430 | clk = rockchip_clk_register_pll(ctx, list->type, list->name, |
90c59025 | 431 | list->parent_names, list->num_parents, |
ef1d9fee | 432 | list->con_offset, grf_lock_offset, |
90c59025 | 433 | list->lock_shift, list->mode_offset, |
4f8a7c54 | 434 | list->mode_shift, list->rate_table, |
e6cebc72 | 435 | list->flags, list->pll_flags); |
90c59025 HS |
436 | if (IS_ERR(clk)) { |
437 | pr_err("%s: failed to register clock %s\n", __func__, | |
438 | list->name); | |
439 | continue; | |
440 | } | |
441 | ||
ef1d9fee | 442 | rockchip_clk_add_lookup(ctx, clk, list->id); |
90c59025 HS |
443 | } |
444 | } | |
445 | ||
a245fecb | 446 | void __init rockchip_clk_register_branches( |
ef1d9fee | 447 | struct rockchip_clk_provider *ctx, |
a245fecb HS |
448 | struct rockchip_clk_branch *list, |
449 | unsigned int nr_clk) | |
450 | { | |
451 | struct clk *clk = NULL; | |
452 | unsigned int idx; | |
453 | unsigned long flags; | |
454 | ||
455 | for (idx = 0; idx < nr_clk; idx++, list++) { | |
456 | flags = list->flags; | |
457 | ||
458 | /* catch simple muxes */ | |
459 | switch (list->branch_type) { | |
460 | case branch_mux: | |
461 | clk = clk_register_mux(NULL, list->name, | |
462 | list->parent_names, list->num_parents, | |
ef1d9fee | 463 | flags, ctx->reg_base + list->muxdiv_offset, |
a245fecb | 464 | list->mux_shift, list->mux_width, |
ef1d9fee | 465 | list->mux_flags, &ctx->lock); |
a245fecb | 466 | break; |
cb1d9f6d HS |
467 | case branch_muxgrf: |
468 | clk = rockchip_clk_register_muxgrf(list->name, | |
469 | list->parent_names, list->num_parents, | |
470 | flags, ctx->grf, list->muxdiv_offset, | |
471 | list->mux_shift, list->mux_width, | |
472 | list->mux_flags); | |
473 | break; | |
a245fecb HS |
474 | case branch_divider: |
475 | if (list->div_table) | |
476 | clk = clk_register_divider_table(NULL, | |
477 | list->name, list->parent_names[0], | |
03ae1747 HS |
478 | flags, |
479 | ctx->reg_base + list->muxdiv_offset, | |
a245fecb HS |
480 | list->div_shift, list->div_width, |
481 | list->div_flags, list->div_table, | |
ef1d9fee | 482 | &ctx->lock); |
a245fecb HS |
483 | else |
484 | clk = clk_register_divider(NULL, list->name, | |
485 | list->parent_names[0], flags, | |
ef1d9fee | 486 | ctx->reg_base + list->muxdiv_offset, |
a245fecb | 487 | list->div_shift, list->div_width, |
ef1d9fee | 488 | list->div_flags, &ctx->lock); |
a245fecb HS |
489 | break; |
490 | case branch_fraction_divider: | |
ef1d9fee | 491 | clk = rockchip_clk_register_frac_branch(ctx, list->name, |
b2155a71 | 492 | list->parent_names, list->num_parents, |
03ae1747 HS |
493 | ctx->reg_base, list->muxdiv_offset, |
494 | list->div_flags, | |
b2155a71 | 495 | list->gate_offset, list->gate_shift, |
8ca1ca8f | 496 | list->gate_flags, flags, list->child, |
ef1d9fee | 497 | &ctx->lock); |
a245fecb | 498 | break; |
956060a5 EZ |
499 | case branch_half_divider: |
500 | clk = rockchip_clk_register_halfdiv(list->name, | |
501 | list->parent_names, list->num_parents, | |
502 | ctx->reg_base, list->muxdiv_offset, | |
503 | list->mux_shift, list->mux_width, | |
504 | list->mux_flags, list->div_shift, | |
505 | list->div_width, list->div_flags, | |
506 | list->gate_offset, list->gate_shift, | |
507 | list->gate_flags, flags, &ctx->lock); | |
508 | break; | |
a245fecb HS |
509 | case branch_gate: |
510 | flags |= CLK_SET_RATE_PARENT; | |
511 | ||
a245fecb HS |
512 | clk = clk_register_gate(NULL, list->name, |
513 | list->parent_names[0], flags, | |
ef1d9fee XZ |
514 | ctx->reg_base + list->gate_offset, |
515 | list->gate_shift, list->gate_flags, &ctx->lock); | |
a245fecb HS |
516 | break; |
517 | case branch_composite: | |
a245fecb HS |
518 | clk = rockchip_clk_register_branch(list->name, |
519 | list->parent_names, list->num_parents, | |
03ae1747 HS |
520 | ctx->reg_base, list->muxdiv_offset, |
521 | list->mux_shift, | |
a245fecb | 522 | list->mux_width, list->mux_flags, |
1f55660f | 523 | list->div_offset, list->div_shift, list->div_width, |
a245fecb HS |
524 | list->div_flags, list->div_table, |
525 | list->gate_offset, list->gate_shift, | |
ef1d9fee | 526 | list->gate_flags, flags, &ctx->lock); |
a245fecb | 527 | break; |
89bf26cb AS |
528 | case branch_mmc: |
529 | clk = rockchip_clk_register_mmc( | |
530 | list->name, | |
531 | list->parent_names, list->num_parents, | |
ef1d9fee | 532 | ctx->reg_base + list->muxdiv_offset, |
89bf26cb AS |
533 | list->div_shift |
534 | ); | |
535 | break; | |
8a76f443 HS |
536 | case branch_inverter: |
537 | clk = rockchip_clk_register_inverter( | |
538 | list->name, list->parent_names, | |
539 | list->num_parents, | |
ef1d9fee XZ |
540 | ctx->reg_base + list->muxdiv_offset, |
541 | list->div_shift, list->div_flags, &ctx->lock); | |
8a76f443 | 542 | break; |
29a30c26 HS |
543 | case branch_factor: |
544 | clk = rockchip_clk_register_factor_branch( | |
545 | list->name, list->parent_names, | |
ef1d9fee | 546 | list->num_parents, ctx->reg_base, |
29a30c26 HS |
547 | list->div_shift, list->div_width, |
548 | list->gate_offset, list->gate_shift, | |
ef1d9fee | 549 | list->gate_flags, flags, &ctx->lock); |
29a30c26 | 550 | break; |
a4f182bf LH |
551 | case branch_ddrclk: |
552 | clk = rockchip_clk_register_ddrclk( | |
553 | list->name, list->flags, | |
554 | list->parent_names, list->num_parents, | |
555 | list->muxdiv_offset, list->mux_shift, | |
556 | list->mux_width, list->div_shift, | |
557 | list->div_width, list->div_flags, | |
558 | ctx->reg_base, &ctx->lock); | |
559 | break; | |
a245fecb HS |
560 | } |
561 | ||
562 | /* none of the cases above matched */ | |
563 | if (!clk) { | |
564 | pr_err("%s: unknown clock type %d\n", | |
565 | __func__, list->branch_type); | |
566 | continue; | |
567 | } | |
568 | ||
569 | if (IS_ERR(clk)) { | |
570 | pr_err("%s: failed to register clock %s: %ld\n", | |
571 | __func__, list->name, PTR_ERR(clk)); | |
572 | continue; | |
573 | } | |
574 | ||
ef1d9fee | 575 | rockchip_clk_add_lookup(ctx, clk, list->id); |
a245fecb HS |
576 | } |
577 | } | |
fe94f974 | 578 | |
ef1d9fee XZ |
579 | void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, |
580 | unsigned int lookup_id, | |
4a1caed3 | 581 | const char *name, const char *const *parent_names, |
f6fba5f6 HS |
582 | u8 num_parents, |
583 | const struct rockchip_cpuclk_reg_data *reg_data, | |
584 | const struct rockchip_cpuclk_rate_table *rates, | |
585 | int nrates) | |
586 | { | |
587 | struct clk *clk; | |
588 | ||
589 | clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents, | |
03ae1747 HS |
590 | reg_data, rates, nrates, |
591 | ctx->reg_base, &ctx->lock); | |
f6fba5f6 HS |
592 | if (IS_ERR(clk)) { |
593 | pr_err("%s: failed to register clock %s: %ld\n", | |
594 | __func__, name, PTR_ERR(clk)); | |
595 | return; | |
596 | } | |
597 | ||
ef1d9fee | 598 | rockchip_clk_add_lookup(ctx, clk, lookup_id); |
f6fba5f6 HS |
599 | } |
600 | ||
692d8328 UKK |
601 | void __init rockchip_clk_protect_critical(const char *const clocks[], |
602 | int nclocks) | |
fe94f974 HS |
603 | { |
604 | int i; | |
605 | ||
606 | /* Protect the clocks that needs to stay on */ | |
607 | for (i = 0; i < nclocks; i++) { | |
608 | struct clk *clk = __clk_lookup(clocks[i]); | |
609 | ||
610 | if (clk) | |
611 | clk_prepare_enable(clk); | |
612 | } | |
613 | } | |
6f1294b5 | 614 | |
ef1d9fee | 615 | static void __iomem *rst_base; |
6f1294b5 | 616 | static unsigned int reg_restart; |
dfff24bd | 617 | static void (*cb_restart)(void); |
6f1294b5 HS |
618 | static int rockchip_restart_notify(struct notifier_block *this, |
619 | unsigned long mode, void *cmd) | |
620 | { | |
dfff24bd HS |
621 | if (cb_restart) |
622 | cb_restart(); | |
623 | ||
ef1d9fee | 624 | writel(0xfdb9, rst_base + reg_restart); |
6f1294b5 HS |
625 | return NOTIFY_DONE; |
626 | } | |
627 | ||
628 | static struct notifier_block rockchip_restart_handler = { | |
629 | .notifier_call = rockchip_restart_notify, | |
630 | .priority = 128, | |
631 | }; | |
632 | ||
03ae1747 HS |
633 | void __init |
634 | rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx, | |
635 | unsigned int reg, | |
636 | void (*cb)(void)) | |
6f1294b5 HS |
637 | { |
638 | int ret; | |
639 | ||
ef1d9fee | 640 | rst_base = ctx->reg_base; |
6f1294b5 | 641 | reg_restart = reg; |
dfff24bd | 642 | cb_restart = cb; |
6f1294b5 HS |
643 | ret = register_restart_handler(&rockchip_restart_handler); |
644 | if (ret) | |
645 | pr_err("%s: cannot register restart handler, %d\n", | |
646 | __func__, ret); | |
647 | } |