Commit | Line | Data |
---|---|---|
c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
a245fecb HS |
2 | /* |
3 | * Copyright (c) 2014 MundoReader S.L. | |
4 | * Author: Heiko Stuebner <heiko@sntech.de> | |
5 | * | |
ef1d9fee XZ |
6 | * Copyright (c) 2016 Rockchip Electronics Co. Ltd. |
7 | * Author: Xing Zheng <zhengxing@rock-chips.com> | |
8 | * | |
a245fecb HS |
9 | * based on |
10 | * | |
11 | * samsung/clk.c | |
12 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
13 | * Copyright (c) 2013 Linaro Ltd. | |
14 | * Author: Thomas Abraham <thomas.ab@samsung.com> | |
a245fecb HS |
15 | */ |
16 | ||
17 | #include <linux/slab.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/clk-provider.h> | |
62e59c4e | 20 | #include <linux/io.h> |
90c59025 HS |
21 | #include <linux/mfd/syscon.h> |
22 | #include <linux/regmap.h> | |
6f1294b5 | 23 | #include <linux/reboot.h> |
4e7cf74f AS |
24 | |
25 | #include "../clk-fractional-divider.h" | |
a245fecb HS |
26 | #include "clk.h" |
27 | ||
41517371 | 28 | /* |
a245fecb HS |
29 | * Register a clock branch. |
30 | * Most clock branches have a form like | |
31 | * | |
32 | * src1 --|--\ | |
33 | * |M |--[GATE]-[DIV]- | |
34 | * src2 --|--/ | |
35 | * | |
36 | * sometimes without one of those components. | |
37 | */ | |
1a4b1819 | 38 | static struct clk *rockchip_clk_register_branch(const char *name, |
03ae1747 HS |
39 | const char *const *parent_names, u8 num_parents, |
40 | void __iomem *base, | |
a245fecb | 41 | int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, |
30d8b7d4 | 42 | u32 *mux_table, |
1f55660f | 43 | int div_offset, u8 div_shift, u8 div_width, u8 div_flags, |
a245fecb HS |
44 | struct clk_div_table *div_table, int gate_offset, |
45 | u8 gate_shift, u8 gate_flags, unsigned long flags, | |
46 | spinlock_t *lock) | |
47 | { | |
63207c37 | 48 | struct clk_hw *hw; |
a245fecb HS |
49 | struct clk_mux *mux = NULL; |
50 | struct clk_gate *gate = NULL; | |
51 | struct clk_divider *div = NULL; | |
52 | const struct clk_ops *mux_ops = NULL, *div_ops = NULL, | |
53 | *gate_ops = NULL; | |
fd3cbbfb | 54 | int ret; |
a245fecb HS |
55 | |
56 | if (num_parents > 1) { | |
57 | mux = kzalloc(sizeof(*mux), GFP_KERNEL); | |
58 | if (!mux) | |
59 | return ERR_PTR(-ENOMEM); | |
60 | ||
61 | mux->reg = base + muxdiv_offset; | |
62 | mux->shift = mux_shift; | |
63 | mux->mask = BIT(mux_width) - 1; | |
64 | mux->flags = mux_flags; | |
30d8b7d4 | 65 | mux->table = mux_table; |
a245fecb HS |
66 | mux->lock = lock; |
67 | mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops | |
68 | : &clk_mux_ops; | |
69 | } | |
70 | ||
71 | if (gate_offset >= 0) { | |
72 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); | |
fd3cbbfb SL |
73 | if (!gate) { |
74 | ret = -ENOMEM; | |
2467b674 | 75 | goto err_gate; |
fd3cbbfb | 76 | } |
a245fecb HS |
77 | |
78 | gate->flags = gate_flags; | |
79 | gate->reg = base + gate_offset; | |
80 | gate->bit_idx = gate_shift; | |
81 | gate->lock = lock; | |
82 | gate_ops = &clk_gate_ops; | |
83 | } | |
84 | ||
85 | if (div_width > 0) { | |
86 | div = kzalloc(sizeof(*div), GFP_KERNEL); | |
fd3cbbfb SL |
87 | if (!div) { |
88 | ret = -ENOMEM; | |
2467b674 | 89 | goto err_div; |
fd3cbbfb | 90 | } |
a245fecb HS |
91 | |
92 | div->flags = div_flags; | |
1f55660f FX |
93 | if (div_offset) |
94 | div->reg = base + div_offset; | |
95 | else | |
96 | div->reg = base + muxdiv_offset; | |
a245fecb HS |
97 | div->shift = div_shift; |
98 | div->width = div_width; | |
99 | div->lock = lock; | |
100 | div->table = div_table; | |
50359819 HS |
101 | div_ops = (div_flags & CLK_DIVIDER_READ_ONLY) |
102 | ? &clk_divider_ro_ops | |
103 | : &clk_divider_ops; | |
a245fecb HS |
104 | } |
105 | ||
63207c37 EZ |
106 | hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, |
107 | mux ? &mux->hw : NULL, mux_ops, | |
108 | div ? &div->hw : NULL, div_ops, | |
109 | gate ? &gate->hw : NULL, gate_ops, | |
110 | flags); | |
111 | if (IS_ERR(hw)) { | |
112 | kfree(div); | |
113 | kfree(gate); | |
114 | return ERR_CAST(hw); | |
fd3cbbfb SL |
115 | } |
116 | ||
63207c37 | 117 | return hw->clk; |
2467b674 SL |
118 | err_div: |
119 | kfree(gate); | |
120 | err_gate: | |
121 | kfree(mux); | |
fd3cbbfb | 122 | return ERR_PTR(ret); |
a245fecb HS |
123 | } |
124 | ||
8ca1ca8f HS |
125 | struct rockchip_clk_frac { |
126 | struct notifier_block clk_nb; | |
127 | struct clk_fractional_divider div; | |
128 | struct clk_gate gate; | |
129 | ||
130 | struct clk_mux mux; | |
131 | const struct clk_ops *mux_ops; | |
132 | int mux_frac_idx; | |
133 | ||
134 | bool rate_change_remuxed; | |
135 | int rate_change_idx; | |
136 | }; | |
137 | ||
138 | #define to_rockchip_clk_frac_nb(nb) \ | |
139 | container_of(nb, struct rockchip_clk_frac, clk_nb) | |
140 | ||
141 | static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb, | |
142 | unsigned long event, void *data) | |
143 | { | |
144 | struct clk_notifier_data *ndata = data; | |
145 | struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb); | |
146 | struct clk_mux *frac_mux = &frac->mux; | |
147 | int ret = 0; | |
148 | ||
149 | pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n", | |
150 | __func__, event, ndata->old_rate, ndata->new_rate); | |
151 | if (event == PRE_RATE_CHANGE) { | |
03ae1747 HS |
152 | frac->rate_change_idx = |
153 | frac->mux_ops->get_parent(&frac_mux->hw); | |
8ca1ca8f | 154 | if (frac->rate_change_idx != frac->mux_frac_idx) { |
03ae1747 HS |
155 | frac->mux_ops->set_parent(&frac_mux->hw, |
156 | frac->mux_frac_idx); | |
8ca1ca8f HS |
157 | frac->rate_change_remuxed = 1; |
158 | } | |
159 | } else if (event == POST_RATE_CHANGE) { | |
160 | /* | |
161 | * The POST_RATE_CHANGE notifier runs directly after the | |
162 | * divider clock is set in clk_change_rate, so we'll have | |
163 | * remuxed back to the original parent before clk_change_rate | |
164 | * reaches the mux itself. | |
165 | */ | |
166 | if (frac->rate_change_remuxed) { | |
03ae1747 HS |
167 | frac->mux_ops->set_parent(&frac_mux->hw, |
168 | frac->rate_change_idx); | |
8ca1ca8f HS |
169 | frac->rate_change_remuxed = 0; |
170 | } | |
171 | } | |
172 | ||
173 | return notifier_from_errno(ret); | |
174 | } | |
175 | ||
41517371 | 176 | /* |
5d890c2d EZ |
177 | * fractional divider must set that denominator is 20 times larger than |
178 | * numerator to generate precise clock frequency. | |
179 | */ | |
1dfcfa72 | 180 | static void rockchip_fractional_approximation(struct clk_hw *hw, |
5d890c2d EZ |
181 | unsigned long rate, unsigned long *parent_rate, |
182 | unsigned long *m, unsigned long *n) | |
183 | { | |
10b74af3 | 184 | struct clk_fractional_divider *fd = to_clk_fd(hw); |
5d890c2d EZ |
185 | unsigned long p_rate, p_parent_rate; |
186 | struct clk_hw *p_parent; | |
5d890c2d EZ |
187 | |
188 | p_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); | |
189 | if ((rate * 20 > p_rate) && (p_rate % rate != 0)) { | |
190 | p_parent = clk_hw_get_parent(clk_hw_get_parent(hw)); | |
191 | p_parent_rate = clk_hw_get_rate(p_parent); | |
192 | *parent_rate = p_parent_rate; | |
193 | } | |
194 | ||
10b74af3 QS |
195 | fd->flags |= CLK_FRAC_DIVIDER_POWER_OF_TWO_PS; |
196 | ||
4e7cf74f | 197 | clk_fractional_divider_general_approximation(hw, rate, parent_rate, m, n); |
5d890c2d EZ |
198 | } |
199 | ||
ff94c866 SR |
200 | static void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, |
201 | struct clk *clk, unsigned int id) | |
202 | { | |
203 | ctx->clk_data.clks[id] = clk; | |
204 | } | |
205 | ||
ef1d9fee XZ |
206 | static struct clk *rockchip_clk_register_frac_branch( |
207 | struct rockchip_clk_provider *ctx, const char *name, | |
4a1caed3 UKK |
208 | const char *const *parent_names, u8 num_parents, |
209 | void __iomem *base, int muxdiv_offset, u8 div_flags, | |
b2155a71 | 210 | int gate_offset, u8 gate_shift, u8 gate_flags, |
8ca1ca8f HS |
211 | unsigned long flags, struct rockchip_clk_branch *child, |
212 | spinlock_t *lock) | |
b2155a71 | 213 | { |
63207c37 | 214 | struct clk_hw *hw; |
8ca1ca8f | 215 | struct rockchip_clk_frac *frac; |
b2155a71 HS |
216 | struct clk_gate *gate = NULL; |
217 | struct clk_fractional_divider *div = NULL; | |
218 | const struct clk_ops *div_ops = NULL, *gate_ops = NULL; | |
219 | ||
8ca1ca8f HS |
220 | if (muxdiv_offset < 0) |
221 | return ERR_PTR(-EINVAL); | |
222 | ||
223 | if (child && child->branch_type != branch_mux) { | |
224 | pr_err("%s: fractional child clock for %s can only be a mux\n", | |
225 | __func__, name); | |
226 | return ERR_PTR(-EINVAL); | |
227 | } | |
b2155a71 | 228 | |
8ca1ca8f HS |
229 | frac = kzalloc(sizeof(*frac), GFP_KERNEL); |
230 | if (!frac) | |
231 | return ERR_PTR(-ENOMEM); | |
232 | ||
233 | if (gate_offset >= 0) { | |
234 | gate = &frac->gate; | |
b2155a71 HS |
235 | gate->flags = gate_flags; |
236 | gate->reg = base + gate_offset; | |
237 | gate->bit_idx = gate_shift; | |
238 | gate->lock = lock; | |
239 | gate_ops = &clk_gate_ops; | |
240 | } | |
241 | ||
8ca1ca8f | 242 | div = &frac->div; |
b2155a71 HS |
243 | div->flags = div_flags; |
244 | div->reg = base + muxdiv_offset; | |
245 | div->mshift = 16; | |
5d49a6e1 | 246 | div->mwidth = 16; |
b2155a71 | 247 | div->nshift = 0; |
5d49a6e1 | 248 | div->nwidth = 16; |
b2155a71 | 249 | div->lock = lock; |
5d890c2d | 250 | div->approximation = rockchip_fractional_approximation; |
b2155a71 HS |
251 | div_ops = &clk_fractional_divider_ops; |
252 | ||
63207c37 EZ |
253 | hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, |
254 | NULL, NULL, | |
255 | &div->hw, div_ops, | |
256 | gate ? &gate->hw : NULL, gate_ops, | |
257 | flags | CLK_SET_RATE_UNGATE); | |
258 | if (IS_ERR(hw)) { | |
8ca1ca8f | 259 | kfree(frac); |
63207c37 | 260 | return ERR_CAST(hw); |
8ca1ca8f HS |
261 | } |
262 | ||
263 | if (child) { | |
264 | struct clk_mux *frac_mux = &frac->mux; | |
265 | struct clk_init_data init; | |
266 | struct clk *mux_clk; | |
a425702f | 267 | int ret; |
8ca1ca8f | 268 | |
a425702f YX |
269 | frac->mux_frac_idx = match_string(child->parent_names, |
270 | child->num_parents, name); | |
8ca1ca8f HS |
271 | frac->mux_ops = &clk_mux_ops; |
272 | frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb; | |
273 | ||
274 | frac_mux->reg = base + child->muxdiv_offset; | |
275 | frac_mux->shift = child->mux_shift; | |
276 | frac_mux->mask = BIT(child->mux_width) - 1; | |
277 | frac_mux->flags = child->mux_flags; | |
30d8b7d4 EZ |
278 | if (child->mux_table) |
279 | frac_mux->table = child->mux_table; | |
8ca1ca8f HS |
280 | frac_mux->lock = lock; |
281 | frac_mux->hw.init = &init; | |
282 | ||
283 | init.name = child->name; | |
284 | init.flags = child->flags | CLK_SET_RATE_PARENT; | |
285 | init.ops = frac->mux_ops; | |
286 | init.parent_names = child->parent_names; | |
287 | init.num_parents = child->num_parents; | |
288 | ||
289 | mux_clk = clk_register(NULL, &frac_mux->hw); | |
fd3cbbfb SL |
290 | if (IS_ERR(mux_clk)) { |
291 | kfree(frac); | |
63207c37 | 292 | return mux_clk; |
fd3cbbfb | 293 | } |
8ca1ca8f | 294 | |
ef1d9fee | 295 | rockchip_clk_add_lookup(ctx, mux_clk, child->id); |
8ca1ca8f HS |
296 | |
297 | /* notifier on the fraction divider to catch rate changes */ | |
298 | if (frac->mux_frac_idx >= 0) { | |
a425702f YX |
299 | pr_debug("%s: found fractional parent in mux at pos %d\n", |
300 | __func__, frac->mux_frac_idx); | |
63207c37 | 301 | ret = clk_notifier_register(hw->clk, &frac->clk_nb); |
8ca1ca8f HS |
302 | if (ret) |
303 | pr_err("%s: failed to register clock notifier for %s\n", | |
304 | __func__, name); | |
305 | } else { | |
306 | pr_warn("%s: could not find %s as parent of %s, rate changes may not work\n", | |
307 | __func__, name, child->name); | |
308 | } | |
309 | } | |
b2155a71 | 310 | |
63207c37 | 311 | return hw->clk; |
b2155a71 HS |
312 | } |
313 | ||
29a30c26 HS |
314 | static struct clk *rockchip_clk_register_factor_branch(const char *name, |
315 | const char *const *parent_names, u8 num_parents, | |
316 | void __iomem *base, unsigned int mult, unsigned int div, | |
317 | int gate_offset, u8 gate_shift, u8 gate_flags, | |
318 | unsigned long flags, spinlock_t *lock) | |
319 | { | |
63207c37 | 320 | struct clk_hw *hw; |
29a30c26 HS |
321 | struct clk_gate *gate = NULL; |
322 | struct clk_fixed_factor *fix = NULL; | |
323 | ||
324 | /* without gate, register a simple factor clock */ | |
325 | if (gate_offset == 0) { | |
326 | return clk_register_fixed_factor(NULL, name, | |
327 | parent_names[0], flags, mult, | |
328 | div); | |
329 | } | |
330 | ||
331 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); | |
332 | if (!gate) | |
333 | return ERR_PTR(-ENOMEM); | |
334 | ||
335 | gate->flags = gate_flags; | |
336 | gate->reg = base + gate_offset; | |
337 | gate->bit_idx = gate_shift; | |
338 | gate->lock = lock; | |
339 | ||
340 | fix = kzalloc(sizeof(*fix), GFP_KERNEL); | |
341 | if (!fix) { | |
342 | kfree(gate); | |
343 | return ERR_PTR(-ENOMEM); | |
344 | } | |
345 | ||
346 | fix->mult = mult; | |
347 | fix->div = div; | |
348 | ||
63207c37 EZ |
349 | hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, |
350 | NULL, NULL, | |
351 | &fix->hw, &clk_fixed_factor_ops, | |
352 | &gate->hw, &clk_gate_ops, flags); | |
353 | if (IS_ERR(hw)) { | |
29a30c26 HS |
354 | kfree(fix); |
355 | kfree(gate); | |
63207c37 | 356 | return ERR_CAST(hw); |
29a30c26 HS |
357 | } |
358 | ||
63207c37 | 359 | return hw->clk; |
29a30c26 HS |
360 | } |
361 | ||
ea650c26 EZ |
362 | struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, |
363 | void __iomem *base, | |
364 | unsigned long nr_clks) | |
a245fecb | 365 | { |
ef1d9fee XZ |
366 | struct rockchip_clk_provider *ctx; |
367 | struct clk **clk_table; | |
368 | int i; | |
369 | ||
370 | ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL); | |
03ae1747 | 371 | if (!ctx) |
ef1d9fee | 372 | return ERR_PTR(-ENOMEM); |
a245fecb HS |
373 | |
374 | clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); | |
03ae1747 | 375 | if (!clk_table) |
ef1d9fee | 376 | goto err_free; |
ef1d9fee XZ |
377 | |
378 | for (i = 0; i < nr_clks; ++i) | |
379 | clk_table[i] = ERR_PTR(-ENOENT); | |
a245fecb | 380 | |
ef1d9fee XZ |
381 | ctx->reg_base = base; |
382 | ctx->clk_data.clks = clk_table; | |
383 | ctx->clk_data.clk_num = nr_clks; | |
384 | ctx->cru_node = np; | |
ef1d9fee XZ |
385 | spin_lock_init(&ctx->lock); |
386 | ||
6f339dc2 HS |
387 | ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node, |
388 | "rockchip,grf"); | |
389 | ||
ef1d9fee XZ |
390 | return ctx; |
391 | ||
392 | err_free: | |
393 | kfree(ctx); | |
394 | return ERR_PTR(-ENOMEM); | |
395 | } | |
ea650c26 | 396 | EXPORT_SYMBOL_GPL(rockchip_clk_init); |
ef1d9fee | 397 | |
ea650c26 EZ |
398 | void rockchip_clk_of_add_provider(struct device_node *np, |
399 | struct rockchip_clk_provider *ctx) | |
ef1d9fee | 400 | { |
ff1ae209 SL |
401 | if (of_clk_add_provider(np, of_clk_src_onecell_get, |
402 | &ctx->clk_data)) | |
403 | pr_err("%s: could not register clk provider\n", __func__); | |
a245fecb | 404 | } |
ea650c26 | 405 | EXPORT_SYMBOL_GPL(rockchip_clk_of_add_provider); |
a245fecb | 406 | |
ea650c26 | 407 | void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, |
ef1d9fee | 408 | struct rockchip_pll_clock *list, |
90c59025 HS |
409 | unsigned int nr_pll, int grf_lock_offset) |
410 | { | |
411 | struct clk *clk; | |
412 | int idx; | |
413 | ||
414 | for (idx = 0; idx < nr_pll; idx++, list++) { | |
ef1d9fee | 415 | clk = rockchip_clk_register_pll(ctx, list->type, list->name, |
90c59025 | 416 | list->parent_names, list->num_parents, |
ef1d9fee | 417 | list->con_offset, grf_lock_offset, |
90c59025 | 418 | list->lock_shift, list->mode_offset, |
4f8a7c54 | 419 | list->mode_shift, list->rate_table, |
e6cebc72 | 420 | list->flags, list->pll_flags); |
90c59025 HS |
421 | if (IS_ERR(clk)) { |
422 | pr_err("%s: failed to register clock %s\n", __func__, | |
423 | list->name); | |
424 | continue; | |
425 | } | |
426 | ||
ef1d9fee | 427 | rockchip_clk_add_lookup(ctx, clk, list->id); |
90c59025 HS |
428 | } |
429 | } | |
ea650c26 | 430 | EXPORT_SYMBOL_GPL(rockchip_clk_register_plls); |
90c59025 | 431 | |
2dc66a5a SR |
432 | unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list, |
433 | unsigned int nr_clk) | |
434 | { | |
435 | unsigned long max = 0; | |
436 | unsigned int idx; | |
437 | ||
438 | for (idx = 0; idx < nr_clk; idx++, list++) { | |
439 | if (list->id > max) | |
440 | max = list->id; | |
441 | if (list->child && list->child->id > max) | |
442 | max = list->id; | |
443 | } | |
444 | ||
445 | return max; | |
446 | } | |
447 | EXPORT_SYMBOL_GPL(rockchip_clk_find_max_clk_id); | |
448 | ||
ea650c26 EZ |
449 | void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, |
450 | struct rockchip_clk_branch *list, | |
451 | unsigned int nr_clk) | |
a245fecb HS |
452 | { |
453 | struct clk *clk = NULL; | |
454 | unsigned int idx; | |
455 | unsigned long flags; | |
456 | ||
457 | for (idx = 0; idx < nr_clk; idx++, list++) { | |
458 | flags = list->flags; | |
459 | ||
460 | /* catch simple muxes */ | |
461 | switch (list->branch_type) { | |
462 | case branch_mux: | |
30d8b7d4 EZ |
463 | if (list->mux_table) |
464 | clk = clk_register_mux_table(NULL, list->name, | |
465 | list->parent_names, list->num_parents, | |
466 | flags, | |
467 | ctx->reg_base + list->muxdiv_offset, | |
468 | list->mux_shift, list->mux_width, | |
469 | list->mux_flags, list->mux_table, | |
470 | &ctx->lock); | |
471 | else | |
472 | clk = clk_register_mux(NULL, list->name, | |
473 | list->parent_names, list->num_parents, | |
474 | flags, | |
475 | ctx->reg_base + list->muxdiv_offset, | |
476 | list->mux_shift, list->mux_width, | |
477 | list->mux_flags, &ctx->lock); | |
a245fecb | 478 | break; |
cb1d9f6d HS |
479 | case branch_muxgrf: |
480 | clk = rockchip_clk_register_muxgrf(list->name, | |
481 | list->parent_names, list->num_parents, | |
482 | flags, ctx->grf, list->muxdiv_offset, | |
483 | list->mux_shift, list->mux_width, | |
484 | list->mux_flags); | |
485 | break; | |
a245fecb HS |
486 | case branch_divider: |
487 | if (list->div_table) | |
488 | clk = clk_register_divider_table(NULL, | |
489 | list->name, list->parent_names[0], | |
03ae1747 HS |
490 | flags, |
491 | ctx->reg_base + list->muxdiv_offset, | |
a245fecb HS |
492 | list->div_shift, list->div_width, |
493 | list->div_flags, list->div_table, | |
ef1d9fee | 494 | &ctx->lock); |
a245fecb HS |
495 | else |
496 | clk = clk_register_divider(NULL, list->name, | |
497 | list->parent_names[0], flags, | |
ef1d9fee | 498 | ctx->reg_base + list->muxdiv_offset, |
a245fecb | 499 | list->div_shift, list->div_width, |
ef1d9fee | 500 | list->div_flags, &ctx->lock); |
a245fecb HS |
501 | break; |
502 | case branch_fraction_divider: | |
ef1d9fee | 503 | clk = rockchip_clk_register_frac_branch(ctx, list->name, |
b2155a71 | 504 | list->parent_names, list->num_parents, |
03ae1747 HS |
505 | ctx->reg_base, list->muxdiv_offset, |
506 | list->div_flags, | |
b2155a71 | 507 | list->gate_offset, list->gate_shift, |
8ca1ca8f | 508 | list->gate_flags, flags, list->child, |
ef1d9fee | 509 | &ctx->lock); |
a245fecb | 510 | break; |
956060a5 EZ |
511 | case branch_half_divider: |
512 | clk = rockchip_clk_register_halfdiv(list->name, | |
513 | list->parent_names, list->num_parents, | |
514 | ctx->reg_base, list->muxdiv_offset, | |
515 | list->mux_shift, list->mux_width, | |
516 | list->mux_flags, list->div_shift, | |
517 | list->div_width, list->div_flags, | |
518 | list->gate_offset, list->gate_shift, | |
519 | list->gate_flags, flags, &ctx->lock); | |
520 | break; | |
a245fecb HS |
521 | case branch_gate: |
522 | flags |= CLK_SET_RATE_PARENT; | |
523 | ||
a245fecb HS |
524 | clk = clk_register_gate(NULL, list->name, |
525 | list->parent_names[0], flags, | |
ef1d9fee XZ |
526 | ctx->reg_base + list->gate_offset, |
527 | list->gate_shift, list->gate_flags, &ctx->lock); | |
a245fecb HS |
528 | break; |
529 | case branch_composite: | |
a245fecb HS |
530 | clk = rockchip_clk_register_branch(list->name, |
531 | list->parent_names, list->num_parents, | |
03ae1747 HS |
532 | ctx->reg_base, list->muxdiv_offset, |
533 | list->mux_shift, | |
a245fecb | 534 | list->mux_width, list->mux_flags, |
30d8b7d4 EZ |
535 | list->mux_table, list->div_offset, |
536 | list->div_shift, list->div_width, | |
a245fecb HS |
537 | list->div_flags, list->div_table, |
538 | list->gate_offset, list->gate_shift, | |
ef1d9fee | 539 | list->gate_flags, flags, &ctx->lock); |
a245fecb | 540 | break; |
89bf26cb AS |
541 | case branch_mmc: |
542 | clk = rockchip_clk_register_mmc( | |
543 | list->name, | |
544 | list->parent_names, list->num_parents, | |
ef1d9fee | 545 | ctx->reg_base + list->muxdiv_offset, |
89bf26cb AS |
546 | list->div_shift |
547 | ); | |
548 | break; | |
8a76f443 HS |
549 | case branch_inverter: |
550 | clk = rockchip_clk_register_inverter( | |
551 | list->name, list->parent_names, | |
552 | list->num_parents, | |
ef1d9fee XZ |
553 | ctx->reg_base + list->muxdiv_offset, |
554 | list->div_shift, list->div_flags, &ctx->lock); | |
8a76f443 | 555 | break; |
29a30c26 HS |
556 | case branch_factor: |
557 | clk = rockchip_clk_register_factor_branch( | |
558 | list->name, list->parent_names, | |
ef1d9fee | 559 | list->num_parents, ctx->reg_base, |
29a30c26 HS |
560 | list->div_shift, list->div_width, |
561 | list->gate_offset, list->gate_shift, | |
ef1d9fee | 562 | list->gate_flags, flags, &ctx->lock); |
29a30c26 | 563 | break; |
a4f182bf LH |
564 | case branch_ddrclk: |
565 | clk = rockchip_clk_register_ddrclk( | |
566 | list->name, list->flags, | |
567 | list->parent_names, list->num_parents, | |
568 | list->muxdiv_offset, list->mux_shift, | |
569 | list->mux_width, list->div_shift, | |
570 | list->div_width, list->div_flags, | |
571 | ctx->reg_base, &ctx->lock); | |
572 | break; | |
a245fecb HS |
573 | } |
574 | ||
575 | /* none of the cases above matched */ | |
576 | if (!clk) { | |
577 | pr_err("%s: unknown clock type %d\n", | |
578 | __func__, list->branch_type); | |
579 | continue; | |
580 | } | |
581 | ||
582 | if (IS_ERR(clk)) { | |
583 | pr_err("%s: failed to register clock %s: %ld\n", | |
584 | __func__, list->name, PTR_ERR(clk)); | |
585 | continue; | |
586 | } | |
587 | ||
ef1d9fee | 588 | rockchip_clk_add_lookup(ctx, clk, list->id); |
a245fecb HS |
589 | } |
590 | } | |
ea650c26 EZ |
591 | EXPORT_SYMBOL_GPL(rockchip_clk_register_branches); |
592 | ||
593 | void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, | |
594 | unsigned int lookup_id, | |
595 | const char *name, const char *const *parent_names, | |
596 | u8 num_parents, | |
597 | const struct rockchip_cpuclk_reg_data *reg_data, | |
598 | const struct rockchip_cpuclk_rate_table *rates, | |
599 | int nrates) | |
f6fba5f6 HS |
600 | { |
601 | struct clk *clk; | |
602 | ||
603 | clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents, | |
03ae1747 HS |
604 | reg_data, rates, nrates, |
605 | ctx->reg_base, &ctx->lock); | |
f6fba5f6 HS |
606 | if (IS_ERR(clk)) { |
607 | pr_err("%s: failed to register clock %s: %ld\n", | |
608 | __func__, name, PTR_ERR(clk)); | |
609 | return; | |
610 | } | |
611 | ||
ef1d9fee | 612 | rockchip_clk_add_lookup(ctx, clk, lookup_id); |
f6fba5f6 | 613 | } |
ea650c26 | 614 | EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk); |
f6fba5f6 | 615 | |
ea650c26 EZ |
616 | void rockchip_clk_protect_critical(const char *const clocks[], |
617 | int nclocks) | |
fe94f974 HS |
618 | { |
619 | int i; | |
620 | ||
621 | /* Protect the clocks that needs to stay on */ | |
622 | for (i = 0; i < nclocks; i++) { | |
623 | struct clk *clk = __clk_lookup(clocks[i]); | |
624 | ||
7f5b57a0 | 625 | clk_prepare_enable(clk); |
fe94f974 HS |
626 | } |
627 | } | |
ea650c26 | 628 | EXPORT_SYMBOL_GPL(rockchip_clk_protect_critical); |
6f1294b5 | 629 | |
ef1d9fee | 630 | static void __iomem *rst_base; |
6f1294b5 | 631 | static unsigned int reg_restart; |
dfff24bd | 632 | static void (*cb_restart)(void); |
6f1294b5 HS |
633 | static int rockchip_restart_notify(struct notifier_block *this, |
634 | unsigned long mode, void *cmd) | |
635 | { | |
dfff24bd HS |
636 | if (cb_restart) |
637 | cb_restart(); | |
638 | ||
ef1d9fee | 639 | writel(0xfdb9, rst_base + reg_restart); |
6f1294b5 HS |
640 | return NOTIFY_DONE; |
641 | } | |
642 | ||
643 | static struct notifier_block rockchip_restart_handler = { | |
644 | .notifier_call = rockchip_restart_notify, | |
645 | .priority = 128, | |
646 | }; | |
647 | ||
ea650c26 | 648 | void |
03ae1747 | 649 | rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx, |
ea650c26 EZ |
650 | unsigned int reg, |
651 | void (*cb)(void)) | |
6f1294b5 HS |
652 | { |
653 | int ret; | |
654 | ||
ef1d9fee | 655 | rst_base = ctx->reg_base; |
6f1294b5 | 656 | reg_restart = reg; |
dfff24bd | 657 | cb_restart = cb; |
6f1294b5 HS |
658 | ret = register_restart_handler(&rockchip_restart_handler); |
659 | if (ret) | |
660 | pr_err("%s: cannot register restart handler, %d\n", | |
661 | __func__, ret); | |
662 | } | |
ea650c26 | 663 | EXPORT_SYMBOL_GPL(rockchip_register_restart_notifier); |