[linux-block.git] / drivers / clk / rockchip / clk.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (c) 2014 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 *
 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
 * Author: Xing Zheng <zhengxing@rock-chips.com>
 *
 * based on
 *
 * samsung/clk.c
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 * Copyright (c) 2013 Linaro Ltd.
 * Author: Thomas Abraham <thomas.ab@samsung.com>
 */

#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/reboot.h>

#include "../clk-fractional-divider.h"
#include "clk.h"

/*
 * Register a clock branch.
 * Most clock branches have a form like
 *
 * src1 --|--\
 *        |M |--[GATE]-[DIV]-
 * src2 --|--/
 *
 * sometimes without one of those components.
 */
static struct clk *rockchip_clk_register_branch(const char *name,
		const char *const *parent_names, u8 num_parents,
		void __iomem *base,
		int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
		u32 *mux_table,
		int div_offset, u8 div_shift, u8 div_width, u8 div_flags,
		struct clk_div_table *div_table, int gate_offset,
		u8 gate_shift, u8 gate_flags, unsigned long flags,
		spinlock_t *lock)
{
	struct clk_hw *hw;
	struct clk_mux *mux = NULL;
	struct clk_gate *gate = NULL;
	struct clk_divider *div = NULL;
	const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
			     *gate_ops = NULL;
	int ret;

	if (num_parents > 1) {
		mux = kzalloc(sizeof(*mux), GFP_KERNEL);
		if (!mux)
			return ERR_PTR(-ENOMEM);

		mux->reg = base + muxdiv_offset;
		mux->shift = mux_shift;
		mux->mask = BIT(mux_width) - 1;
		mux->flags = mux_flags;
		mux->table = mux_table;
		mux->lock = lock;
		mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
							: &clk_mux_ops;
	}

	if (gate_offset >= 0) {
		gate = kzalloc(sizeof(*gate), GFP_KERNEL);
		if (!gate) {
			ret = -ENOMEM;
			goto err_gate;
		}

		gate->flags = gate_flags;
		gate->reg = base + gate_offset;
		gate->bit_idx = gate_shift;
		gate->lock = lock;
		gate_ops = &clk_gate_ops;
	}

	if (div_width > 0) {
		div = kzalloc(sizeof(*div), GFP_KERNEL);
		if (!div) {
			ret = -ENOMEM;
			goto err_div;
		}

		div->flags = div_flags;
		if (div_offset)
			div->reg = base + div_offset;
		else
			div->reg = base + muxdiv_offset;
		div->shift = div_shift;
		div->width = div_width;
		div->lock = lock;
		div->table = div_table;
		div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
						? &clk_divider_ro_ops
						: &clk_divider_ops;
	}

	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
				       mux ? &mux->hw : NULL, mux_ops,
				       div ? &div->hw : NULL, div_ops,
				       gate ? &gate->hw : NULL, gate_ops,
				       flags);
	if (IS_ERR(hw)) {
		kfree(div);
		kfree(gate);
		return ERR_CAST(hw);
	}

	return hw->clk;
err_div:
	kfree(gate);
err_gate:
	kfree(mux);
	return ERR_PTR(ret);
}

struct rockchip_clk_frac {
	struct notifier_block			clk_nb;
	struct clk_fractional_divider		div;
	struct clk_gate				gate;

	struct clk_mux				mux;
	const struct clk_ops			*mux_ops;
	int					mux_frac_idx;

	bool					rate_change_remuxed;
	int					rate_change_idx;
};

#define to_rockchip_clk_frac_nb(nb) \
			container_of(nb, struct rockchip_clk_frac, clk_nb)

static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
					 unsigned long event, void *data)
{
	struct clk_notifier_data *ndata = data;
	struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb);
	struct clk_mux *frac_mux = &frac->mux;
	int ret = 0;

	pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
		 __func__, event, ndata->old_rate, ndata->new_rate);
	if (event == PRE_RATE_CHANGE) {
		frac->rate_change_idx =
				frac->mux_ops->get_parent(&frac_mux->hw);
		if (frac->rate_change_idx != frac->mux_frac_idx) {
			frac->mux_ops->set_parent(&frac_mux->hw,
						  frac->mux_frac_idx);
			frac->rate_change_remuxed = 1;
		}
	} else if (event == POST_RATE_CHANGE) {
		/*
		 * The POST_RATE_CHANGE notifier runs directly after the
		 * divider clock is set in clk_change_rate, so we'll have
		 * remuxed back to the original parent before clk_change_rate
		 * reaches the mux itself.
		 */
		if (frac->rate_change_remuxed) {
			frac->mux_ops->set_parent(&frac_mux->hw,
						  frac->rate_change_idx);
			frac->rate_change_remuxed = 0;
		}
	}

	return notifier_from_errno(ret);
}

/*
 * fractional divider must set that denominator is 20 times larger than
 * numerator to generate precise clock frequency.
 */
static void rockchip_fractional_approximation(struct clk_hw *hw,
		unsigned long rate, unsigned long *parent_rate,
		unsigned long *m, unsigned long *n)
{
	struct clk_fractional_divider *fd = to_clk_fd(hw);
	unsigned long p_rate, p_parent_rate;
	struct clk_hw *p_parent;

	p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
	if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
		p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
		p_parent_rate = clk_hw_get_rate(p_parent);
		*parent_rate = p_parent_rate;
	}

	fd->flags |= CLK_FRAC_DIVIDER_POWER_OF_TWO_PS;

	clk_fractional_divider_general_approximation(hw, rate, parent_rate, m, n);
}

static void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
				    struct clk *clk, unsigned int id)
{
	ctx->clk_data.clks[id] = clk;
}

static struct clk *rockchip_clk_register_frac_branch(
		struct rockchip_clk_provider *ctx, const char *name,
		const char *const *parent_names, u8 num_parents,
		void __iomem *base, int muxdiv_offset, u8 div_flags,
		int gate_offset, u8 gate_shift, u8 gate_flags,
		unsigned long flags, struct rockchip_clk_branch *child,
		spinlock_t *lock)
{
	struct clk_hw *hw;
	struct rockchip_clk_frac *frac;
	struct clk_gate *gate = NULL;
	struct clk_fractional_divider *div = NULL;
	const struct clk_ops *div_ops = NULL, *gate_ops = NULL;

	if (muxdiv_offset < 0)
		return ERR_PTR(-EINVAL);

	if (child && child->branch_type != branch_mux) {
		pr_err("%s: fractional child clock for %s can only be a mux\n",
		       __func__, name);
		return ERR_PTR(-EINVAL);
	}

	frac = kzalloc(sizeof(*frac), GFP_KERNEL);
	if (!frac)
		return ERR_PTR(-ENOMEM);

	if (gate_offset >= 0) {
		gate = &frac->gate;
		gate->flags = gate_flags;
		gate->reg = base + gate_offset;
		gate->bit_idx = gate_shift;
		gate->lock = lock;
		gate_ops = &clk_gate_ops;
	}

	div = &frac->div;
	div->flags = div_flags;
	div->reg = base + muxdiv_offset;
	div->mshift = 16;
	div->mwidth = 16;
	div->nshift = 0;
	div->nwidth = 16;
	div->lock = lock;
	div->approximation = rockchip_fractional_approximation;
	div_ops = &clk_fractional_divider_ops;

	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
				       NULL, NULL,
				       &div->hw, div_ops,
				       gate ? &gate->hw : NULL, gate_ops,
				       flags | CLK_SET_RATE_UNGATE);
	if (IS_ERR(hw)) {
		kfree(frac);
		return ERR_CAST(hw);
	}

	if (child) {
		struct clk_mux *frac_mux = &frac->mux;
		struct clk_init_data init;
		struct clk *mux_clk;
		int ret;

		frac->mux_frac_idx = match_string(child->parent_names,
						  child->num_parents, name);
		frac->mux_ops = &clk_mux_ops;
		frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb;

		frac_mux->reg = base + child->muxdiv_offset;
		frac_mux->shift = child->mux_shift;
		frac_mux->mask = BIT(child->mux_width) - 1;
		frac_mux->flags = child->mux_flags;
		if (child->mux_table)
			frac_mux->table = child->mux_table;
		frac_mux->lock = lock;
		frac_mux->hw.init = &init;

		init.name = child->name;
		init.flags = child->flags | CLK_SET_RATE_PARENT;
		init.ops = frac->mux_ops;
		init.parent_names = child->parent_names;
		init.num_parents = child->num_parents;

		mux_clk = clk_register(NULL, &frac_mux->hw);
		if (IS_ERR(mux_clk)) {
			kfree(frac);
			return mux_clk;
		}

		rockchip_clk_add_lookup(ctx, mux_clk, child->id);

		/* notifier on the fraction divider to catch rate changes */
		if (frac->mux_frac_idx >= 0) {
			pr_debug("%s: found fractional parent in mux at pos %d\n",
				 __func__, frac->mux_frac_idx);
			ret = clk_notifier_register(hw->clk, &frac->clk_nb);
			if (ret)
				pr_err("%s: failed to register clock notifier for %s\n",
						__func__, name);
		} else {
			pr_warn("%s: could not find %s as parent of %s, rate changes may not work\n",
				__func__, name, child->name);
		}
	}

	return hw->clk;
}

static struct clk *rockchip_clk_register_factor_branch(const char *name,
		const char *const *parent_names, u8 num_parents,
		void __iomem *base, unsigned int mult, unsigned int div,
		int gate_offset, u8 gate_shift, u8 gate_flags,
		unsigned long flags, spinlock_t *lock)
{
	struct clk_hw *hw;
	struct clk_gate *gate = NULL;
	struct clk_fixed_factor *fix = NULL;

	/* without gate, register a simple factor clock */
	if (gate_offset == 0) {
		return clk_register_fixed_factor(NULL, name,
				parent_names[0], flags, mult,
				div);
	}

	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
	if (!gate)
		return ERR_PTR(-ENOMEM);

	gate->flags = gate_flags;
	gate->reg = base + gate_offset;
	gate->bit_idx = gate_shift;
	gate->lock = lock;

	fix = kzalloc(sizeof(*fix), GFP_KERNEL);
	if (!fix) {
		kfree(gate);
		return ERR_PTR(-ENOMEM);
	}

	fix->mult = mult;
	fix->div = div;

	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
				       NULL, NULL,
				       &fix->hw, &clk_fixed_factor_ops,
				       &gate->hw, &clk_gate_ops, flags);
	if (IS_ERR(hw)) {
		kfree(fix);
		kfree(gate);
		return ERR_CAST(hw);
	}

	return hw->clk;
}

struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
						void __iomem *base,
						unsigned long nr_clks)
{
	struct rockchip_clk_provider *ctx;
	struct clk **clk_table;
	int i;

	ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL);
	if (!ctx)
		return ERR_PTR(-ENOMEM);

	clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
	if (!clk_table)
		goto err_free;

	for (i = 0; i < nr_clks; ++i)
		clk_table[i] = ERR_PTR(-ENOENT);

	ctx->reg_base = base;
	ctx->clk_data.clks = clk_table;
	ctx->clk_data.clk_num = nr_clks;
	ctx->cru_node = np;
	spin_lock_init(&ctx->lock);

	ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
						   "rockchip,grf");

	return ctx;

err_free:
	kfree(ctx);
	return ERR_PTR(-ENOMEM);
}
EXPORT_SYMBOL_GPL(rockchip_clk_init);

void rockchip_clk_of_add_provider(struct device_node *np,
				  struct rockchip_clk_provider *ctx)
{
	if (of_clk_add_provider(np, of_clk_src_onecell_get,
				&ctx->clk_data))
		pr_err("%s: could not register clk provider\n", __func__);
}
EXPORT_SYMBOL_GPL(rockchip_clk_of_add_provider);

void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
				struct rockchip_pll_clock *list,
				unsigned int nr_pll, int grf_lock_offset)
{
	struct clk *clk;
	int idx;

	for (idx = 0; idx < nr_pll; idx++, list++) {
		clk = rockchip_clk_register_pll(ctx, list->type, list->name,
				list->parent_names, list->num_parents,
				list->con_offset, grf_lock_offset,
				list->lock_shift, list->mode_offset,
				list->mode_shift, list->rate_table,
				list->flags, list->pll_flags);
		if (IS_ERR(clk)) {
			pr_err("%s: failed to register clock %s\n", __func__,
				list->name);
			continue;
		}

		rockchip_clk_add_lookup(ctx, clk, list->id);
	}
}
EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);

void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
				    struct rockchip_clk_branch *list,
				    unsigned int nr_clk)
{
	struct clk *clk = NULL;
	unsigned int idx;
	unsigned long flags;

	for (idx = 0; idx < nr_clk; idx++, list++) {
		flags = list->flags;

		/* catch simple muxes */
		switch (list->branch_type) {
		case branch_mux:
			if (list->mux_table)
				clk = clk_register_mux_table(NULL, list->name,
					list->parent_names, list->num_parents,
					flags,
					ctx->reg_base + list->muxdiv_offset,
					list->mux_shift, list->mux_width,
					list->mux_flags, list->mux_table,
					&ctx->lock);
			else
				clk = clk_register_mux(NULL, list->name,
					list->parent_names, list->num_parents,
					flags,
					ctx->reg_base + list->muxdiv_offset,
					list->mux_shift, list->mux_width,
					list->mux_flags, &ctx->lock);
			break;
		case branch_muxgrf:
			clk = rockchip_clk_register_muxgrf(list->name,
				list->parent_names, list->num_parents,
				flags, ctx->grf, list->muxdiv_offset,
				list->mux_shift, list->mux_width,
				list->mux_flags);
			break;
		case branch_divider:
			if (list->div_table)
				clk = clk_register_divider_table(NULL,
					list->name, list->parent_names[0],
					flags,
					ctx->reg_base + list->muxdiv_offset,
					list->div_shift, list->div_width,
					list->div_flags, list->div_table,
					&ctx->lock);
			else
				clk = clk_register_divider(NULL, list->name,
					list->parent_names[0], flags,
					ctx->reg_base + list->muxdiv_offset,
					list->div_shift, list->div_width,
					list->div_flags, &ctx->lock);
			break;
		case branch_fraction_divider:
			clk = rockchip_clk_register_frac_branch(ctx, list->name,
				list->parent_names, list->num_parents,
				ctx->reg_base, list->muxdiv_offset,
				list->div_flags,
				list->gate_offset, list->gate_shift,
				list->gate_flags, flags, list->child,
				&ctx->lock);
			break;
		case branch_half_divider:
			clk = rockchip_clk_register_halfdiv(list->name,
				list->parent_names, list->num_parents,
				ctx->reg_base, list->muxdiv_offset,
				list->mux_shift, list->mux_width,
				list->mux_flags, list->div_shift,
				list->div_width, list->div_flags,
				list->gate_offset, list->gate_shift,
				list->gate_flags, flags, &ctx->lock);
			break;
		case branch_gate:
			flags |= CLK_SET_RATE_PARENT;

			clk = clk_register_gate(NULL, list->name,
				list->parent_names[0], flags,
				ctx->reg_base + list->gate_offset,
				list->gate_shift, list->gate_flags, &ctx->lock);
			break;
		case branch_composite:
			clk = rockchip_clk_register_branch(list->name,
				list->parent_names, list->num_parents,
				ctx->reg_base, list->muxdiv_offset,
				list->mux_shift,
				list->mux_width, list->mux_flags,
				list->mux_table, list->div_offset,
				list->div_shift, list->div_width,
				list->div_flags, list->div_table,
				list->gate_offset, list->gate_shift,
				list->gate_flags, flags, &ctx->lock);
			break;
		case branch_mmc:
			clk = rockchip_clk_register_mmc(
				list->name,
				list->parent_names, list->num_parents,
				ctx->reg_base + list->muxdiv_offset,
				list->div_shift
			);
			break;
		case branch_inverter:
			clk = rockchip_clk_register_inverter(
				list->name, list->parent_names,
				list->num_parents,
				ctx->reg_base + list->muxdiv_offset,
				list->div_shift, list->div_flags, &ctx->lock);
			break;
		case branch_factor:
			clk = rockchip_clk_register_factor_branch(
				list->name, list->parent_names,
				list->num_parents, ctx->reg_base,
				list->div_shift, list->div_width,
				list->gate_offset, list->gate_shift,
				list->gate_flags, flags, &ctx->lock);
			break;
		case branch_ddrclk:
			clk = rockchip_clk_register_ddrclk(
				list->name, list->flags,
				list->parent_names, list->num_parents,
				list->muxdiv_offset, list->mux_shift,
				list->mux_width, list->div_shift,
				list->div_width, list->div_flags,
				ctx->reg_base, &ctx->lock);
			break;
		}

		/* none of the cases above matched */
		if (!clk) {
			pr_err("%s: unknown clock type %d\n",
			       __func__, list->branch_type);
			continue;
		}

		if (IS_ERR(clk)) {
			pr_err("%s: failed to register clock %s: %ld\n",
			       __func__, list->name, PTR_ERR(clk));
			continue;
		}

		rockchip_clk_add_lookup(ctx, clk, list->id);
	}
}
EXPORT_SYMBOL_GPL(rockchip_clk_register_branches);

void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
				  unsigned int lookup_id,
				  const char *name, const char *const *parent_names,
				  u8 num_parents,
				  const struct rockchip_cpuclk_reg_data *reg_data,
				  const struct rockchip_cpuclk_rate_table *rates,
				  int nrates)
{
	struct clk *clk;

	clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents,
					   reg_data, rates, nrates,
					   ctx->reg_base, &ctx->lock);
	if (IS_ERR(clk)) {
		pr_err("%s: failed to register clock %s: %ld\n",
		       __func__, name, PTR_ERR(clk));
		return;
	}

	rockchip_clk_add_lookup(ctx, clk, lookup_id);
}
EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk);

void rockchip_clk_protect_critical(const char *const clocks[],
				   int nclocks)
{
	int i;

	/* Protect the clocks that needs to stay on */
	for (i = 0; i < nclocks; i++) {
		struct clk *clk = __clk_lookup(clocks[i]);

		clk_prepare_enable(clk);
	}
}
EXPORT_SYMBOL_GPL(rockchip_clk_protect_critical);

static void __iomem *rst_base;
static unsigned int reg_restart;
static void (*cb_restart)(void);
static int rockchip_restart_notify(struct notifier_block *this,
				   unsigned long mode, void *cmd)
{
	if (cb_restart)
		cb_restart();

	writel(0xfdb9, rst_base + reg_restart);
	return NOTIFY_DONE;
}

static struct notifier_block rockchip_restart_handler = {
	.notifier_call = rockchip_restart_notify,
	.priority = 128,
};

void
rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
				   unsigned int reg,
				   void (*cb)(void))
{
	int ret;

	rst_base = ctx->reg_base;
	reg_restart = reg;
	cb_restart = cb;
	ret = register_restart_handler(&rockchip_restart_handler);
	if (ret)
		pr_err("%s: cannot register restart handler, %d\n",
		       __func__, ret);
}
EXPORT_SYMBOL_GPL(rockchip_register_restart_notifier);
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
a245fecb HS	2	/*
	3	* Copyright (c) 2014 MundoReader S.L.
	4	* Author: Heiko Stuebner <heiko@sntech.de>
	5	*
ef1d9fee XZ	6	* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
	7	* Author: Xing Zheng <zhengxing@rock-chips.com>
	8	*
a245fecb HS	9	* based on
	10	*
	11	* samsung/clk.c
	12	* Copyright (c) 2013 Samsung Electronics Co., Ltd.
	13	* Copyright (c) 2013 Linaro Ltd.
	14	* Author: Thomas Abraham <thomas.ab@samsung.com>
a245fecb HS	15	*/
	16
	17	#include <linux/slab.h>
	18	#include <linux/clk.h>
	19	#include <linux/clk-provider.h>
62e59c4e	20	#include <linux/io.h>
90c59025 HS	21	#include <linux/mfd/syscon.h>
90c59025 HS	22	#include <linux/regmap.h>
6f1294b5	23	#include <linux/reboot.h>
4e7cf74f AS	24
4e7cf74f AS	25	#include "../clk-fractional-divider.h"
a245fecb HS	26	#include "clk.h"
a245fecb HS	27
41517371	28	/*
a245fecb HS	29	* Register a clock branch.
	30	* Most clock branches have a form like
	31	*
	32	* src1 --\|--\
	33	* \|M \|--[GATE]-[DIV]-
	34	* src2 --\|--/
	35	*
	36	* sometimes without one of those components.
	37	*/
1a4b1819	38	static struct clk rockchip_clk_register_branch(const char name,
03ae1747 HS	39	const char const parent_names, u8 num_parents,
03ae1747 HS	40	void __iomem *base,
a245fecb	41	int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
30d8b7d4	42	u32 *mux_table,
1f55660f	43	int div_offset, u8 div_shift, u8 div_width, u8 div_flags,
a245fecb HS	44	struct clk_div_table *div_table, int gate_offset,
	45	u8 gate_shift, u8 gate_flags, unsigned long flags,
	46	spinlock_t *lock)
	47	{
63207c37	48	struct clk_hw *hw;
a245fecb HS	49	struct clk_mux *mux = NULL;
	50	struct clk_gate *gate = NULL;
	51	struct clk_divider *div = NULL;
	52	const struct clk_ops mux_ops = NULL, div_ops = NULL,
	53	*gate_ops = NULL;
fd3cbbfb	54	int ret;
a245fecb HS	55
	56	if (num_parents > 1) {
	57	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
	58	if (!mux)
	59	return ERR_PTR(-ENOMEM);
	60
	61	mux->reg = base + muxdiv_offset;
	62	mux->shift = mux_shift;
	63	mux->mask = BIT(mux_width) - 1;
	64	mux->flags = mux_flags;
30d8b7d4	65	mux->table = mux_table;
a245fecb HS	66	mux->lock = lock;
	67	mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
	68	: &clk_mux_ops;
	69	}
	70
	71	if (gate_offset >= 0) {
	72	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
fd3cbbfb SL	73	if (!gate) {
fd3cbbfb SL	74	ret = -ENOMEM;
2467b674	75	goto err_gate;
fd3cbbfb	76	}
a245fecb HS	77
	78	gate->flags = gate_flags;
	79	gate->reg = base + gate_offset;
	80	gate->bit_idx = gate_shift;
	81	gate->lock = lock;
	82	gate_ops = &clk_gate_ops;
	83	}
	84
	85	if (div_width > 0) {
	86	div = kzalloc(sizeof(*div), GFP_KERNEL);
fd3cbbfb SL	87	if (!div) {
fd3cbbfb SL	88	ret = -ENOMEM;
2467b674	89	goto err_div;
fd3cbbfb	90	}
a245fecb HS	91
a245fecb HS	92	div->flags = div_flags;
1f55660f FX	93	if (div_offset)
	94	div->reg = base + div_offset;
	95	else
	96	div->reg = base + muxdiv_offset;
a245fecb HS	97	div->shift = div_shift;
	98	div->width = div_width;
	99	div->lock = lock;
	100	div->table = div_table;
50359819 HS	101	div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
	102	? &clk_divider_ro_ops
	103	: &clk_divider_ops;
a245fecb HS	104	}
a245fecb HS	105
63207c37 EZ	106	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
	107	mux ? &mux->hw : NULL, mux_ops,
	108	div ? &div->hw : NULL, div_ops,
	109	gate ? &gate->hw : NULL, gate_ops,
	110	flags);
	111	if (IS_ERR(hw)) {
	112	kfree(div);
	113	kfree(gate);
	114	return ERR_CAST(hw);
fd3cbbfb SL	115	}
fd3cbbfb SL	116
63207c37	117	return hw->clk;
2467b674 SL	118	err_div:
	119	kfree(gate);
	120	err_gate:
	121	kfree(mux);
fd3cbbfb	122	return ERR_PTR(ret);
a245fecb HS	123	}
a245fecb HS	124
8ca1ca8f HS	125	struct rockchip_clk_frac {
	126	struct notifier_block clk_nb;
	127	struct clk_fractional_divider div;
	128	struct clk_gate gate;
	129
	130	struct clk_mux mux;
	131	const struct clk_ops *mux_ops;
	132	int mux_frac_idx;
	133
	134	bool rate_change_remuxed;
	135	int rate_change_idx;
	136	};
	137
	138	#define to_rockchip_clk_frac_nb(nb) \
	139	container_of(nb, struct rockchip_clk_frac, clk_nb)
	140
	141	static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
	142	unsigned long event, void *data)
	143	{
	144	struct clk_notifier_data *ndata = data;
	145	struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb);
	146	struct clk_mux *frac_mux = &frac->mux;
	147	int ret = 0;
	148
	149	pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
	150	__func__, event, ndata->old_rate, ndata->new_rate);
	151	if (event == PRE_RATE_CHANGE) {
03ae1747 HS	152	frac->rate_change_idx =
03ae1747 HS	153	frac->mux_ops->get_parent(&frac_mux->hw);
8ca1ca8f	154	if (frac->rate_change_idx != frac->mux_frac_idx) {
03ae1747 HS	155	frac->mux_ops->set_parent(&frac_mux->hw,
03ae1747 HS	156	frac->mux_frac_idx);
8ca1ca8f HS	157	frac->rate_change_remuxed = 1;
	158	}
	159	} else if (event == POST_RATE_CHANGE) {
	160	/*
	161	* The POST_RATE_CHANGE notifier runs directly after the
	162	* divider clock is set in clk_change_rate, so we'll have
	163	* remuxed back to the original parent before clk_change_rate
	164	* reaches the mux itself.
	165	*/
	166	if (frac->rate_change_remuxed) {
03ae1747 HS	167	frac->mux_ops->set_parent(&frac_mux->hw,
03ae1747 HS	168	frac->rate_change_idx);
8ca1ca8f HS	169	frac->rate_change_remuxed = 0;
	170	}
	171	}
	172
	173	return notifier_from_errno(ret);
	174	}
	175
41517371	176	/*
5d890c2d EZ	177	* fractional divider must set that denominator is 20 times larger than
	178	* numerator to generate precise clock frequency.
	179	*/
1dfcfa72	180	static void rockchip_fractional_approximation(struct clk_hw *hw,
5d890c2d EZ	181	unsigned long rate, unsigned long *parent_rate,
	182	unsigned long m, unsigned long n)
	183	{
10b74af3	184	struct clk_fractional_divider *fd = to_clk_fd(hw);
5d890c2d EZ	185	unsigned long p_rate, p_parent_rate;
5d890c2d EZ	186	struct clk_hw *p_parent;
5d890c2d EZ	187
	188	p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
	189	if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
	190	p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
	191	p_parent_rate = clk_hw_get_rate(p_parent);
	192	*parent_rate = p_parent_rate;
	193	}
	194
10b74af3 QS	195	fd->flags \|= CLK_FRAC_DIVIDER_POWER_OF_TWO_PS;
10b74af3 QS	196
4e7cf74f	197	clk_fractional_divider_general_approximation(hw, rate, parent_rate, m, n);
5d890c2d EZ	198	}
5d890c2d EZ	199
ff94c866 SR	200	static void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
	201	struct clk *clk, unsigned int id)
	202	{
	203	ctx->clk_data.clks[id] = clk;
	204	}
	205
ef1d9fee XZ	206	static struct clk *rockchip_clk_register_frac_branch(
ef1d9fee XZ	207	struct rockchip_clk_provider ctx, const char name,
4a1caed3 UKK	208	const char const parent_names, u8 num_parents,
4a1caed3 UKK	209	void __iomem *base, int muxdiv_offset, u8 div_flags,
b2155a71	210	int gate_offset, u8 gate_shift, u8 gate_flags,
8ca1ca8f HS	211	unsigned long flags, struct rockchip_clk_branch *child,
8ca1ca8f HS	212	spinlock_t *lock)
b2155a71	213	{
63207c37	214	struct clk_hw *hw;
8ca1ca8f	215	struct rockchip_clk_frac *frac;
b2155a71 HS	216	struct clk_gate *gate = NULL;
	217	struct clk_fractional_divider *div = NULL;
	218	const struct clk_ops div_ops = NULL, gate_ops = NULL;
	219
8ca1ca8f HS	220	if (muxdiv_offset < 0)
	221	return ERR_PTR(-EINVAL);
	222
	223	if (child && child->branch_type != branch_mux) {
	224	pr_err("%s: fractional child clock for %s can only be a mux\n",
	225	__func__, name);
	226	return ERR_PTR(-EINVAL);
	227	}
b2155a71	228
8ca1ca8f HS	229	frac = kzalloc(sizeof(*frac), GFP_KERNEL);
	230	if (!frac)
	231	return ERR_PTR(-ENOMEM);
	232
	233	if (gate_offset >= 0) {
	234	gate = &frac->gate;
b2155a71 HS	235	gate->flags = gate_flags;
	236	gate->reg = base + gate_offset;
	237	gate->bit_idx = gate_shift;
	238	gate->lock = lock;
	239	gate_ops = &clk_gate_ops;
	240	}
	241
8ca1ca8f	242	div = &frac->div;
b2155a71 HS	243	div->flags = div_flags;
	244	div->reg = base + muxdiv_offset;
	245	div->mshift = 16;
5d49a6e1	246	div->mwidth = 16;
b2155a71	247	div->nshift = 0;
5d49a6e1	248	div->nwidth = 16;
b2155a71	249	div->lock = lock;
5d890c2d	250	div->approximation = rockchip_fractional_approximation;
b2155a71 HS	251	div_ops = &clk_fractional_divider_ops;
b2155a71 HS	252
63207c37 EZ	253	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
	254	NULL, NULL,
	255	&div->hw, div_ops,
	256	gate ? &gate->hw : NULL, gate_ops,
	257	flags \| CLK_SET_RATE_UNGATE);
	258	if (IS_ERR(hw)) {
8ca1ca8f	259	kfree(frac);
63207c37	260	return ERR_CAST(hw);
8ca1ca8f HS	261	}
	262
	263	if (child) {
	264	struct clk_mux *frac_mux = &frac->mux;
	265	struct clk_init_data init;
	266	struct clk *mux_clk;
a425702f	267	int ret;
8ca1ca8f	268
a425702f YX	269	frac->mux_frac_idx = match_string(child->parent_names,
a425702f YX	270	child->num_parents, name);
8ca1ca8f HS	271	frac->mux_ops = &clk_mux_ops;
	272	frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb;
	273
	274	frac_mux->reg = base + child->muxdiv_offset;
	275	frac_mux->shift = child->mux_shift;
	276	frac_mux->mask = BIT(child->mux_width) - 1;
	277	frac_mux->flags = child->mux_flags;
30d8b7d4 EZ	278	if (child->mux_table)
30d8b7d4 EZ	279	frac_mux->table = child->mux_table;
8ca1ca8f HS	280	frac_mux->lock = lock;
	281	frac_mux->hw.init = &init;
	282
	283	init.name = child->name;
	284	init.flags = child->flags \| CLK_SET_RATE_PARENT;
	285	init.ops = frac->mux_ops;
	286	init.parent_names = child->parent_names;
	287	init.num_parents = child->num_parents;
	288
	289	mux_clk = clk_register(NULL, &frac_mux->hw);
fd3cbbfb SL	290	if (IS_ERR(mux_clk)) {
fd3cbbfb SL	291	kfree(frac);
63207c37	292	return mux_clk;
fd3cbbfb	293	}
8ca1ca8f	294
ef1d9fee	295	rockchip_clk_add_lookup(ctx, mux_clk, child->id);
8ca1ca8f HS	296
	297	/* notifier on the fraction divider to catch rate changes */
	298	if (frac->mux_frac_idx >= 0) {
a425702f YX	299	pr_debug("%s: found fractional parent in mux at pos %d\n",
a425702f YX	300	__func__, frac->mux_frac_idx);
63207c37	301	ret = clk_notifier_register(hw->clk, &frac->clk_nb);
8ca1ca8f HS	302	if (ret)
	303	pr_err("%s: failed to register clock notifier for %s\n",
	304	__func__, name);
	305	} else {
	306	pr_warn("%s: could not find %s as parent of %s, rate changes may not work\n",
	307	__func__, name, child->name);
	308	}
	309	}
b2155a71	310
63207c37	311	return hw->clk;
b2155a71 HS	312	}
b2155a71 HS	313
29a30c26 HS	314	static struct clk rockchip_clk_register_factor_branch(const char name,
	315	const char const parent_names, u8 num_parents,
	316	void __iomem *base, unsigned int mult, unsigned int div,
	317	int gate_offset, u8 gate_shift, u8 gate_flags,
	318	unsigned long flags, spinlock_t *lock)
	319	{
63207c37	320	struct clk_hw *hw;
29a30c26 HS	321	struct clk_gate *gate = NULL;
	322	struct clk_fixed_factor *fix = NULL;
	323
	324	/* without gate, register a simple factor clock */
	325	if (gate_offset == 0) {
	326	return clk_register_fixed_factor(NULL, name,
	327	parent_names[0], flags, mult,
	328	div);
	329	}
	330
	331	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
	332	if (!gate)
	333	return ERR_PTR(-ENOMEM);
	334
	335	gate->flags = gate_flags;
	336	gate->reg = base + gate_offset;
	337	gate->bit_idx = gate_shift;
	338	gate->lock = lock;
	339
	340	fix = kzalloc(sizeof(*fix), GFP_KERNEL);
	341	if (!fix) {
	342	kfree(gate);
	343	return ERR_PTR(-ENOMEM);
	344	}
	345
	346	fix->mult = mult;
	347	fix->div = div;
	348
63207c37 EZ	349	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
	350	NULL, NULL,
	351	&fix->hw, &clk_fixed_factor_ops,
	352	&gate->hw, &clk_gate_ops, flags);
	353	if (IS_ERR(hw)) {
29a30c26 HS	354	kfree(fix);
29a30c26 HS	355	kfree(gate);
63207c37	356	return ERR_CAST(hw);
29a30c26 HS	357	}
29a30c26 HS	358
63207c37	359	return hw->clk;
29a30c26 HS	360	}
29a30c26 HS	361
ea650c26 EZ	362	struct rockchip_clk_provider rockchip_clk_init(struct device_node np,
	363	void __iomem *base,
	364	unsigned long nr_clks)
a245fecb	365	{
ef1d9fee XZ	366	struct rockchip_clk_provider *ctx;
	367	struct clk **clk_table;
	368	int i;
	369
	370	ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL);
03ae1747	371	if (!ctx)
ef1d9fee	372	return ERR_PTR(-ENOMEM);
a245fecb HS	373
a245fecb HS	374	clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
03ae1747	375	if (!clk_table)
ef1d9fee	376	goto err_free;
ef1d9fee XZ	377
	378	for (i = 0; i < nr_clks; ++i)
	379	clk_table[i] = ERR_PTR(-ENOENT);
a245fecb	380
ef1d9fee XZ	381	ctx->reg_base = base;
	382	ctx->clk_data.clks = clk_table;
	383	ctx->clk_data.clk_num = nr_clks;
	384	ctx->cru_node = np;
ef1d9fee XZ	385	spin_lock_init(&ctx->lock);
ef1d9fee XZ	386
6f339dc2 HS	387	ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
	388	"rockchip,grf");
	389
ef1d9fee XZ	390	return ctx;
	391
	392	err_free:
	393	kfree(ctx);
	394	return ERR_PTR(-ENOMEM);
	395	}
ea650c26	396	EXPORT_SYMBOL_GPL(rockchip_clk_init);
ef1d9fee	397
ea650c26 EZ	398	void rockchip_clk_of_add_provider(struct device_node *np,
ea650c26 EZ	399	struct rockchip_clk_provider *ctx)
ef1d9fee	400	{
ff1ae209 SL	401	if (of_clk_add_provider(np, of_clk_src_onecell_get,
	402	&ctx->clk_data))
	403	pr_err("%s: could not register clk provider\n", __func__);
a245fecb	404	}
ea650c26	405	EXPORT_SYMBOL_GPL(rockchip_clk_of_add_provider);
a245fecb	406
ea650c26	407	void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
ef1d9fee	408	struct rockchip_pll_clock *list,
90c59025 HS	409	unsigned int nr_pll, int grf_lock_offset)
	410	{
	411	struct clk *clk;
	412	int idx;
	413
	414	for (idx = 0; idx < nr_pll; idx++, list++) {
ef1d9fee	415	clk = rockchip_clk_register_pll(ctx, list->type, list->name,
90c59025	416	list->parent_names, list->num_parents,
ef1d9fee	417	list->con_offset, grf_lock_offset,
90c59025	418	list->lock_shift, list->mode_offset,
4f8a7c54	419	list->mode_shift, list->rate_table,
e6cebc72	420	list->flags, list->pll_flags);
90c59025 HS	421	if (IS_ERR(clk)) {
	422	pr_err("%s: failed to register clock %s\n", __func__,
	423	list->name);
	424	continue;
	425	}
	426
ef1d9fee	427	rockchip_clk_add_lookup(ctx, clk, list->id);
90c59025 HS	428	}
90c59025 HS	429	}
ea650c26	430	EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);
90c59025	431
ea650c26 EZ	432	void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
	433	struct rockchip_clk_branch *list,
	434	unsigned int nr_clk)
a245fecb HS	435	{
	436	struct clk *clk = NULL;
	437	unsigned int idx;
	438	unsigned long flags;
	439
	440	for (idx = 0; idx < nr_clk; idx++, list++) {
	441	flags = list->flags;
	442
	443	/* catch simple muxes */
	444	switch (list->branch_type) {
	445	case branch_mux:
30d8b7d4 EZ	446	if (list->mux_table)
	447	clk = clk_register_mux_table(NULL, list->name,
	448	list->parent_names, list->num_parents,
	449	flags,
	450	ctx->reg_base + list->muxdiv_offset,
	451	list->mux_shift, list->mux_width,
	452	list->mux_flags, list->mux_table,
	453	&ctx->lock);
	454	else
	455	clk = clk_register_mux(NULL, list->name,
	456	list->parent_names, list->num_parents,
	457	flags,
	458	ctx->reg_base + list->muxdiv_offset,
	459	list->mux_shift, list->mux_width,
	460	list->mux_flags, &ctx->lock);
a245fecb	461	break;
cb1d9f6d HS	462	case branch_muxgrf:
	463	clk = rockchip_clk_register_muxgrf(list->name,
	464	list->parent_names, list->num_parents,
	465	flags, ctx->grf, list->muxdiv_offset,
	466	list->mux_shift, list->mux_width,
	467	list->mux_flags);
	468	break;
a245fecb HS	469	case branch_divider:
	470	if (list->div_table)
	471	clk = clk_register_divider_table(NULL,
	472	list->name, list->parent_names[0],
03ae1747 HS	473	flags,
03ae1747 HS	474	ctx->reg_base + list->muxdiv_offset,
a245fecb HS	475	list->div_shift, list->div_width,
a245fecb HS	476	list->div_flags, list->div_table,
ef1d9fee	477	&ctx->lock);
a245fecb HS	478	else
	479	clk = clk_register_divider(NULL, list->name,
	480	list->parent_names[0], flags,
ef1d9fee	481	ctx->reg_base + list->muxdiv_offset,
a245fecb	482	list->div_shift, list->div_width,
ef1d9fee	483	list->div_flags, &ctx->lock);
a245fecb HS	484	break;
a245fecb HS	485	case branch_fraction_divider:
ef1d9fee	486	clk = rockchip_clk_register_frac_branch(ctx, list->name,
b2155a71	487	list->parent_names, list->num_parents,
03ae1747 HS	488	ctx->reg_base, list->muxdiv_offset,
03ae1747 HS	489	list->div_flags,
b2155a71	490	list->gate_offset, list->gate_shift,
8ca1ca8f	491	list->gate_flags, flags, list->child,
ef1d9fee	492	&ctx->lock);
a245fecb	493	break;
956060a5 EZ	494	case branch_half_divider:
	495	clk = rockchip_clk_register_halfdiv(list->name,
	496	list->parent_names, list->num_parents,
	497	ctx->reg_base, list->muxdiv_offset,
	498	list->mux_shift, list->mux_width,
	499	list->mux_flags, list->div_shift,
	500	list->div_width, list->div_flags,
	501	list->gate_offset, list->gate_shift,
	502	list->gate_flags, flags, &ctx->lock);
	503	break;
a245fecb HS	504	case branch_gate:
	505	flags \|= CLK_SET_RATE_PARENT;
	506
a245fecb HS	507	clk = clk_register_gate(NULL, list->name,
a245fecb HS	508	list->parent_names[0], flags,
ef1d9fee XZ	509	ctx->reg_base + list->gate_offset,
ef1d9fee XZ	510	list->gate_shift, list->gate_flags, &ctx->lock);
a245fecb HS	511	break;
a245fecb HS	512	case branch_composite:
a245fecb HS	513	clk = rockchip_clk_register_branch(list->name,
a245fecb HS	514	list->parent_names, list->num_parents,
03ae1747 HS	515	ctx->reg_base, list->muxdiv_offset,
03ae1747 HS	516	list->mux_shift,
a245fecb	517	list->mux_width, list->mux_flags,
30d8b7d4 EZ	518	list->mux_table, list->div_offset,
30d8b7d4 EZ	519	list->div_shift, list->div_width,
a245fecb HS	520	list->div_flags, list->div_table,
a245fecb HS	521	list->gate_offset, list->gate_shift,
ef1d9fee	522	list->gate_flags, flags, &ctx->lock);
a245fecb	523	break;
89bf26cb AS	524	case branch_mmc:
	525	clk = rockchip_clk_register_mmc(
	526	list->name,
	527	list->parent_names, list->num_parents,
ef1d9fee	528	ctx->reg_base + list->muxdiv_offset,
89bf26cb AS	529	list->div_shift
	530	);
	531	break;
8a76f443 HS	532	case branch_inverter:
	533	clk = rockchip_clk_register_inverter(
	534	list->name, list->parent_names,
	535	list->num_parents,
ef1d9fee XZ	536	ctx->reg_base + list->muxdiv_offset,
ef1d9fee XZ	537	list->div_shift, list->div_flags, &ctx->lock);
8a76f443	538	break;
29a30c26 HS	539	case branch_factor:
	540	clk = rockchip_clk_register_factor_branch(
	541	list->name, list->parent_names,
ef1d9fee	542	list->num_parents, ctx->reg_base,
29a30c26 HS	543	list->div_shift, list->div_width,
29a30c26 HS	544	list->gate_offset, list->gate_shift,
ef1d9fee	545	list->gate_flags, flags, &ctx->lock);
29a30c26	546	break;
a4f182bf LH	547	case branch_ddrclk:
	548	clk = rockchip_clk_register_ddrclk(
	549	list->name, list->flags,
	550	list->parent_names, list->num_parents,
	551	list->muxdiv_offset, list->mux_shift,
	552	list->mux_width, list->div_shift,
	553	list->div_width, list->div_flags,
	554	ctx->reg_base, &ctx->lock);
	555	break;
a245fecb HS	556	}
	557
	558	/* none of the cases above matched */
	559	if (!clk) {
	560	pr_err("%s: unknown clock type %d\n",
	561	__func__, list->branch_type);
	562	continue;
	563	}
	564
	565	if (IS_ERR(clk)) {
	566	pr_err("%s: failed to register clock %s: %ld\n",
	567	__func__, list->name, PTR_ERR(clk));
	568	continue;
	569	}
	570
ef1d9fee	571	rockchip_clk_add_lookup(ctx, clk, list->id);
a245fecb HS	572	}
a245fecb HS	573	}
ea650c26 EZ	574	EXPORT_SYMBOL_GPL(rockchip_clk_register_branches);
	575
	576	void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
	577	unsigned int lookup_id,
	578	const char name, const char const *parent_names,
	579	u8 num_parents,
	580	const struct rockchip_cpuclk_reg_data *reg_data,
	581	const struct rockchip_cpuclk_rate_table *rates,
	582	int nrates)
f6fba5f6 HS	583	{
	584	struct clk *clk;
	585
	586	clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents,
03ae1747 HS	587	reg_data, rates, nrates,
03ae1747 HS	588	ctx->reg_base, &ctx->lock);
f6fba5f6 HS	589	if (IS_ERR(clk)) {
	590	pr_err("%s: failed to register clock %s: %ld\n",
	591	__func__, name, PTR_ERR(clk));
	592	return;
	593	}
	594
ef1d9fee	595	rockchip_clk_add_lookup(ctx, clk, lookup_id);
f6fba5f6	596	}
ea650c26	597	EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk);
f6fba5f6	598
ea650c26 EZ	599	void rockchip_clk_protect_critical(const char *const clocks[],
ea650c26 EZ	600	int nclocks)
fe94f974 HS	601	{
	602	int i;
	603
	604	/* Protect the clocks that needs to stay on */
	605	for (i = 0; i < nclocks; i++) {
	606	struct clk *clk = __clk_lookup(clocks[i]);
	607
7f5b57a0	608	clk_prepare_enable(clk);
fe94f974 HS	609	}
fe94f974 HS	610	}
ea650c26	611	EXPORT_SYMBOL_GPL(rockchip_clk_protect_critical);
6f1294b5	612
ef1d9fee	613	static void __iomem *rst_base;
6f1294b5	614	static unsigned int reg_restart;
dfff24bd	615	static void (*cb_restart)(void);
6f1294b5 HS	616	static int rockchip_restart_notify(struct notifier_block *this,
	617	unsigned long mode, void *cmd)
	618	{
dfff24bd HS	619	if (cb_restart)
	620	cb_restart();
	621
ef1d9fee	622	writel(0xfdb9, rst_base + reg_restart);
6f1294b5 HS	623	return NOTIFY_DONE;
	624	}
	625
	626	static struct notifier_block rockchip_restart_handler = {
	627	.notifier_call = rockchip_restart_notify,
	628	.priority = 128,
	629	};
	630
ea650c26	631	void
03ae1747	632	rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
ea650c26 EZ	633	unsigned int reg,
ea650c26 EZ	634	void (*cb)(void))
6f1294b5 HS	635	{
	636	int ret;
	637
ef1d9fee	638	rst_base = ctx->reg_base;
6f1294b5	639	reg_restart = reg;
dfff24bd	640	cb_restart = cb;
6f1294b5 HS	641	ret = register_restart_handler(&rockchip_restart_handler);
	642	if (ret)
	643	pr_err("%s: cannot register restart handler, %d\n",
	644	__func__, ret);
	645	}
ea650c26	646	EXPORT_SYMBOL_GPL(rockchip_register_restart_notifier);