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307a2e9a JC |
1 | /* |
2 | * Copyright (c) 2015 Rockchip Electronics Co. Ltd. | |
3 | * Author: Xing Zheng <zhengxing@rock-chips.com> | |
4 | * Jeffy Chen <jeffy.chen@rock-chips.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/clk-provider.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/of_address.h> | |
20 | #include <linux/syscore_ops.h> | |
21 | #include <dt-bindings/clock/rk3228-cru.h> | |
22 | #include "clk.h" | |
23 | ||
24 | #define RK3228_GRF_SOC_STATUS0 0x480 | |
25 | ||
26 | enum rk3228_plls { | |
27 | apll, dpll, cpll, gpll, | |
28 | }; | |
29 | ||
30 | static struct rockchip_pll_rate_table rk3228_pll_rates[] = { | |
31 | /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ | |
32 | RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), | |
33 | RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), | |
34 | RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), | |
35 | RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), | |
36 | RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), | |
37 | RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), | |
38 | RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), | |
39 | RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), | |
40 | RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), | |
41 | RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), | |
42 | RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), | |
43 | RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), | |
44 | RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), | |
45 | RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), | |
46 | RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), | |
47 | RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), | |
48 | RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), | |
49 | RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), | |
50 | RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), | |
51 | RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), | |
52 | RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), | |
53 | RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), | |
54 | RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), | |
55 | RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), | |
56 | RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), | |
57 | RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), | |
58 | RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), | |
59 | RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), | |
60 | RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), | |
61 | RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), | |
62 | RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), | |
63 | RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), | |
64 | RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), | |
65 | RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), | |
66 | RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), | |
67 | RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), | |
68 | RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), | |
69 | RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), | |
70 | RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), | |
71 | RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), | |
72 | RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), | |
73 | RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), | |
74 | { /* sentinel */ }, | |
75 | }; | |
76 | ||
77 | #define RK3228_DIV_CPU_MASK 0x1f | |
78 | #define RK3228_DIV_CPU_SHIFT 8 | |
79 | ||
80 | #define RK3228_DIV_PERI_MASK 0xf | |
81 | #define RK3228_DIV_PERI_SHIFT 0 | |
82 | #define RK3228_DIV_ACLK_MASK 0x7 | |
83 | #define RK3228_DIV_ACLK_SHIFT 4 | |
84 | #define RK3228_DIV_HCLK_MASK 0x3 | |
85 | #define RK3228_DIV_HCLK_SHIFT 8 | |
86 | #define RK3228_DIV_PCLK_MASK 0x7 | |
87 | #define RK3228_DIV_PCLK_SHIFT 12 | |
88 | ||
89 | #define RK3228_CLKSEL1(_core_peri_div) \ | |
90 | { \ | |
91 | .reg = RK2928_CLKSEL_CON(1), \ | |
92 | .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \ | |
93 | RK3228_DIV_PERI_SHIFT) \ | |
94 | } | |
95 | ||
96 | #define RK3228_CPUCLK_RATE(_prate, _core_peri_div) \ | |
97 | { \ | |
98 | .prate = _prate, \ | |
99 | .divs = { \ | |
100 | RK3228_CLKSEL1(_core_peri_div), \ | |
101 | }, \ | |
102 | } | |
103 | ||
104 | static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = { | |
105 | RK3228_CPUCLK_RATE(816000000, 4), | |
106 | RK3228_CPUCLK_RATE(600000000, 4), | |
107 | RK3228_CPUCLK_RATE(312000000, 4), | |
108 | }; | |
109 | ||
110 | static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = { | |
111 | .core_reg = RK2928_CLKSEL_CON(0), | |
112 | .div_core_shift = 0, | |
113 | .div_core_mask = 0x1f, | |
268aebaa XZ |
114 | .mux_core_alt = 1, |
115 | .mux_core_main = 0, | |
307a2e9a | 116 | .mux_core_shift = 6, |
268aebaa | 117 | .mux_core_mask = 0x1, |
307a2e9a JC |
118 | }; |
119 | ||
120 | PNAME(mux_pll_p) = { "clk_24m", "xin24m" }; | |
121 | ||
122 | PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" }; | |
123 | PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" }; | |
124 | PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" }; | |
125 | PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" }; | |
126 | PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" }; | |
127 | PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" }; | |
128 | ||
129 | PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" }; | |
130 | PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" }; | |
131 | PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" }; | |
132 | PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" }; | |
133 | PNAME(mux_aclk_peri_src_p) = { "cpll_peri", "gpll_peri", "hdmiphy_peri" }; | |
134 | PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" }; | |
135 | PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" }; | |
136 | ||
137 | PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" }; | |
138 | ||
139 | PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" }; | |
140 | PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" }; | |
141 | ||
142 | PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; | |
143 | PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" }; | |
144 | PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" }; | |
145 | PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" }; | |
146 | PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" }; | |
147 | ||
148 | PNAME(mux_aclk_gpu_pre_p) = { "cpll_gpu", "gpll_gpu", "hdmiphy_gpu", "usb480m_gpu" }; | |
149 | ||
150 | PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; | |
151 | PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; | |
152 | PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; | |
153 | ||
154 | PNAME(mux_sclk_macphy_50m_p) = { "ext_gmac", "phy_50m_out" }; | |
155 | PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_macphy_50m" }; | |
156 | PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" }; | |
157 | ||
158 | static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = { | |
159 | [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), | |
160 | RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates), | |
161 | [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3), | |
162 | RK2928_MODE_CON, 4, 6, 0, NULL), | |
163 | [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6), | |
164 | RK2928_MODE_CON, 8, 8, 0, NULL), | |
165 | [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9), | |
166 | RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates), | |
167 | }; | |
168 | ||
169 | #define MFLAGS CLK_MUX_HIWORD_MASK | |
170 | #define DFLAGS CLK_DIVIDER_HIWORD_MASK | |
171 | #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) | |
172 | ||
173 | static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { | |
174 | /* | |
175 | * Clock-Architecture Diagram 1 | |
176 | */ | |
177 | ||
178 | DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, | |
179 | RK2928_CLKSEL_CON(4), 8, 5, DFLAGS), | |
180 | ||
181 | /* PD_DDR */ | |
182 | GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED, | |
183 | RK2928_CLKGATE_CON(0), 2, GFLAGS), | |
184 | GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, | |
185 | RK2928_CLKGATE_CON(0), 2, GFLAGS), | |
186 | GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, | |
187 | RK2928_CLKGATE_CON(0), 2, GFLAGS), | |
188 | COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, | |
189 | RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, | |
190 | RK2928_CLKGATE_CON(7), 1, GFLAGS), | |
191 | GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED, | |
192 | RK2928_CLKGATE_CON(8), 5, GFLAGS), | |
36714529 | 193 | FACTOR_GATE(0, "ddrphy", "ddrphy4x", CLK_IGNORE_UNUSED, 1, 4, |
307a2e9a JC |
194 | RK2928_CLKGATE_CON(7), 0, GFLAGS), |
195 | ||
196 | /* PD_CORE */ | |
197 | GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, | |
198 | RK2928_CLKGATE_CON(0), 6, GFLAGS), | |
199 | GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, | |
200 | RK2928_CLKGATE_CON(0), 6, GFLAGS), | |
201 | GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, | |
202 | RK2928_CLKGATE_CON(0), 6, GFLAGS), | |
203 | COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, | |
204 | RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, | |
205 | RK2928_CLKGATE_CON(4), 1, GFLAGS), | |
206 | COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED, | |
207 | RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, | |
208 | RK2928_CLKGATE_CON(4), 0, GFLAGS), | |
209 | ||
210 | /* PD_MISC */ | |
211 | MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT, | |
212 | RK2928_MISC_CON, 13, 1, MFLAGS), | |
213 | MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT, | |
214 | RK2928_MISC_CON, 14, 1, MFLAGS), | |
215 | MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, | |
216 | RK2928_MISC_CON, 15, 1, MFLAGS), | |
217 | ||
218 | /* PD_BUS */ | |
219 | GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED, | |
220 | RK2928_CLKGATE_CON(0), 1, GFLAGS), | |
221 | GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED, | |
222 | RK2928_CLKGATE_CON(0), 1, GFLAGS), | |
223 | GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED, | |
224 | RK2928_CLKGATE_CON(0), 1, GFLAGS), | |
225 | COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0, | |
226 | RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS), | |
227 | GATE(ARMCLK, "aclk_cpu", "aclk_cpu_src", 0, | |
228 | RK2928_CLKGATE_CON(6), 0, GFLAGS), | |
229 | COMPOSITE_NOMUX(0, "hclk_cpu", "aclk_cpu_src", 0, | |
230 | RK2928_CLKSEL_CON(1), 8, 2, DFLAGS, | |
231 | RK2928_CLKGATE_CON(6), 1, GFLAGS), | |
232 | COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0, | |
233 | RK2928_CLKSEL_CON(1), 12, 3, DFLAGS, | |
234 | RK2928_CLKGATE_CON(6), 2, GFLAGS), | |
235 | GATE(0, "pclk_cpu", "pclk_bus_src", 0, | |
236 | RK2928_CLKGATE_CON(6), 3, GFLAGS), | |
237 | GATE(0, "pclk_phy_pre", "pclk_bus_src", 0, | |
238 | RK2928_CLKGATE_CON(6), 4, GFLAGS), | |
239 | GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0, | |
240 | RK2928_CLKGATE_CON(6), 13, GFLAGS), | |
241 | ||
242 | /* PD_VIDEO */ | |
243 | COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0, | |
244 | RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS, | |
245 | RK2928_CLKGATE_CON(3), 11, GFLAGS), | |
36714529 | 246 | FACTOR_GATE(0, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4, |
307a2e9a JC |
247 | RK2928_CLKGATE_CON(4), 4, GFLAGS), |
248 | ||
249 | COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0, | |
250 | RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS, | |
251 | RK2928_CLKGATE_CON(3), 2, GFLAGS), | |
36714529 | 252 | FACTOR_GATE(0, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4, |
307a2e9a JC |
253 | RK2928_CLKGATE_CON(4), 5, GFLAGS), |
254 | ||
255 | COMPOSITE(0, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0, | |
256 | RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS, | |
257 | RK2928_CLKGATE_CON(3), 3, GFLAGS), | |
258 | ||
259 | COMPOSITE(0, "sclk_vdec_core", mux_pll_src_4plls_p, 0, | |
260 | RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, 8, 5, DFLAGS, | |
261 | RK2928_CLKGATE_CON(3), 4, GFLAGS), | |
262 | ||
263 | /* PD_VIO */ | |
264 | COMPOSITE(0, "aclk_iep_pre", mux_pll_src_4plls_p, 0, | |
265 | RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, 0, 5, DFLAGS, | |
266 | RK2928_CLKGATE_CON(3), 0, GFLAGS), | |
267 | DIV(0, "hclk_vio_pre", "aclk_iep_pre", 0, | |
268 | RK2928_CLKSEL_CON(2), 0, 5, DFLAGS), | |
269 | ||
270 | COMPOSITE(0, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0, | |
271 | RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, 8, 5, DFLAGS, | |
272 | RK2928_CLKGATE_CON(1), 4, GFLAGS), | |
273 | ||
274 | MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0, | |
275 | RK2928_CLKSEL_CON(33), 13, 2, MFLAGS), | |
276 | COMPOSITE_NOMUX(0, "aclk_rga_pre", "sclk_rga_src", 0, | |
277 | RK2928_CLKSEL_CON(33), 8, 5, DFLAGS, | |
278 | RK2928_CLKGATE_CON(1), 2, GFLAGS), | |
279 | COMPOSITE(0, "sclk_rga", mux_sclk_rga_p, 0, | |
280 | RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, 0, 5, DFLAGS, | |
281 | RK2928_CLKGATE_CON(3), 6, GFLAGS), | |
282 | ||
283 | COMPOSITE(0, "aclk_vop_pre", mux_pll_src_4plls_p, 0, | |
284 | RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, 0, 5, DFLAGS, | |
285 | RK2928_CLKGATE_CON(1), 1, GFLAGS), | |
286 | ||
287 | COMPOSITE(0, "sclk_hdcp", mux_pll_src_3plls_p, 0, | |
288 | RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 6, DFLAGS, | |
289 | RK2928_CLKGATE_CON(3), 5, GFLAGS), | |
290 | ||
bdc7deec | 291 | GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0, |
307a2e9a JC |
292 | RK2928_CLKGATE_CON(3), 7, GFLAGS), |
293 | ||
294 | COMPOSITE(0, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0, | |
295 | RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, 0, 14, DFLAGS, | |
296 | RK2928_CLKGATE_CON(3), 8, GFLAGS), | |
297 | ||
298 | /* PD_PERI */ | |
299 | GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED, | |
300 | RK2928_CLKGATE_CON(2), 0, GFLAGS), | |
301 | GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED, | |
302 | RK2928_CLKGATE_CON(2), 0, GFLAGS), | |
303 | GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED, | |
304 | RK2928_CLKGATE_CON(2), 0, GFLAGS), | |
305 | COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0, | |
306 | RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS), | |
307 | COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0, | |
308 | RK2928_CLKSEL_CON(10), 12, 3, DFLAGS, | |
309 | RK2928_CLKGATE_CON(5), 2, GFLAGS), | |
310 | COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0, | |
311 | RK2928_CLKSEL_CON(10), 8, 2, DFLAGS, | |
312 | RK2928_CLKGATE_CON(5), 1, GFLAGS), | |
313 | GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, | |
314 | RK2928_CLKGATE_CON(5), 0, GFLAGS), | |
315 | ||
316 | GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, | |
317 | RK2928_CLKGATE_CON(6), 5, GFLAGS), | |
318 | GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, | |
319 | RK2928_CLKGATE_CON(6), 6, GFLAGS), | |
320 | GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, | |
321 | RK2928_CLKGATE_CON(6), 7, GFLAGS), | |
322 | GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, | |
323 | RK2928_CLKGATE_CON(6), 8, GFLAGS), | |
324 | GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, | |
325 | RK2928_CLKGATE_CON(6), 9, GFLAGS), | |
326 | GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, | |
327 | RK2928_CLKGATE_CON(6), 10, GFLAGS), | |
328 | ||
329 | COMPOSITE(0, "sclk_crypto", mux_pll_src_2plls_p, 0, | |
330 | RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, 0, 5, DFLAGS, | |
331 | RK2928_CLKGATE_CON(2), 7, GFLAGS), | |
332 | ||
333 | COMPOSITE(0, "sclk_tsp", mux_pll_src_2plls_p, 0, | |
334 | RK2928_CLKSEL_CON(22), 15, 1, MFLAGS, 8, 5, DFLAGS, | |
335 | RK2928_CLKGATE_CON(2), 6, GFLAGS), | |
336 | ||
337 | GATE(0, "sclk_hsadc", "ext_hsadc", 0, | |
338 | RK3288_CLKGATE_CON(10), 12, GFLAGS), | |
339 | ||
340 | COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0, | |
341 | RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS, | |
342 | RK2928_CLKGATE_CON(2), 15, GFLAGS), | |
343 | ||
344 | COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, | |
345 | RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS, | |
346 | RK2928_CLKGATE_CON(2), 11, GFLAGS), | |
347 | ||
348 | COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, | |
349 | RK2928_CLKSEL_CON(11), 10, 2, MFLAGS, | |
350 | RK2928_CLKGATE_CON(2), 13, GFLAGS), | |
351 | DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, | |
352 | RK2928_CLKSEL_CON(12), 0, 8, DFLAGS), | |
353 | ||
354 | COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0, | |
355 | RK2928_CLKSEL_CON(11), 12, 2, MFLAGS, | |
356 | RK2928_CLKGATE_CON(2), 14, GFLAGS), | |
357 | DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, | |
358 | RK2928_CLKSEL_CON(12), 8, 8, DFLAGS), | |
359 | ||
360 | /* | |
361 | * Clock-Architecture Diagram 2 | |
362 | */ | |
363 | ||
364 | GATE(0, "gpll_vop", "gpll", 0, | |
365 | RK2928_CLKGATE_CON(3), 1, GFLAGS), | |
366 | GATE(0, "cpll_vop", "cpll", 0, | |
367 | RK2928_CLKGATE_CON(3), 1, GFLAGS), | |
368 | MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0, | |
369 | RK2928_CLKSEL_CON(27), 0, 1, MFLAGS), | |
bdc7deec | 370 | DIV(DCLK_HDMI_PHY, "dclk_hdmiphy", "sclk_vop_src", 0, |
307a2e9a JC |
371 | RK2928_CLKSEL_CON(29), 0, 3, DFLAGS), |
372 | DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, | |
373 | RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), | |
0a9d4ac0 | 374 | MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0, |
307a2e9a JC |
375 | RK2928_CLKSEL_CON(27), 1, 1, MFLAGS), |
376 | ||
36714529 HS |
377 | FACTOR(0, "xin12m", "xin24m", 0, 1, 2), |
378 | ||
307a2e9a JC |
379 | COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0, |
380 | RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS, | |
381 | RK2928_CLKGATE_CON(0), 3, GFLAGS), | |
382 | COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, | |
383 | RK3288_CLKSEL_CON(8), 0, | |
384 | RK3288_CLKGATE_CON(0), 4, GFLAGS), | |
385 | COMPOSITE_NODIV(SCLK_I2S0, "sclk_i2s0", mux_i2s0_p, 0, | |
386 | RK2928_CLKSEL_CON(9), 8, 2, MFLAGS, | |
387 | RK2928_CLKGATE_CON(0), 5, GFLAGS), | |
388 | ||
389 | COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0, | |
390 | RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS, | |
391 | RK2928_CLKGATE_CON(0), 10, GFLAGS), | |
392 | COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, | |
393 | RK3288_CLKSEL_CON(7), 0, | |
394 | RK3288_CLKGATE_CON(0), 11, GFLAGS), | |
395 | MUX(0, "i2s1_pre", mux_i2s1_pre_p, 0, | |
396 | RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), | |
397 | GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", 0, | |
398 | RK2928_CLKGATE_CON(0), 14, GFLAGS), | |
399 | COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0, | |
400 | RK2928_CLKSEL_CON(3), 12, 1, MFLAGS, | |
401 | RK2928_CLKGATE_CON(0), 13, GFLAGS), | |
402 | ||
403 | COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0, | |
404 | RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS, | |
405 | RK2928_CLKGATE_CON(0), 7, GFLAGS), | |
406 | COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, | |
407 | RK3288_CLKSEL_CON(30), 0, | |
408 | RK3288_CLKGATE_CON(0), 8, GFLAGS), | |
409 | COMPOSITE_NODIV(SCLK_I2S2, "sclk_i2s2", mux_i2s2_p, 0, | |
410 | RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, | |
411 | RK2928_CLKGATE_CON(0), 9, GFLAGS), | |
412 | ||
413 | COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0, | |
414 | RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS, | |
415 | RK2928_CLKGATE_CON(2), 10, GFLAGS), | |
416 | COMPOSITE_FRAC(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT, | |
417 | RK3288_CLKSEL_CON(20), 0, | |
418 | RK3288_CLKGATE_CON(2), 12, GFLAGS), | |
419 | MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0, | |
420 | RK2928_CLKSEL_CON(6), 8, 2, MFLAGS), | |
421 | ||
422 | GATE(0, "jtag", "ext_jtag", 0, | |
423 | RK2928_CLKGATE_CON(1), 3, GFLAGS), | |
424 | ||
425 | GATE(0, "sclk_otgphy0", "xin24m", 0, | |
426 | RK2928_CLKGATE_CON(1), 5, GFLAGS), | |
427 | GATE(0, "sclk_otgphy1", "xin24m", 0, | |
428 | RK2928_CLKGATE_CON(1), 6, GFLAGS), | |
429 | ||
a3cb9aa4 | 430 | COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0, |
307a2e9a JC |
431 | RK2928_CLKSEL_CON(24), 6, 10, DFLAGS, |
432 | RK2928_CLKGATE_CON(2), 8, GFLAGS), | |
433 | ||
434 | GATE(0, "cpll_gpu", "cpll", 0, | |
435 | RK2928_CLKGATE_CON(3), 13, GFLAGS), | |
436 | GATE(0, "gpll_gpu", "gpll", 0, | |
437 | RK2928_CLKGATE_CON(3), 13, GFLAGS), | |
438 | GATE(0, "hdmiphy_gpu", "hdmiphy", 0, | |
439 | RK2928_CLKGATE_CON(3), 13, GFLAGS), | |
440 | GATE(0, "usb480m_gpu", "usb480m", 0, | |
441 | RK2928_CLKGATE_CON(3), 13, GFLAGS), | |
442 | COMPOSITE_NOGATE(0, "aclk_gpu_pre", mux_aclk_gpu_pre_p, 0, | |
443 | RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS), | |
444 | ||
445 | COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0, | |
446 | RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS, | |
447 | RK2928_CLKGATE_CON(2), 9, GFLAGS), | |
448 | ||
449 | /* PD_UART */ | |
450 | COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0, | |
451 | RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS, | |
452 | RK2928_CLKGATE_CON(1), 8, GFLAGS), | |
453 | COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0, | |
454 | RK2928_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS, | |
455 | RK2928_CLKGATE_CON(1), 10, GFLAGS), | |
456 | COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p, | |
457 | 0, RK2928_CLKSEL_CON(15), 12, 2, | |
458 | MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS), | |
459 | COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, | |
460 | RK2928_CLKSEL_CON(17), 0, | |
461 | RK2928_CLKGATE_CON(1), 9, GFLAGS), | |
462 | COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, | |
463 | RK2928_CLKSEL_CON(18), 0, | |
464 | RK2928_CLKGATE_CON(1), 11, GFLAGS), | |
465 | COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, | |
466 | RK2928_CLKSEL_CON(19), 0, | |
467 | RK2928_CLKGATE_CON(1), 13, GFLAGS), | |
468 | MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, | |
469 | RK2928_CLKSEL_CON(13), 8, 2, MFLAGS), | |
470 | MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, | |
471 | RK2928_CLKSEL_CON(14), 8, 2, MFLAGS), | |
472 | MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, | |
473 | RK2928_CLKSEL_CON(15), 8, 2, MFLAGS), | |
474 | ||
475 | COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, | |
476 | RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS, | |
477 | RK2928_CLKGATE_CON(1), 0, GFLAGS), | |
478 | ||
479 | COMPOSITE(0, "sclk_gmac_src", mux_pll_src_2plls_p, 0, | |
480 | RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 5, DFLAGS, | |
481 | RK2928_CLKGATE_CON(1), 7, GFLAGS), | |
482 | MUX(0, "sclk_macphy_50m", mux_sclk_macphy_50m_p, 0, | |
483 | RK2928_CLKSEL_CON(29), 10, 1, MFLAGS), | |
484 | MUX(0, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0, | |
485 | RK2928_CLKSEL_CON(5), 5, 1, MFLAGS), | |
486 | GATE(0, "sclk_mac_refout", "sclk_gmac_pre", 0, | |
487 | RK2928_CLKGATE_CON(5), 4, GFLAGS), | |
488 | GATE(0, "sclk_mac_ref", "sclk_gmac_pre", 0, | |
489 | RK2928_CLKGATE_CON(5), 3, GFLAGS), | |
490 | GATE(0, "sclk_mac_rx", "sclk_gmac_pre", 0, | |
491 | RK2928_CLKGATE_CON(5), 5, GFLAGS), | |
492 | GATE(0, "sclk_mac_tx", "sclk_gmac_pre", 0, | |
493 | RK2928_CLKGATE_CON(5), 6, GFLAGS), | |
494 | COMPOSITE(0, "sclk_macphy", mux_sclk_macphy_p, 0, | |
495 | RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, 8, 2, DFLAGS, | |
496 | RK2928_CLKGATE_CON(5), 7, GFLAGS), | |
497 | COMPOSITE(0, "sclk_gmac_out", mux_pll_src_2plls_p, 0, | |
498 | RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS, | |
499 | RK2928_CLKGATE_CON(2), 2, GFLAGS), | |
500 | ||
501 | /* | |
502 | * Clock-Architecture Diagram 3 | |
503 | */ | |
504 | ||
505 | /* PD_VOP */ | |
506 | GATE(0, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS), | |
507 | GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS), | |
508 | GATE(0, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS), | |
509 | GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS), | |
510 | ||
0a9d4ac0 | 511 | GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS), |
307a2e9a JC |
512 | GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS), |
513 | ||
514 | GATE(0, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS), | |
515 | GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS), | |
516 | ||
517 | GATE(0, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS), | |
518 | GATE(0, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS), | |
0a9d4ac0 | 519 | GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS), |
307a2e9a JC |
520 | GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS), |
521 | GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS), | |
522 | GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS), | |
523 | GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS), | |
524 | GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS), | |
bdc7deec | 525 | GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS), |
307a2e9a JC |
526 | GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS), |
527 | GATE(0, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS), | |
528 | ||
529 | /* PD_PERI */ | |
530 | GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 0, GFLAGS), | |
531 | GATE(0, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4, GFLAGS), | |
532 | ||
533 | GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 0, GFLAGS), | |
534 | GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1, GFLAGS), | |
535 | GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS), | |
536 | GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS), | |
537 | GATE(0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS), | |
538 | GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS), | |
539 | GATE(0, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS), | |
540 | GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS), | |
541 | GATE(0, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS), | |
542 | GATE(0, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS), | |
543 | GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS), | |
544 | GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS), | |
545 | GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS), | |
546 | ||
547 | GATE(0, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS), | |
548 | GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS), | |
549 | ||
550 | /* PD_GPU */ | |
551 | GATE(0, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS), | |
552 | GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 15, GFLAGS), | |
553 | ||
554 | /* PD_BUS */ | |
555 | GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), | |
556 | GATE(0, "aclk_initmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), | |
557 | GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS), | |
558 | GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS), | |
559 | ||
560 | GATE(0, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS), | |
561 | GATE(0, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS), | |
562 | GATE(0, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS), | |
563 | GATE(0, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS), | |
564 | GATE(0, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS), | |
565 | GATE(0, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS), | |
566 | GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS), | |
567 | GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS), | |
568 | ||
569 | GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS), | |
570 | GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS), | |
571 | GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS), | |
572 | ||
573 | GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS), | |
574 | GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS), | |
575 | GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS), | |
576 | GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS), | |
577 | GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS), | |
578 | GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS), | |
579 | GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 4, GFLAGS), | |
580 | GATE(0, "pclk_stimer", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS), | |
581 | GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS), | |
582 | GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS), | |
583 | GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS), | |
584 | GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS), | |
585 | GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 10, GFLAGS), | |
586 | GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 11, GFLAGS), | |
587 | GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS), | |
588 | GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 13, GFLAGS), | |
589 | GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 14, GFLAGS), | |
a3cb9aa4 | 590 | GATE(PCLK_TSADC, "pclk_tsadc", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 15, GFLAGS), |
307a2e9a JC |
591 | GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 0, GFLAGS), |
592 | GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS), | |
593 | GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS), | |
594 | GATE(0, "pclk_sim", "pclk_cpu", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS), | |
595 | ||
596 | GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS), | |
597 | GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS), | |
bdc7deec | 598 | GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS), |
307a2e9a JC |
599 | GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS), |
600 | GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS), | |
601 | ||
602 | GATE(0, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS), | |
603 | GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS), | |
604 | GATE(0, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS), | |
605 | GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS), | |
606 | GATE(0, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS), | |
607 | GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS), | |
608 | GATE(0, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS), | |
609 | GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS), | |
610 | ||
611 | /* PD_MMC */ | |
612 | MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1), | |
bb07698f | 613 | MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0), |
307a2e9a JC |
614 | |
615 | MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1), | |
bb07698f | 616 | MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 0), |
307a2e9a JC |
617 | |
618 | MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1), | |
bb07698f | 619 | MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0), |
307a2e9a JC |
620 | }; |
621 | ||
622 | static const char *const rk3228_critical_clocks[] __initconst = { | |
623 | "aclk_cpu", | |
624 | "aclk_peri", | |
625 | "hclk_peri", | |
626 | "pclk_peri", | |
627 | }; | |
628 | ||
629 | static void __init rk3228_clk_init(struct device_node *np) | |
630 | { | |
ef1d9fee | 631 | struct rockchip_clk_provider *ctx; |
307a2e9a | 632 | void __iomem *reg_base; |
307a2e9a JC |
633 | |
634 | reg_base = of_iomap(np, 0); | |
635 | if (!reg_base) { | |
636 | pr_err("%s: could not map cru region\n", __func__); | |
637 | return; | |
638 | } | |
639 | ||
ef1d9fee XZ |
640 | ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); |
641 | if (IS_ERR(ctx)) { | |
642 | pr_err("%s: rockchip clk init failed\n", __func__); | |
1d003eb0 | 643 | iounmap(reg_base); |
ef1d9fee XZ |
644 | return; |
645 | } | |
307a2e9a | 646 | |
ef1d9fee | 647 | rockchip_clk_register_plls(ctx, rk3228_pll_clks, |
307a2e9a JC |
648 | ARRAY_SIZE(rk3228_pll_clks), |
649 | RK3228_GRF_SOC_STATUS0); | |
ef1d9fee | 650 | rockchip_clk_register_branches(ctx, rk3228_clk_branches, |
307a2e9a JC |
651 | ARRAY_SIZE(rk3228_clk_branches)); |
652 | rockchip_clk_protect_critical(rk3228_critical_clocks, | |
653 | ARRAY_SIZE(rk3228_critical_clocks)); | |
654 | ||
ef1d9fee | 655 | rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", |
307a2e9a JC |
656 | mux_armclk_p, ARRAY_SIZE(mux_armclk_p), |
657 | &rk3228_cpuclk_data, rk3228_cpuclk_rates, | |
658 | ARRAY_SIZE(rk3228_cpuclk_rates)); | |
659 | ||
660 | rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), | |
661 | ROCKCHIP_SOFTRST_HIWORD_MASK); | |
662 | ||
ef1d9fee XZ |
663 | rockchip_register_restart_notifier(ctx, RK3228_GLB_SRST_FST, NULL); |
664 | ||
665 | rockchip_clk_of_add_provider(np, ctx); | |
307a2e9a JC |
666 | } |
667 | CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init); |