Commit | Line | Data |
---|---|---|
f6022e88 EZ |
1 | /* |
2 | * Copyright (c) 2017 Rockchip Electronics Co. Ltd. | |
3 | * Author: Elaine <zhangqing@rock-chips.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/clk-provider.h> | |
17 | #include <linux/of.h> | |
18 | #include <linux/of_address.h> | |
19 | #include <linux/syscore_ops.h> | |
20 | #include <dt-bindings/clock/rk3128-cru.h> | |
21 | #include "clk.h" | |
22 | ||
23 | #define RK3128_GRF_SOC_STATUS0 0x14c | |
24 | ||
25 | enum rk3128_plls { | |
26 | apll, dpll, cpll, gpll, | |
27 | }; | |
28 | ||
29 | static struct rockchip_pll_rate_table rk3128_pll_rates[] = { | |
30 | /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ | |
31 | RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), | |
32 | RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), | |
33 | RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), | |
34 | RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), | |
35 | RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), | |
36 | RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), | |
37 | RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), | |
38 | RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), | |
39 | RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), | |
40 | RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), | |
41 | RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), | |
42 | RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), | |
43 | RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), | |
44 | RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), | |
45 | RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), | |
46 | RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), | |
47 | RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), | |
48 | RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), | |
49 | RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), | |
50 | RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), | |
51 | RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), | |
52 | RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), | |
53 | RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0), | |
54 | RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0), | |
55 | RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0), | |
56 | RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), | |
57 | RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0), | |
58 | RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0), | |
59 | RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0), | |
60 | RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0), | |
61 | RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), | |
62 | RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0), | |
63 | RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0), | |
64 | RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0), | |
65 | RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0), | |
66 | RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), | |
67 | RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0), | |
68 | RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0), | |
69 | RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), | |
70 | RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0), | |
71 | RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), | |
72 | RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0), | |
73 | { /* sentinel */ }, | |
74 | }; | |
75 | ||
76 | #define RK3128_DIV_CPU_MASK 0x1f | |
77 | #define RK3128_DIV_CPU_SHIFT 8 | |
78 | ||
79 | #define RK3128_DIV_PERI_MASK 0xf | |
80 | #define RK3128_DIV_PERI_SHIFT 0 | |
81 | #define RK3128_DIV_ACLK_MASK 0x7 | |
82 | #define RK3128_DIV_ACLK_SHIFT 4 | |
83 | #define RK3128_DIV_HCLK_MASK 0x3 | |
84 | #define RK3128_DIV_HCLK_SHIFT 8 | |
85 | #define RK3128_DIV_PCLK_MASK 0x7 | |
86 | #define RK3128_DIV_PCLK_SHIFT 12 | |
87 | ||
88 | #define RK3128_CLKSEL1(_core_aclk_div, _pclk_dbg_div) \ | |
89 | { \ | |
90 | .reg = RK2928_CLKSEL_CON(1), \ | |
91 | .val = HIWORD_UPDATE(_pclk_dbg_div, RK3128_DIV_PERI_MASK, \ | |
92 | RK3128_DIV_PERI_SHIFT) | \ | |
93 | HIWORD_UPDATE(_core_aclk_div, RK3128_DIV_ACLK_MASK, \ | |
94 | RK3128_DIV_ACLK_SHIFT), \ | |
95 | } | |
96 | ||
97 | #define RK3128_CPUCLK_RATE(_prate, _core_aclk_div, _pclk_dbg_div) \ | |
98 | { \ | |
99 | .prate = _prate, \ | |
100 | .divs = { \ | |
101 | RK3128_CLKSEL1(_core_aclk_div, _pclk_dbg_div), \ | |
102 | }, \ | |
103 | } | |
104 | ||
105 | static struct rockchip_cpuclk_rate_table rk3128_cpuclk_rates[] __initdata = { | |
106 | RK3128_CPUCLK_RATE(1800000000, 1, 7), | |
107 | RK3128_CPUCLK_RATE(1704000000, 1, 7), | |
108 | RK3128_CPUCLK_RATE(1608000000, 1, 7), | |
109 | RK3128_CPUCLK_RATE(1512000000, 1, 7), | |
110 | RK3128_CPUCLK_RATE(1488000000, 1, 5), | |
111 | RK3128_CPUCLK_RATE(1416000000, 1, 5), | |
112 | RK3128_CPUCLK_RATE(1392000000, 1, 5), | |
113 | RK3128_CPUCLK_RATE(1296000000, 1, 5), | |
114 | RK3128_CPUCLK_RATE(1200000000, 1, 5), | |
115 | RK3128_CPUCLK_RATE(1104000000, 1, 5), | |
116 | RK3128_CPUCLK_RATE(1008000000, 1, 5), | |
117 | RK3128_CPUCLK_RATE(912000000, 1, 5), | |
118 | RK3128_CPUCLK_RATE(816000000, 1, 3), | |
119 | RK3128_CPUCLK_RATE(696000000, 1, 3), | |
120 | RK3128_CPUCLK_RATE(600000000, 1, 3), | |
121 | RK3128_CPUCLK_RATE(408000000, 1, 1), | |
122 | RK3128_CPUCLK_RATE(312000000, 1, 1), | |
123 | RK3128_CPUCLK_RATE(216000000, 1, 1), | |
124 | RK3128_CPUCLK_RATE(96000000, 1, 1), | |
125 | }; | |
126 | ||
127 | static const struct rockchip_cpuclk_reg_data rk3128_cpuclk_data = { | |
128 | .core_reg = RK2928_CLKSEL_CON(0), | |
129 | .div_core_shift = 0, | |
130 | .div_core_mask = 0x1f, | |
131 | .mux_core_alt = 1, | |
132 | .mux_core_main = 0, | |
133 | .mux_core_shift = 7, | |
134 | .mux_core_mask = 0x1, | |
135 | }; | |
136 | ||
137 | PNAME(mux_pll_p) = { "clk_24m", "xin24m" }; | |
138 | ||
139 | PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_div2_ddr" }; | |
140 | PNAME(mux_armclk_p) = { "apll_core", "gpll_div2_core" }; | |
141 | PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" }; | |
142 | PNAME(mux_aclk_cpu_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" }; | |
143 | ||
144 | PNAME(mux_pll_src_5plls_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3", "usb480m" }; | |
145 | PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "gpll_div2", "usb480m" }; | |
146 | PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "gpll_div2" }; | |
147 | ||
148 | PNAME(mux_aclk_peri_src_p) = { "gpll_peri", "cpll_peri", "gpll_div2_peri", "gpll_div3_peri" }; | |
149 | PNAME(mux_mmc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" }; | |
150 | PNAME(mux_clk_cif_out_src_p) = { "clk_cif_src", "xin24m" }; | |
151 | PNAME(mux_sclk_vop_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" }; | |
152 | ||
153 | PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; | |
154 | PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" }; | |
155 | PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" }; | |
156 | PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" }; | |
157 | ||
158 | PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; | |
159 | PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; | |
160 | PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; | |
161 | ||
162 | PNAME(mux_sclk_gmac_p) = { "sclk_gmac_src", "gmac_clkin" }; | |
163 | PNAME(mux_sclk_sfc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" }; | |
164 | ||
165 | static struct rockchip_pll_clock rk3128_pll_clks[] __initdata = { | |
166 | [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), | |
167 | RK2928_MODE_CON, 0, 1, 0, rk3128_pll_rates), | |
168 | [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), | |
169 | RK2928_MODE_CON, 4, 0, 0, NULL), | |
170 | [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8), | |
171 | RK2928_MODE_CON, 8, 2, 0, rk3128_pll_rates), | |
172 | [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), | |
173 | RK2928_MODE_CON, 12, 3, ROCKCHIP_PLL_SYNC_RATE, rk3128_pll_rates), | |
174 | }; | |
175 | ||
176 | #define MFLAGS CLK_MUX_HIWORD_MASK | |
177 | #define DFLAGS CLK_DIVIDER_HIWORD_MASK | |
178 | #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) | |
179 | ||
180 | static struct rockchip_clk_branch rk3128_i2s0_fracmux __initdata = | |
181 | MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT, | |
182 | RK2928_CLKSEL_CON(9), 8, 2, MFLAGS); | |
183 | ||
184 | static struct rockchip_clk_branch rk3128_i2s1_fracmux __initdata = | |
185 | MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT, | |
186 | RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); | |
187 | ||
188 | static struct rockchip_clk_branch rk3128_spdif_fracmux __initdata = | |
189 | MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT, | |
190 | RK2928_CLKSEL_CON(6), 8, 2, MFLAGS); | |
191 | ||
192 | static struct rockchip_clk_branch rk3128_uart0_fracmux __initdata = | |
193 | MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, | |
194 | RK2928_CLKSEL_CON(13), 8, 2, MFLAGS); | |
195 | ||
196 | static struct rockchip_clk_branch rk3128_uart1_fracmux __initdata = | |
197 | MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, | |
198 | RK2928_CLKSEL_CON(14), 8, 2, MFLAGS); | |
199 | ||
200 | static struct rockchip_clk_branch rk3128_uart2_fracmux __initdata = | |
201 | MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, | |
202 | RK2928_CLKSEL_CON(15), 8, 2, MFLAGS); | |
203 | ||
33461405 | 204 | static struct rockchip_clk_branch common_clk_branches[] __initdata = { |
f6022e88 EZ |
205 | /* |
206 | * Clock-Architecture Diagram 1 | |
207 | */ | |
208 | ||
209 | FACTOR(PLL_GPLL_DIV2, "gpll_div2", "gpll", 0, 1, 2), | |
210 | FACTOR(PLL_GPLL_DIV3, "gpll_div3", "gpll", 0, 1, 3), | |
211 | ||
212 | DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, | |
213 | RK2928_CLKSEL_CON(4), 8, 5, DFLAGS), | |
214 | ||
215 | /* PD_DDR */ | |
216 | GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, | |
217 | RK2928_CLKGATE_CON(0), 2, GFLAGS), | |
218 | GATE(0, "gpll_div2_ddr", "gpll_div2", CLK_IGNORE_UNUSED, | |
219 | RK2928_CLKGATE_CON(0), 2, GFLAGS), | |
220 | COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED, | |
221 | RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), | |
222 | FACTOR(SCLK_DDRC, "clk_ddrc", "ddrphy2x", 0, 1, 2), | |
223 | FACTOR(0, "clk_ddrphy", "ddrphy2x", 0, 1, 2), | |
224 | ||
225 | /* PD_CORE */ | |
226 | GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, | |
227 | RK2928_CLKGATE_CON(0), 6, GFLAGS), | |
228 | GATE(0, "gpll_div2_core", "gpll_div2", CLK_IGNORE_UNUSED, | |
229 | RK2928_CLKGATE_CON(0), 6, GFLAGS), | |
230 | COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, | |
231 | RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, | |
232 | RK2928_CLKGATE_CON(0), 0, GFLAGS), | |
233 | COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED, | |
234 | RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, | |
235 | RK2928_CLKGATE_CON(0), 7, GFLAGS), | |
236 | ||
237 | /* PD_MISC */ | |
238 | MUX(SCLK_USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, | |
239 | RK2928_MISC_CON, 15, 1, MFLAGS), | |
240 | ||
241 | /* PD_CPU */ | |
242 | COMPOSITE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0, | |
243 | RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS, | |
244 | RK2928_CLKGATE_CON(0), 1, GFLAGS), | |
245 | GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0, | |
246 | RK2928_CLKGATE_CON(0), 3, GFLAGS), | |
247 | COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", 0, | |
248 | RK2928_CLKSEL_CON(1), 8, 2, DFLAGS, | |
249 | RK2928_CLKGATE_CON(0), 4, GFLAGS), | |
250 | COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", 0, | |
251 | RK2928_CLKSEL_CON(1), 12, 2, DFLAGS, | |
252 | RK2928_CLKGATE_CON(0), 5, GFLAGS), | |
253 | COMPOSITE_NOMUX(SCLK_CRYPTO, "clk_crypto", "aclk_cpu_src", 0, | |
254 | RK2928_CLKSEL_CON(24), 0, 2, DFLAGS, | |
255 | RK2928_CLKGATE_CON(0), 12, GFLAGS), | |
256 | ||
257 | /* PD_VIDEO */ | |
258 | COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_5plls_p, 0, | |
259 | RK2928_CLKSEL_CON(32), 5, 3, MFLAGS, 0, 5, DFLAGS, | |
260 | RK2928_CLKGATE_CON(3), 9, GFLAGS), | |
261 | FACTOR(HCLK_VEPU, "hclk_vepu", "aclk_vepu", 0, 1, 4), | |
262 | ||
263 | COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_5plls_p, 0, | |
264 | RK2928_CLKSEL_CON(32), 13, 3, MFLAGS, 8, 5, DFLAGS, | |
265 | RK2928_CLKGATE_CON(3), 11, GFLAGS), | |
266 | FACTOR_GATE(HCLK_VDPU, "hclk_vdpu", "aclk_vdpu", 0, 1, 4, | |
267 | RK2928_CLKGATE_CON(3), 12, GFLAGS), | |
268 | ||
269 | COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_5plls_p, 0, | |
270 | RK2928_CLKSEL_CON(34), 13, 3, MFLAGS, 8, 5, DFLAGS, | |
271 | RK2928_CLKGATE_CON(3), 10, GFLAGS), | |
272 | ||
273 | /* PD_VIO */ | |
274 | COMPOSITE(ACLK_VIO0, "aclk_vio0", mux_pll_src_5plls_p, 0, | |
275 | RK2928_CLKSEL_CON(31), 5, 3, MFLAGS, 0, 5, DFLAGS, | |
276 | RK2928_CLKGATE_CON(3), 0, GFLAGS), | |
277 | COMPOSITE(ACLK_VIO1, "aclk_vio1", mux_pll_src_5plls_p, 0, | |
278 | RK2928_CLKSEL_CON(31), 13, 3, MFLAGS, 8, 5, DFLAGS, | |
279 | RK2928_CLKGATE_CON(1), 4, GFLAGS), | |
280 | COMPOSITE(HCLK_VIO, "hclk_vio", mux_pll_src_4plls_p, 0, | |
281 | RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, | |
282 | RK2928_CLKGATE_CON(0), 11, GFLAGS), | |
283 | ||
284 | /* PD_PERI */ | |
285 | GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED, | |
286 | RK2928_CLKGATE_CON(2), 0, GFLAGS), | |
287 | GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED, | |
288 | RK2928_CLKGATE_CON(2), 0, GFLAGS), | |
289 | GATE(0, "gpll_div2_peri", "gpll_div2", CLK_IGNORE_UNUSED, | |
290 | RK2928_CLKGATE_CON(2), 0, GFLAGS), | |
291 | GATE(0, "gpll_div3_peri", "gpll_div3", CLK_IGNORE_UNUSED, | |
292 | RK2928_CLKGATE_CON(2), 0, GFLAGS), | |
293 | COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0, | |
294 | RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS), | |
295 | COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0, | |
296 | RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, | |
297 | RK2928_CLKGATE_CON(2), 3, GFLAGS), | |
298 | COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0, | |
299 | RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, | |
300 | RK2928_CLKGATE_CON(2), 2, GFLAGS), | |
301 | GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, | |
302 | RK2928_CLKGATE_CON(2), 1, GFLAGS), | |
303 | ||
304 | GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, | |
305 | RK2928_CLKGATE_CON(10), 3, GFLAGS), | |
306 | GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, | |
307 | RK2928_CLKGATE_CON(10), 4, GFLAGS), | |
308 | GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, | |
309 | RK2928_CLKGATE_CON(10), 5, GFLAGS), | |
310 | GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, | |
311 | RK2928_CLKGATE_CON(10), 6, GFLAGS), | |
312 | GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, | |
313 | RK2928_CLKGATE_CON(10), 7, GFLAGS), | |
314 | GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, | |
315 | RK2928_CLKGATE_CON(10), 8, GFLAGS), | |
316 | ||
317 | GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0, | |
a4eb2865 | 318 | RK2928_CLKGATE_CON(10), 0, GFLAGS), |
f6022e88 | 319 | GATE(SCLK_PVTM_GPU, "clk_pvtm_gpu", "xin24m", 0, |
a4eb2865 | 320 | RK2928_CLKGATE_CON(10), 1, GFLAGS), |
f6022e88 | 321 | GATE(SCLK_PVTM_FUNC, "clk_pvtm_func", "xin24m", 0, |
a4eb2865 | 322 | RK2928_CLKGATE_CON(10), 2, GFLAGS), |
f6022e88 | 323 | GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", CLK_IGNORE_UNUSED, |
a4eb2865 | 324 | RK2928_CLKGATE_CON(2), 15, GFLAGS), |
f6022e88 EZ |
325 | |
326 | COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, | |
327 | RK2928_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS, | |
328 | RK2928_CLKGATE_CON(2), 11, GFLAGS), | |
329 | ||
330 | COMPOSITE(SCLK_SDIO, "sclk_sdio", mux_mmc_src_p, 0, | |
331 | RK2928_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS, | |
332 | RK2928_CLKGATE_CON(2), 13, GFLAGS), | |
333 | ||
334 | COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0, | |
335 | RK2928_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS, | |
336 | RK2928_CLKGATE_CON(2), 14, GFLAGS), | |
337 | ||
338 | DIV(SCLK_PVTM, "clk_pvtm", "clk_pvtm_func", 0, | |
339 | RK2928_CLKSEL_CON(2), 0, 7, DFLAGS), | |
340 | ||
341 | /* | |
342 | * Clock-Architecture Diagram 2 | |
343 | */ | |
344 | COMPOSITE(DCLK_VOP, "dclk_vop", mux_sclk_vop_src_p, 0, | |
345 | RK2928_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS, | |
346 | RK2928_CLKGATE_CON(3), 1, GFLAGS), | |
347 | COMPOSITE(SCLK_VOP, "sclk_vop", mux_sclk_vop_src_p, 0, | |
348 | RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS, | |
349 | RK2928_CLKGATE_CON(3), 2, GFLAGS), | |
350 | COMPOSITE(DCLK_EBC, "dclk_ebc", mux_pll_src_3plls_p, 0, | |
351 | RK2928_CLKSEL_CON(23), 0, 2, MFLAGS, 8, 8, DFLAGS, | |
352 | RK2928_CLKGATE_CON(3), 4, GFLAGS), | |
353 | ||
354 | FACTOR(0, "xin12m", "xin24m", 0, 1, 2), | |
355 | ||
356 | COMPOSITE_NODIV(SCLK_CIF_SRC, "sclk_cif_src", mux_pll_src_4plls_p, 0, | |
357 | RK2928_CLKSEL_CON(29), 0, 2, MFLAGS, | |
358 | RK2928_CLKGATE_CON(3), 7, GFLAGS), | |
359 | MUX(SCLK_CIF_OUT_SRC, "sclk_cif_out_src", mux_clk_cif_out_src_p, 0, | |
360 | RK2928_CLKSEL_CON(13), 14, 2, MFLAGS), | |
361 | DIV(SCLK_CIF_OUT, "sclk_cif_out", "sclk_cif_out_src", 0, | |
362 | RK2928_CLKSEL_CON(29), 2, 5, DFLAGS), | |
363 | ||
364 | COMPOSITE(0, "i2s0_src", mux_pll_src_3plls_p, 0, | |
365 | RK2928_CLKSEL_CON(9), 14, 2, MFLAGS, 0, 7, DFLAGS, | |
366 | RK2928_CLKGATE_CON(4), 4, GFLAGS), | |
367 | COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, | |
368 | RK2928_CLKSEL_CON(8), 0, | |
369 | RK2928_CLKGATE_CON(4), 5, GFLAGS, | |
370 | &rk3128_i2s0_fracmux), | |
371 | GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT, | |
372 | RK2928_CLKGATE_CON(4), 6, GFLAGS), | |
373 | ||
374 | COMPOSITE(0, "i2s1_src", mux_pll_src_3plls_p, 0, | |
375 | RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS, | |
376 | RK2928_CLKGATE_CON(0), 9, GFLAGS), | |
377 | COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, | |
378 | RK2928_CLKSEL_CON(7), 0, | |
379 | RK2928_CLKGATE_CON(0), 10, GFLAGS, | |
380 | &rk3128_i2s1_fracmux), | |
381 | GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT, | |
382 | RK2928_CLKGATE_CON(0), 14, GFLAGS), | |
383 | COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0, | |
384 | RK2928_CLKSEL_CON(3), 12, 1, MFLAGS, | |
385 | RK2928_CLKGATE_CON(0), 13, GFLAGS), | |
386 | ||
387 | COMPOSITE(0, "sclk_spdif_src", mux_pll_src_3plls_p, 0, | |
388 | RK2928_CLKSEL_CON(6), 14, 2, MFLAGS, 0, 7, DFLAGS, | |
389 | RK2928_CLKGATE_CON(2), 10, GFLAGS), | |
390 | COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT, | |
391 | RK2928_CLKSEL_CON(20), 0, | |
392 | RK2928_CLKGATE_CON(2), 12, GFLAGS, | |
393 | &rk3128_spdif_fracmux), | |
394 | ||
395 | GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED, | |
396 | RK2928_CLKGATE_CON(1), 3, GFLAGS), | |
397 | ||
398 | GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", 0, | |
399 | RK2928_CLKGATE_CON(1), 5, GFLAGS), | |
400 | GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin12m", 0, | |
401 | RK2928_CLKGATE_CON(1), 6, GFLAGS), | |
402 | ||
403 | COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0, | |
404 | RK2928_CLKSEL_CON(24), 8, 8, DFLAGS, | |
405 | RK2928_CLKGATE_CON(2), 8, GFLAGS), | |
406 | ||
407 | COMPOSITE(ACLK_GPU, "aclk_gpu", mux_pll_src_5plls_p, 0, | |
408 | RK2928_CLKSEL_CON(34), 5, 3, MFLAGS, 0, 5, DFLAGS, | |
409 | RK2928_CLKGATE_CON(3), 13, GFLAGS), | |
410 | ||
411 | COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_3plls_p, 0, | |
412 | RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS, | |
413 | RK2928_CLKGATE_CON(2), 9, GFLAGS), | |
414 | ||
415 | /* PD_UART */ | |
416 | COMPOSITE(0, "uart0_src", mux_pll_src_4plls_p, 0, | |
417 | RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS, | |
418 | RK2928_CLKGATE_CON(1), 8, GFLAGS), | |
419 | MUX(0, "uart12_src", mux_pll_src_4plls_p, 0, | |
420 | RK2928_CLKSEL_CON(13), 14, 2, MFLAGS), | |
421 | COMPOSITE_NOMUX(0, "uart1_src", "uart12_src", 0, | |
422 | RK2928_CLKSEL_CON(14), 0, 7, DFLAGS, | |
423 | RK2928_CLKGATE_CON(1), 10, GFLAGS), | |
424 | COMPOSITE_NOMUX(0, "uart2_src", "uart12_src", 0, | |
425 | RK2928_CLKSEL_CON(15), 0, 7, DFLAGS, | |
426 | RK2928_CLKGATE_CON(1), 13, GFLAGS), | |
427 | COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, | |
428 | RK2928_CLKSEL_CON(17), 0, | |
429 | RK2928_CLKGATE_CON(1), 9, GFLAGS, | |
430 | &rk3128_uart0_fracmux), | |
431 | COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, | |
432 | RK2928_CLKSEL_CON(18), 0, | |
433 | RK2928_CLKGATE_CON(1), 11, GFLAGS, | |
434 | &rk3128_uart1_fracmux), | |
435 | COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, | |
436 | RK2928_CLKSEL_CON(19), 0, | |
437 | RK2928_CLKGATE_CON(1), 13, GFLAGS, | |
438 | &rk3128_uart2_fracmux), | |
439 | ||
440 | COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_3plls_p, 0, | |
441 | RK2928_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS, | |
442 | RK2928_CLKGATE_CON(1), 7, GFLAGS), | |
443 | MUX(SCLK_MAC, "sclk_gmac", mux_sclk_gmac_p, 0, | |
444 | RK2928_CLKSEL_CON(5), 15, 1, MFLAGS), | |
445 | GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_gmac", 0, | |
446 | RK2928_CLKGATE_CON(2), 5, GFLAGS), | |
447 | GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_gmac", 0, | |
448 | RK2928_CLKGATE_CON(2), 4, GFLAGS), | |
449 | GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_gmac", 0, | |
450 | RK2928_CLKGATE_CON(2), 6, GFLAGS), | |
451 | GATE(SCLK_MAC_TX, "sclk_mac_tx", "sclk_gmac", 0, | |
452 | RK2928_CLKGATE_CON(2), 7, GFLAGS), | |
453 | ||
454 | COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_3plls_p, 0, | |
455 | RK2928_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS, | |
456 | RK2928_CLKGATE_CON(1), 14, GFLAGS), | |
457 | ||
458 | COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0, | |
459 | RK2928_CLKSEL_CON(2), 14, 2, MFLAGS, 8, 5, DFLAGS, | |
460 | RK2928_CLKGATE_CON(10), 15, GFLAGS), | |
461 | ||
f6022e88 EZ |
462 | COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "cpll", 0, |
463 | RK2928_CLKSEL_CON(29), 8, 6, DFLAGS, | |
464 | RK2928_CLKGATE_CON(1), 0, GFLAGS), | |
465 | ||
466 | /* | |
467 | * Clock-Architecture Diagram 3 | |
468 | */ | |
469 | ||
470 | /* PD_VOP */ | |
471 | GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS), | |
472 | GATE(ACLK_CIF, "aclk_cif", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS), | |
473 | GATE(ACLK_RGA, "aclk_rga", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS), | |
474 | GATE(0, "aclk_vio0_niu", "aclk_vio0", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS), | |
475 | ||
476 | GATE(ACLK_IEP, "aclk_iep", "aclk_vio1", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS), | |
477 | GATE(0, "aclk_vio1_niu", "aclk_vio1", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 10, GFLAGS), | |
478 | ||
479 | GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS), | |
480 | GATE(PCLK_MIPI, "pclk_mipi", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS), | |
481 | GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS), | |
482 | GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS), | |
483 | GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS), | |
484 | GATE(0, "hclk_vio_niu", "hclk_vio", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 12, GFLAGS), | |
485 | GATE(HCLK_CIF, "hclk_cif", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS), | |
486 | GATE(HCLK_EBC, "hclk_ebc", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS), | |
487 | ||
488 | /* PD_PERI */ | |
489 | GATE(0, "aclk_peri_axi", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS), | |
490 | GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(10), 10, GFLAGS), | |
491 | GATE(ACLK_DMAC, "aclk_dmac", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS), | |
492 | GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS), | |
493 | GATE(0, "aclk_cpu_to_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS), | |
f6022e88 EZ |
494 | |
495 | GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), | |
496 | GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS), | |
497 | GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), | |
498 | GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS), | |
499 | GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), | |
500 | GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 13, GFLAGS), | |
501 | GATE(0, "hclk_peri_ahb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS), | |
502 | GATE(HCLK_SPDIF, "hclk_spdif", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS), | |
503 | GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 12, GFLAGS), | |
504 | GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS), | |
505 | GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS), | |
506 | GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS), | |
507 | GATE(0, "hclk_emmc_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 6, GFLAGS), | |
508 | GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS), | |
509 | GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 14, GFLAGS), | |
510 | ||
511 | GATE(PCLK_SIM_CARD, "pclk_sim_card", "pclk_peri", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS), | |
512 | GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS), | |
513 | GATE(0, "pclk_peri_axi", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS), | |
514 | GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS), | |
515 | GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), | |
516 | GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), | |
517 | GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS), | |
518 | GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS), | |
519 | GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS), | |
520 | GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS), | |
521 | GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS), | |
522 | GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS), | |
523 | GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS), | |
524 | GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS), | |
525 | GATE(PCLK_EFUSE, "pclk_efuse", "pclk_peri", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS), | |
526 | GATE(PCLK_TIMER, "pclk_timer", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 7, GFLAGS), | |
527 | GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS), | |
528 | GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS), | |
529 | GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS), | |
530 | GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS), | |
531 | ||
532 | /* PD_BUS */ | |
533 | GATE(0, "aclk_initmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS), | |
534 | GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS), | |
535 | ||
536 | GATE(0, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS), | |
537 | GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), | |
538 | ||
f6022e88 EZ |
539 | GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS), |
540 | GATE(0, "pclk_ddrupctl", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 7, GFLAGS), | |
541 | GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS), | |
542 | GATE(0, "pclk_mipiphy", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 0, GFLAGS), | |
543 | ||
e8620acc | 544 | GATE(0, "pclk_pmu", "pclk_pmu_pre", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS), |
f6022e88 EZ |
545 | GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 3, GFLAGS), |
546 | ||
547 | /* PD_MMC */ | |
548 | MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1), | |
549 | MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0), | |
550 | ||
551 | MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1), | |
552 | MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 0), | |
553 | ||
554 | MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1), | |
555 | MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0), | |
556 | }; | |
557 | ||
33461405 EZ |
558 | static struct rockchip_clk_branch rk3126_clk_branches[] __initdata = { |
559 | GATE(0, "pclk_stimer", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15, GFLAGS), | |
560 | GATE(0, "pclk_s_efuse", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), | |
561 | GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 8, GFLAGS), | |
562 | }; | |
563 | ||
564 | static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = { | |
565 | COMPOSITE(SCLK_SFC, "sclk_sfc", mux_sclk_sfc_src_p, 0, | |
566 | RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS, | |
567 | RK2928_CLKGATE_CON(3), 15, GFLAGS), | |
568 | ||
569 | GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS), | |
570 | GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS), | |
571 | }; | |
572 | ||
f6022e88 EZ |
573 | static const char *const rk3128_critical_clocks[] __initconst = { |
574 | "aclk_cpu", | |
575 | "hclk_cpu", | |
576 | "pclk_cpu", | |
577 | "aclk_peri", | |
578 | "hclk_peri", | |
579 | "pclk_peri", | |
e8620acc | 580 | "pclk_pmu", |
00e6751f | 581 | "sclk_timer5", |
f6022e88 EZ |
582 | }; |
583 | ||
33461405 | 584 | static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np) |
f6022e88 EZ |
585 | { |
586 | struct rockchip_clk_provider *ctx; | |
587 | void __iomem *reg_base; | |
588 | ||
589 | reg_base = of_iomap(np, 0); | |
590 | if (!reg_base) { | |
591 | pr_err("%s: could not map cru region\n", __func__); | |
33461405 | 592 | return ERR_PTR(-ENOMEM); |
f6022e88 EZ |
593 | } |
594 | ||
595 | ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); | |
596 | if (IS_ERR(ctx)) { | |
597 | pr_err("%s: rockchip clk init failed\n", __func__); | |
598 | iounmap(reg_base); | |
33461405 | 599 | return ERR_PTR(-ENOMEM); |
f6022e88 EZ |
600 | } |
601 | ||
602 | rockchip_clk_register_plls(ctx, rk3128_pll_clks, | |
603 | ARRAY_SIZE(rk3128_pll_clks), | |
604 | RK3128_GRF_SOC_STATUS0); | |
33461405 EZ |
605 | rockchip_clk_register_branches(ctx, common_clk_branches, |
606 | ARRAY_SIZE(common_clk_branches)); | |
f6022e88 EZ |
607 | |
608 | rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", | |
609 | mux_armclk_p, ARRAY_SIZE(mux_armclk_p), | |
610 | &rk3128_cpuclk_data, rk3128_cpuclk_rates, | |
611 | ARRAY_SIZE(rk3128_cpuclk_rates)); | |
612 | ||
613 | rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), | |
614 | ROCKCHIP_SOFTRST_HIWORD_MASK); | |
615 | ||
616 | rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL); | |
617 | ||
33461405 EZ |
618 | return ctx; |
619 | } | |
620 | ||
621 | static void __init rk3126_clk_init(struct device_node *np) | |
622 | { | |
623 | struct rockchip_clk_provider *ctx; | |
624 | ||
625 | ctx = rk3128_common_clk_init(np); | |
626 | if (IS_ERR(ctx)) | |
627 | return; | |
628 | ||
629 | rockchip_clk_register_branches(ctx, rk3126_clk_branches, | |
630 | ARRAY_SIZE(rk3126_clk_branches)); | |
631 | rockchip_clk_protect_critical(rk3128_critical_clocks, | |
632 | ARRAY_SIZE(rk3128_critical_clocks)); | |
633 | ||
634 | rockchip_clk_of_add_provider(np, ctx); | |
635 | } | |
636 | ||
637 | CLK_OF_DECLARE(rk3126_cru, "rockchip,rk3126-cru", rk3126_clk_init); | |
638 | ||
639 | static void __init rk3128_clk_init(struct device_node *np) | |
640 | { | |
641 | struct rockchip_clk_provider *ctx; | |
642 | ||
643 | ctx = rk3128_common_clk_init(np); | |
644 | if (IS_ERR(ctx)) | |
645 | return; | |
646 | ||
647 | rockchip_clk_register_branches(ctx, rk3128_clk_branches, | |
648 | ARRAY_SIZE(rk3128_clk_branches)); | |
649 | rockchip_clk_protect_critical(rk3128_critical_clocks, | |
650 | ARRAY_SIZE(rk3128_critical_clocks)); | |
651 | ||
f6022e88 EZ |
652 | rockchip_clk_of_add_provider(np, ctx); |
653 | } | |
654 | ||
655 | CLK_OF_DECLARE(rk3128_cru, "rockchip,rk3128-cru", rk3128_clk_init); |