Commit | Line | Data |
---|---|---|
f6fba5f6 HS |
1 | /* |
2 | * Copyright (c) 2014 MundoReader S.L. | |
3 | * Author: Heiko Stuebner <heiko@sntech.de> | |
4 | * | |
5 | * based on clk/samsung/clk-cpu.c | |
6 | * Copyright (c) 2014 Samsung Electronics Co., Ltd. | |
7 | * Author: Thomas Abraham <thomas.ab@samsung.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * A CPU clock is defined as a clock supplied to a CPU or a group of CPUs. | |
14 | * The CPU clock is typically derived from a hierarchy of clock | |
15 | * blocks which includes mux and divider blocks. There are a number of other | |
16 | * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI | |
17 | * clock for CPU domain. The rates of these auxiliary clocks are related to the | |
18 | * CPU clock rate and this relation is usually specified in the hardware manual | |
19 | * of the SoC or supplied after the SoC characterization. | |
20 | * | |
21 | * The below implementation of the CPU clock allows the rate changes of the CPU | |
22 | * clock and the corresponding rate changes of the auxillary clocks of the CPU | |
23 | * domain. The platform clock driver provides a clock register configuration | |
24 | * for each configurable rate which is then used to program the clock hardware | |
25 | * registers to acheive a fast co-oridinated rate change for all the CPU domain | |
26 | * clocks. | |
27 | * | |
28 | * On a rate change request for the CPU clock, the rate change is propagated | |
29 | * upto the PLL supplying the clock to the CPU domain clock blocks. While the | |
30 | * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an | |
31 | * alternate clock source. If required, the alternate clock source is divided | |
32 | * down in order to keep the output clock rate within the previous OPP limits. | |
33 | */ | |
34 | ||
35 | #include <linux/of.h> | |
36 | #include <linux/slab.h> | |
37 | #include <linux/io.h> | |
38 | #include <linux/clk-provider.h> | |
39 | #include "clk.h" | |
40 | ||
41 | /** | |
42 | * struct rockchip_cpuclk: information about clock supplied to a CPU core. | |
43 | * @hw: handle between ccf and cpu clock. | |
44 | * @alt_parent: alternate parent clock to use when switching the speed | |
45 | * of the primary parent clock. | |
46 | * @reg_base: base register for cpu-clock values. | |
47 | * @clk_nb: clock notifier registered for changes in clock speed of the | |
48 | * primary parent clock. | |
49 | * @rate_count: number of rates in the rate_table | |
50 | * @rate_table: pll-rates and their associated dividers | |
51 | * @reg_data: cpu-specific register settings | |
52 | * @lock: clock lock | |
53 | */ | |
54 | struct rockchip_cpuclk { | |
55 | struct clk_hw hw; | |
56 | ||
57 | struct clk_mux cpu_mux; | |
58 | const struct clk_ops *cpu_mux_ops; | |
59 | ||
60 | struct clk *alt_parent; | |
61 | void __iomem *reg_base; | |
62 | struct notifier_block clk_nb; | |
63 | unsigned int rate_count; | |
64 | struct rockchip_cpuclk_rate_table *rate_table; | |
65 | const struct rockchip_cpuclk_reg_data *reg_data; | |
66 | spinlock_t *lock; | |
67 | }; | |
68 | ||
69 | #define to_rockchip_cpuclk_hw(hw) container_of(hw, struct rockchip_cpuclk, hw) | |
70 | #define to_rockchip_cpuclk_nb(nb) \ | |
71 | container_of(nb, struct rockchip_cpuclk, clk_nb) | |
72 | ||
73 | static const struct rockchip_cpuclk_rate_table *rockchip_get_cpuclk_settings( | |
74 | struct rockchip_cpuclk *cpuclk, unsigned long rate) | |
75 | { | |
76 | const struct rockchip_cpuclk_rate_table *rate_table = | |
77 | cpuclk->rate_table; | |
78 | int i; | |
79 | ||
80 | for (i = 0; i < cpuclk->rate_count; i++) { | |
81 | if (rate == rate_table[i].prate) | |
82 | return &rate_table[i]; | |
83 | } | |
84 | ||
85 | return NULL; | |
86 | } | |
87 | ||
88 | static unsigned long rockchip_cpuclk_recalc_rate(struct clk_hw *hw, | |
89 | unsigned long parent_rate) | |
90 | { | |
91 | struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw); | |
92 | const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; | |
93 | u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg); | |
94 | ||
95 | clksel0 >>= reg_data->div_core_shift; | |
96 | clksel0 &= reg_data->div_core_mask; | |
97 | return parent_rate / (clksel0 + 1); | |
98 | } | |
99 | ||
100 | static const struct clk_ops rockchip_cpuclk_ops = { | |
101 | .recalc_rate = rockchip_cpuclk_recalc_rate, | |
102 | }; | |
103 | ||
104 | static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk, | |
105 | const struct rockchip_cpuclk_rate_table *rate) | |
106 | { | |
107 | int i; | |
108 | ||
109 | /* alternate parent is active now. set the dividers */ | |
110 | for (i = 0; i < ARRAY_SIZE(rate->divs); i++) { | |
111 | const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i]; | |
112 | ||
113 | if (!clksel->reg) | |
114 | continue; | |
115 | ||
116 | pr_debug("%s: setting reg 0x%x to 0x%x\n", | |
117 | __func__, clksel->reg, clksel->val); | |
118 | writel(clksel->val , cpuclk->reg_base + clksel->reg); | |
119 | } | |
120 | } | |
121 | ||
122 | static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, | |
123 | struct clk_notifier_data *ndata) | |
124 | { | |
125 | const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; | |
126 | unsigned long alt_prate, alt_div; | |
a5e1baf7 | 127 | unsigned long flags; |
f6fba5f6 HS |
128 | |
129 | alt_prate = clk_get_rate(cpuclk->alt_parent); | |
130 | ||
a5e1baf7 | 131 | spin_lock_irqsave(cpuclk->lock, flags); |
f6fba5f6 HS |
132 | |
133 | /* | |
134 | * If the old parent clock speed is less than the clock speed | |
135 | * of the alternate parent, then it should be ensured that at no point | |
136 | * the armclk speed is more than the old_rate until the dividers are | |
137 | * set. | |
138 | */ | |
139 | if (alt_prate > ndata->old_rate) { | |
140 | /* calculate dividers */ | |
141 | alt_div = DIV_ROUND_UP(alt_prate, ndata->old_rate) - 1; | |
142 | if (alt_div > reg_data->div_core_mask) { | |
143 | pr_warn("%s: limiting alt-divider %lu to %d\n", | |
144 | __func__, alt_div, reg_data->div_core_mask); | |
145 | alt_div = reg_data->div_core_mask; | |
146 | } | |
147 | ||
148 | /* | |
149 | * Change parents and add dividers in a single transaction. | |
150 | * | |
151 | * NOTE: we do this in a single transaction so we're never | |
152 | * dividing the primary parent by the extra dividers that were | |
153 | * needed for the alt. | |
154 | */ | |
155 | pr_debug("%s: setting div %lu as alt-rate %lu > old-rate %lu\n", | |
156 | __func__, alt_div, alt_prate, ndata->old_rate); | |
157 | ||
158 | writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask, | |
159 | reg_data->div_core_shift) | | |
160 | HIWORD_UPDATE(1, 1, reg_data->mux_core_shift), | |
161 | cpuclk->reg_base + reg_data->core_reg); | |
162 | } else { | |
163 | /* select alternate parent */ | |
164 | writel(HIWORD_UPDATE(1, 1, reg_data->mux_core_shift), | |
165 | cpuclk->reg_base + reg_data->core_reg); | |
166 | } | |
167 | ||
a5e1baf7 | 168 | spin_unlock_irqrestore(cpuclk->lock, flags); |
f6fba5f6 HS |
169 | return 0; |
170 | } | |
171 | ||
172 | static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk, | |
173 | struct clk_notifier_data *ndata) | |
174 | { | |
175 | const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; | |
176 | const struct rockchip_cpuclk_rate_table *rate; | |
a5e1baf7 | 177 | unsigned long flags; |
f6fba5f6 HS |
178 | |
179 | rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate); | |
180 | if (!rate) { | |
181 | pr_err("%s: Invalid rate : %lu for cpuclk\n", | |
182 | __func__, ndata->new_rate); | |
183 | return -EINVAL; | |
184 | } | |
185 | ||
a5e1baf7 | 186 | spin_lock_irqsave(cpuclk->lock, flags); |
f6fba5f6 HS |
187 | |
188 | if (ndata->old_rate < ndata->new_rate) | |
189 | rockchip_cpuclk_set_dividers(cpuclk, rate); | |
190 | ||
191 | /* | |
192 | * post-rate change event, re-mux to primary parent and remove dividers. | |
193 | * | |
194 | * NOTE: we do this in a single transaction so we're never dividing the | |
195 | * primary parent by the extra dividers that were needed for the alt. | |
196 | */ | |
197 | ||
198 | writel(HIWORD_UPDATE(0, reg_data->div_core_mask, | |
199 | reg_data->div_core_shift) | | |
200 | HIWORD_UPDATE(0, 1, reg_data->mux_core_shift), | |
201 | cpuclk->reg_base + reg_data->core_reg); | |
202 | ||
203 | if (ndata->old_rate > ndata->new_rate) | |
204 | rockchip_cpuclk_set_dividers(cpuclk, rate); | |
205 | ||
a5e1baf7 | 206 | spin_unlock_irqrestore(cpuclk->lock, flags); |
f6fba5f6 HS |
207 | return 0; |
208 | } | |
209 | ||
210 | /* | |
211 | * This clock notifier is called when the frequency of the parent clock | |
212 | * of cpuclk is to be changed. This notifier handles the setting up all | |
213 | * the divider clocks, remux to temporary parent and handling the safe | |
214 | * frequency levels when using temporary parent. | |
215 | */ | |
216 | static int rockchip_cpuclk_notifier_cb(struct notifier_block *nb, | |
217 | unsigned long event, void *data) | |
218 | { | |
219 | struct clk_notifier_data *ndata = data; | |
220 | struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_nb(nb); | |
221 | int ret = 0; | |
222 | ||
223 | pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n", | |
224 | __func__, event, ndata->old_rate, ndata->new_rate); | |
225 | if (event == PRE_RATE_CHANGE) | |
226 | ret = rockchip_cpuclk_pre_rate_change(cpuclk, ndata); | |
227 | else if (event == POST_RATE_CHANGE) | |
228 | ret = rockchip_cpuclk_post_rate_change(cpuclk, ndata); | |
229 | ||
230 | return notifier_from_errno(ret); | |
231 | } | |
232 | ||
233 | struct clk *rockchip_clk_register_cpuclk(const char *name, | |
234 | const char **parent_names, u8 num_parents, | |
235 | const struct rockchip_cpuclk_reg_data *reg_data, | |
236 | const struct rockchip_cpuclk_rate_table *rates, | |
237 | int nrates, void __iomem *reg_base, spinlock_t *lock) | |
238 | { | |
239 | struct rockchip_cpuclk *cpuclk; | |
240 | struct clk_init_data init; | |
241 | struct clk *clk, *cclk; | |
242 | int ret; | |
243 | ||
244 | if (num_parents != 2) { | |
245 | pr_err("%s: needs two parent clocks\n", __func__); | |
246 | return ERR_PTR(-EINVAL); | |
247 | } | |
248 | ||
249 | cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL); | |
250 | if (!cpuclk) | |
251 | return ERR_PTR(-ENOMEM); | |
252 | ||
253 | init.name = name; | |
254 | init.parent_names = &parent_names[0]; | |
255 | init.num_parents = 1; | |
256 | init.ops = &rockchip_cpuclk_ops; | |
257 | ||
258 | /* only allow rate changes when we have a rate table */ | |
259 | init.flags = (nrates > 0) ? CLK_SET_RATE_PARENT : 0; | |
260 | ||
261 | /* disallow automatic parent changes by ccf */ | |
262 | init.flags |= CLK_SET_RATE_NO_REPARENT; | |
263 | ||
264 | init.flags |= CLK_GET_RATE_NOCACHE; | |
265 | ||
266 | cpuclk->reg_base = reg_base; | |
267 | cpuclk->lock = lock; | |
268 | cpuclk->reg_data = reg_data; | |
269 | cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb; | |
270 | cpuclk->hw.init = &init; | |
271 | ||
272 | cpuclk->alt_parent = __clk_lookup(parent_names[1]); | |
273 | if (!cpuclk->alt_parent) { | |
274 | pr_err("%s: could not lookup alternate parent\n", | |
275 | __func__); | |
276 | ret = -EINVAL; | |
277 | goto free_cpuclk; | |
278 | } | |
279 | ||
280 | ret = clk_prepare_enable(cpuclk->alt_parent); | |
281 | if (ret) { | |
282 | pr_err("%s: could not enable alternate parent\n", | |
283 | __func__); | |
284 | goto free_cpuclk; | |
285 | } | |
286 | ||
287 | clk = __clk_lookup(parent_names[0]); | |
288 | if (!clk) { | |
289 | pr_err("%s: could not lookup parent clock %s\n", | |
290 | __func__, parent_names[0]); | |
291 | ret = -EINVAL; | |
292 | goto free_cpuclk; | |
293 | } | |
294 | ||
295 | ret = clk_notifier_register(clk, &cpuclk->clk_nb); | |
296 | if (ret) { | |
297 | pr_err("%s: failed to register clock notifier for %s\n", | |
298 | __func__, name); | |
299 | goto free_cpuclk; | |
300 | } | |
301 | ||
302 | if (nrates > 0) { | |
303 | cpuclk->rate_count = nrates; | |
304 | cpuclk->rate_table = kmemdup(rates, | |
305 | sizeof(*rates) * nrates, | |
306 | GFP_KERNEL); | |
307 | if (!cpuclk->rate_table) { | |
308 | pr_err("%s: could not allocate memory for cpuclk rates\n", | |
309 | __func__); | |
310 | ret = -ENOMEM; | |
311 | goto unregister_notifier; | |
312 | } | |
313 | } | |
314 | ||
315 | cclk = clk_register(NULL, &cpuclk->hw); | |
316 | if (IS_ERR(clk)) { | |
317 | pr_err("%s: could not register cpuclk %s\n", __func__, name); | |
318 | ret = PTR_ERR(clk); | |
319 | goto free_rate_table; | |
320 | } | |
321 | ||
322 | return cclk; | |
323 | ||
324 | free_rate_table: | |
325 | kfree(cpuclk->rate_table); | |
326 | unregister_notifier: | |
327 | clk_notifier_unregister(clk, &cpuclk->clk_nb); | |
328 | free_cpuclk: | |
329 | kfree(cpuclk); | |
330 | return ERR_PTR(ret); | |
331 | } |