Commit | Line | Data |
---|---|---|
f6fba5f6 HS |
1 | /* |
2 | * Copyright (c) 2014 MundoReader S.L. | |
3 | * Author: Heiko Stuebner <heiko@sntech.de> | |
4 | * | |
5 | * based on clk/samsung/clk-cpu.c | |
6 | * Copyright (c) 2014 Samsung Electronics Co., Ltd. | |
7 | * Author: Thomas Abraham <thomas.ab@samsung.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * A CPU clock is defined as a clock supplied to a CPU or a group of CPUs. | |
14 | * The CPU clock is typically derived from a hierarchy of clock | |
15 | * blocks which includes mux and divider blocks. There are a number of other | |
16 | * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI | |
17 | * clock for CPU domain. The rates of these auxiliary clocks are related to the | |
18 | * CPU clock rate and this relation is usually specified in the hardware manual | |
19 | * of the SoC or supplied after the SoC characterization. | |
20 | * | |
21 | * The below implementation of the CPU clock allows the rate changes of the CPU | |
22 | * clock and the corresponding rate changes of the auxillary clocks of the CPU | |
23 | * domain. The platform clock driver provides a clock register configuration | |
24 | * for each configurable rate which is then used to program the clock hardware | |
25 | * registers to acheive a fast co-oridinated rate change for all the CPU domain | |
26 | * clocks. | |
27 | * | |
28 | * On a rate change request for the CPU clock, the rate change is propagated | |
29 | * upto the PLL supplying the clock to the CPU domain clock blocks. While the | |
30 | * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an | |
31 | * alternate clock source. If required, the alternate clock source is divided | |
32 | * down in order to keep the output clock rate within the previous OPP limits. | |
33 | */ | |
34 | ||
35 | #include <linux/of.h> | |
36 | #include <linux/slab.h> | |
37 | #include <linux/io.h> | |
f684ff8b | 38 | #include <linux/clk.h> |
f6fba5f6 HS |
39 | #include <linux/clk-provider.h> |
40 | #include "clk.h" | |
41 | ||
42 | /** | |
43 | * struct rockchip_cpuclk: information about clock supplied to a CPU core. | |
44 | * @hw: handle between ccf and cpu clock. | |
45 | * @alt_parent: alternate parent clock to use when switching the speed | |
46 | * of the primary parent clock. | |
47 | * @reg_base: base register for cpu-clock values. | |
48 | * @clk_nb: clock notifier registered for changes in clock speed of the | |
49 | * primary parent clock. | |
50 | * @rate_count: number of rates in the rate_table | |
51 | * @rate_table: pll-rates and their associated dividers | |
52 | * @reg_data: cpu-specific register settings | |
53 | * @lock: clock lock | |
54 | */ | |
55 | struct rockchip_cpuclk { | |
56 | struct clk_hw hw; | |
57 | ||
58 | struct clk_mux cpu_mux; | |
59 | const struct clk_ops *cpu_mux_ops; | |
60 | ||
61 | struct clk *alt_parent; | |
62 | void __iomem *reg_base; | |
63 | struct notifier_block clk_nb; | |
64 | unsigned int rate_count; | |
65 | struct rockchip_cpuclk_rate_table *rate_table; | |
66 | const struct rockchip_cpuclk_reg_data *reg_data; | |
67 | spinlock_t *lock; | |
68 | }; | |
69 | ||
70 | #define to_rockchip_cpuclk_hw(hw) container_of(hw, struct rockchip_cpuclk, hw) | |
71 | #define to_rockchip_cpuclk_nb(nb) \ | |
72 | container_of(nb, struct rockchip_cpuclk, clk_nb) | |
73 | ||
74 | static const struct rockchip_cpuclk_rate_table *rockchip_get_cpuclk_settings( | |
75 | struct rockchip_cpuclk *cpuclk, unsigned long rate) | |
76 | { | |
77 | const struct rockchip_cpuclk_rate_table *rate_table = | |
78 | cpuclk->rate_table; | |
79 | int i; | |
80 | ||
81 | for (i = 0; i < cpuclk->rate_count; i++) { | |
82 | if (rate == rate_table[i].prate) | |
83 | return &rate_table[i]; | |
84 | } | |
85 | ||
86 | return NULL; | |
87 | } | |
88 | ||
89 | static unsigned long rockchip_cpuclk_recalc_rate(struct clk_hw *hw, | |
90 | unsigned long parent_rate) | |
91 | { | |
92 | struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw); | |
93 | const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; | |
94 | u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg); | |
95 | ||
96 | clksel0 >>= reg_data->div_core_shift; | |
97 | clksel0 &= reg_data->div_core_mask; | |
98 | return parent_rate / (clksel0 + 1); | |
99 | } | |
100 | ||
101 | static const struct clk_ops rockchip_cpuclk_ops = { | |
102 | .recalc_rate = rockchip_cpuclk_recalc_rate, | |
103 | }; | |
104 | ||
105 | static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk, | |
106 | const struct rockchip_cpuclk_rate_table *rate) | |
107 | { | |
108 | int i; | |
109 | ||
110 | /* alternate parent is active now. set the dividers */ | |
111 | for (i = 0; i < ARRAY_SIZE(rate->divs); i++) { | |
112 | const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i]; | |
113 | ||
114 | if (!clksel->reg) | |
115 | continue; | |
116 | ||
117 | pr_debug("%s: setting reg 0x%x to 0x%x\n", | |
118 | __func__, clksel->reg, clksel->val); | |
fc6d875e | 119 | writel(clksel->val, cpuclk->reg_base + clksel->reg); |
f6fba5f6 HS |
120 | } |
121 | } | |
122 | ||
123 | static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, | |
124 | struct clk_notifier_data *ndata) | |
125 | { | |
126 | const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; | |
127 | unsigned long alt_prate, alt_div; | |
a5e1baf7 | 128 | unsigned long flags; |
f6fba5f6 HS |
129 | |
130 | alt_prate = clk_get_rate(cpuclk->alt_parent); | |
131 | ||
a5e1baf7 | 132 | spin_lock_irqsave(cpuclk->lock, flags); |
f6fba5f6 HS |
133 | |
134 | /* | |
135 | * If the old parent clock speed is less than the clock speed | |
136 | * of the alternate parent, then it should be ensured that at no point | |
137 | * the armclk speed is more than the old_rate until the dividers are | |
138 | * set. | |
139 | */ | |
140 | if (alt_prate > ndata->old_rate) { | |
141 | /* calculate dividers */ | |
142 | alt_div = DIV_ROUND_UP(alt_prate, ndata->old_rate) - 1; | |
143 | if (alt_div > reg_data->div_core_mask) { | |
144 | pr_warn("%s: limiting alt-divider %lu to %d\n", | |
145 | __func__, alt_div, reg_data->div_core_mask); | |
146 | alt_div = reg_data->div_core_mask; | |
147 | } | |
148 | ||
149 | /* | |
150 | * Change parents and add dividers in a single transaction. | |
151 | * | |
152 | * NOTE: we do this in a single transaction so we're never | |
153 | * dividing the primary parent by the extra dividers that were | |
154 | * needed for the alt. | |
155 | */ | |
156 | pr_debug("%s: setting div %lu as alt-rate %lu > old-rate %lu\n", | |
157 | __func__, alt_div, alt_prate, ndata->old_rate); | |
158 | ||
159 | writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask, | |
160 | reg_data->div_core_shift) | | |
268aebaa XZ |
161 | HIWORD_UPDATE(reg_data->mux_core_alt, |
162 | reg_data->mux_core_mask, | |
163 | reg_data->mux_core_shift), | |
f6fba5f6 HS |
164 | cpuclk->reg_base + reg_data->core_reg); |
165 | } else { | |
166 | /* select alternate parent */ | |
268aebaa XZ |
167 | writel(HIWORD_UPDATE(reg_data->mux_core_alt, |
168 | reg_data->mux_core_mask, | |
169 | reg_data->mux_core_shift), | |
170 | cpuclk->reg_base + reg_data->core_reg); | |
f6fba5f6 HS |
171 | } |
172 | ||
a5e1baf7 | 173 | spin_unlock_irqrestore(cpuclk->lock, flags); |
f6fba5f6 HS |
174 | return 0; |
175 | } | |
176 | ||
177 | static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk, | |
178 | struct clk_notifier_data *ndata) | |
179 | { | |
180 | const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; | |
181 | const struct rockchip_cpuclk_rate_table *rate; | |
a5e1baf7 | 182 | unsigned long flags; |
f6fba5f6 HS |
183 | |
184 | rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate); | |
185 | if (!rate) { | |
186 | pr_err("%s: Invalid rate : %lu for cpuclk\n", | |
187 | __func__, ndata->new_rate); | |
188 | return -EINVAL; | |
189 | } | |
190 | ||
a5e1baf7 | 191 | spin_lock_irqsave(cpuclk->lock, flags); |
f6fba5f6 HS |
192 | |
193 | if (ndata->old_rate < ndata->new_rate) | |
194 | rockchip_cpuclk_set_dividers(cpuclk, rate); | |
195 | ||
196 | /* | |
197 | * post-rate change event, re-mux to primary parent and remove dividers. | |
198 | * | |
199 | * NOTE: we do this in a single transaction so we're never dividing the | |
200 | * primary parent by the extra dividers that were needed for the alt. | |
201 | */ | |
202 | ||
203 | writel(HIWORD_UPDATE(0, reg_data->div_core_mask, | |
204 | reg_data->div_core_shift) | | |
268aebaa XZ |
205 | HIWORD_UPDATE(reg_data->mux_core_main, |
206 | reg_data->mux_core_mask, | |
207 | reg_data->mux_core_shift), | |
f6fba5f6 HS |
208 | cpuclk->reg_base + reg_data->core_reg); |
209 | ||
210 | if (ndata->old_rate > ndata->new_rate) | |
211 | rockchip_cpuclk_set_dividers(cpuclk, rate); | |
212 | ||
a5e1baf7 | 213 | spin_unlock_irqrestore(cpuclk->lock, flags); |
f6fba5f6 HS |
214 | return 0; |
215 | } | |
216 | ||
217 | /* | |
218 | * This clock notifier is called when the frequency of the parent clock | |
219 | * of cpuclk is to be changed. This notifier handles the setting up all | |
220 | * the divider clocks, remux to temporary parent and handling the safe | |
221 | * frequency levels when using temporary parent. | |
222 | */ | |
223 | static int rockchip_cpuclk_notifier_cb(struct notifier_block *nb, | |
224 | unsigned long event, void *data) | |
225 | { | |
226 | struct clk_notifier_data *ndata = data; | |
227 | struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_nb(nb); | |
228 | int ret = 0; | |
229 | ||
230 | pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n", | |
231 | __func__, event, ndata->old_rate, ndata->new_rate); | |
232 | if (event == PRE_RATE_CHANGE) | |
233 | ret = rockchip_cpuclk_pre_rate_change(cpuclk, ndata); | |
234 | else if (event == POST_RATE_CHANGE) | |
235 | ret = rockchip_cpuclk_post_rate_change(cpuclk, ndata); | |
236 | ||
237 | return notifier_from_errno(ret); | |
238 | } | |
239 | ||
240 | struct clk *rockchip_clk_register_cpuclk(const char *name, | |
4a1caed3 | 241 | const char *const *parent_names, u8 num_parents, |
f6fba5f6 HS |
242 | const struct rockchip_cpuclk_reg_data *reg_data, |
243 | const struct rockchip_cpuclk_rate_table *rates, | |
244 | int nrates, void __iomem *reg_base, spinlock_t *lock) | |
245 | { | |
246 | struct rockchip_cpuclk *cpuclk; | |
247 | struct clk_init_data init; | |
248 | struct clk *clk, *cclk; | |
249 | int ret; | |
250 | ||
ea03835f JC |
251 | if (num_parents < 2) { |
252 | pr_err("%s: needs at least two parent clocks\n", __func__); | |
f6fba5f6 HS |
253 | return ERR_PTR(-EINVAL); |
254 | } | |
255 | ||
256 | cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL); | |
257 | if (!cpuclk) | |
258 | return ERR_PTR(-ENOMEM); | |
259 | ||
260 | init.name = name; | |
268aebaa | 261 | init.parent_names = &parent_names[reg_data->mux_core_main]; |
f6fba5f6 HS |
262 | init.num_parents = 1; |
263 | init.ops = &rockchip_cpuclk_ops; | |
264 | ||
265 | /* only allow rate changes when we have a rate table */ | |
266 | init.flags = (nrates > 0) ? CLK_SET_RATE_PARENT : 0; | |
267 | ||
268 | /* disallow automatic parent changes by ccf */ | |
269 | init.flags |= CLK_SET_RATE_NO_REPARENT; | |
270 | ||
271 | init.flags |= CLK_GET_RATE_NOCACHE; | |
272 | ||
273 | cpuclk->reg_base = reg_base; | |
274 | cpuclk->lock = lock; | |
275 | cpuclk->reg_data = reg_data; | |
276 | cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb; | |
277 | cpuclk->hw.init = &init; | |
278 | ||
268aebaa | 279 | cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]); |
f6fba5f6 | 280 | if (!cpuclk->alt_parent) { |
268aebaa XZ |
281 | pr_err("%s: could not lookup alternate parent: (%d)\n", |
282 | __func__, reg_data->mux_core_alt); | |
f6fba5f6 HS |
283 | ret = -EINVAL; |
284 | goto free_cpuclk; | |
285 | } | |
286 | ||
287 | ret = clk_prepare_enable(cpuclk->alt_parent); | |
288 | if (ret) { | |
289 | pr_err("%s: could not enable alternate parent\n", | |
290 | __func__); | |
291 | goto free_cpuclk; | |
292 | } | |
293 | ||
268aebaa | 294 | clk = __clk_lookup(parent_names[reg_data->mux_core_main]); |
f6fba5f6 | 295 | if (!clk) { |
268aebaa XZ |
296 | pr_err("%s: could not lookup parent clock: (%d) %s\n", |
297 | __func__, reg_data->mux_core_main, | |
298 | parent_names[reg_data->mux_core_main]); | |
f6fba5f6 | 299 | ret = -EINVAL; |
282312d1 | 300 | goto free_alt_parent; |
f6fba5f6 HS |
301 | } |
302 | ||
303 | ret = clk_notifier_register(clk, &cpuclk->clk_nb); | |
304 | if (ret) { | |
305 | pr_err("%s: failed to register clock notifier for %s\n", | |
306 | __func__, name); | |
282312d1 | 307 | goto free_alt_parent; |
f6fba5f6 HS |
308 | } |
309 | ||
310 | if (nrates > 0) { | |
311 | cpuclk->rate_count = nrates; | |
312 | cpuclk->rate_table = kmemdup(rates, | |
313 | sizeof(*rates) * nrates, | |
314 | GFP_KERNEL); | |
315 | if (!cpuclk->rate_table) { | |
316 | pr_err("%s: could not allocate memory for cpuclk rates\n", | |
317 | __func__); | |
318 | ret = -ENOMEM; | |
319 | goto unregister_notifier; | |
320 | } | |
321 | } | |
322 | ||
323 | cclk = clk_register(NULL, &cpuclk->hw); | |
3183c0d5 | 324 | if (IS_ERR(cclk)) { |
f6fba5f6 | 325 | pr_err("%s: could not register cpuclk %s\n", __func__, name); |
3183c0d5 | 326 | ret = PTR_ERR(cclk); |
f6fba5f6 HS |
327 | goto free_rate_table; |
328 | } | |
329 | ||
330 | return cclk; | |
331 | ||
332 | free_rate_table: | |
333 | kfree(cpuclk->rate_table); | |
334 | unregister_notifier: | |
335 | clk_notifier_unregister(clk, &cpuclk->clk_nb); | |
282312d1 SL |
336 | free_alt_parent: |
337 | clk_disable_unprepare(cpuclk->alt_parent); | |
f6fba5f6 HS |
338 | free_cpuclk: |
339 | kfree(cpuclk); | |
340 | return ERR_PTR(ret); | |
341 | } |