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clk: Remove io.h from clk-provider.h
[linux-block.git] / drivers / clk / renesas / r9a06g032-clocks.c
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4c3d8852
MP		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R9A09G032 clock driver
4 *
5 * Copyright (C) 2018 Renesas Electronics Europe Limited
6 *
7 * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
8 */
9
10#include <linux/clk.h>
11#include <linux/clk-provider.h>
12#include <linux/delay.h>
13#include <linux/init.h>
62e59c4e 14#include <linux/io.h>
4c3d8852
MP		 15#include <linux/kernel.h>
16#include <linux/math64.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21#include <linux/spinlock.h>
22#include <dt-bindings/clock/r9a06g032-sysctrl.h>
23
24struct r9a06g032_gate {
25 u16 gate, reset, ready, midle,
26 scon, mirack, mistat;
27};
28
29/* This is used to describe a clock for instantiation */
30struct r9a06g032_clkdesc {
31 const char *name;
32 uint32_t type: 3;
33 uint32_t index: 8;
34 uint32_t source : 8; /* source index + 1 (0 == none) */
35 /* these are used to populate the bitsel struct */
36 union {
37 struct r9a06g032_gate gate;
38 /* for dividers */
39 struct {
40 unsigned int div_min : 10, div_max : 10, reg: 10;
41 u16 div_table[4];
42 };
43 /* For fixed-factor ones */
44 struct {
45 u16 div, mul;
46 };
47 unsigned int factor;
48 unsigned int frequency;
49 /* for dual gate */
50 struct {
51 uint16_t group : 1, index: 3;
52 u16 sel, g1, r1, g2, r2;
53 } dual;
54 };
55} __packed;
56
57#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \
58 { .gate = _clk, .reset = _rst, \
59 .ready = _rdy, .midle = _midle, \
60 .scon = _scon, .mirack = _mirack, .mistat = _mistat }
61#define D_GATE(_idx, _n, _src, ...) \
62 { .type = K_GATE, .index = R9A06G032_##_idx, \
63 .source = 1 + R9A06G032_##_src, .name = _n, \
64 .gate = I_GATE(__VA_ARGS__), }
65#define D_ROOT(_idx, _n, _mul, _div) \
66 { .type = K_FFC, .index = R9A06G032_##_idx, .name = _n, \
67 .div = _div, .mul = _mul }
68#define D_FFC(_idx, _n, _src, _div) \
69 { .type = K_FFC, .index = R9A06G032_##_idx, \
70 .source = 1 + R9A06G032_##_src, .name = _n, \
71 .div = _div, .mul = 1}
72#define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) \
73 { .type = K_DIV, .index = R9A06G032_##_idx, \
74 .source = 1 + R9A06G032_##_src, .name = _n, \
75 .reg = _reg, .div_min = _min, .div_max = _max, \
76 .div_table = { __VA_ARGS__ } }
77#define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \
78 { .type = K_DUALGATE, .index = R9A06G032_##_idx, \
79 .source = 1 + R9A06G032_##_src, .name = _n, \
80 .dual = { .group = _g, .index = _gi, \
81 .g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, }
82
83enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE };
84
85/* Internal clock IDs */
86#define R9A06G032_CLKOUT 0
87#define R9A06G032_CLKOUT_D10 2
88#define R9A06G032_CLKOUT_D16 3
89#define R9A06G032_CLKOUT_D160 4
90#define R9A06G032_CLKOUT_D1OR2 5
91#define R9A06G032_CLKOUT_D20 6
92#define R9A06G032_CLKOUT_D40 7
93#define R9A06G032_CLKOUT_D5 8
94#define R9A06G032_CLKOUT_D8 9
95#define R9A06G032_DIV_ADC 10
96#define R9A06G032_DIV_I2C 11
97#define R9A06G032_DIV_NAND 12
98#define R9A06G032_DIV_P1_PG 13
99#define R9A06G032_DIV_P2_PG 14
100#define R9A06G032_DIV_P3_PG 15
101#define R9A06G032_DIV_P4_PG 16
102#define R9A06G032_DIV_P5_PG 17
103#define R9A06G032_DIV_P6_PG 18
104#define R9A06G032_DIV_QSPI0 19
105#define R9A06G032_DIV_QSPI1 20
106#define R9A06G032_DIV_REF_SYNC 21
107#define R9A06G032_DIV_SDIO0 22
108#define R9A06G032_DIV_SDIO1 23
109#define R9A06G032_DIV_SWITCH 24
110#define R9A06G032_DIV_UART 25
111#define R9A06G032_DIV_MOTOR 64
112#define R9A06G032_CLK_DDRPHY_PLLCLK_D4 78
113#define R9A06G032_CLK_ECAT100_D4 79
114#define R9A06G032_CLK_HSR100_D2 80
115#define R9A06G032_CLK_REF_SYNC_D4 81
116#define R9A06G032_CLK_REF_SYNC_D8 82
117#define R9A06G032_CLK_SERCOS100_D2 83
118#define R9A06G032_DIV_CA7 84
119
120#define R9A06G032_UART_GROUP_012 154
121#define R9A06G032_UART_GROUP_34567 155
122
123#define R9A06G032_CLOCK_COUNT (R9A06G032_UART_GROUP_34567 + 1)
124
125static const struct r9a06g032_clkdesc r9a06g032_clocks[] __initconst = {
126 D_ROOT(CLKOUT, "clkout", 25, 1),
127 D_ROOT(CLK_PLL_USB, "clk_pll_usb", 12, 10),
128 D_FFC(CLKOUT_D10, "clkout_d10", CLKOUT, 10),
129 D_FFC(CLKOUT_D16, "clkout_d16", CLKOUT, 16),
130 D_FFC(CLKOUT_D160, "clkout_d160", CLKOUT, 160),
131 D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2),
132 D_FFC(CLKOUT_D20, "clkout_d20", CLKOUT, 20),
133 D_FFC(CLKOUT_D40, "clkout_d40", CLKOUT, 40),
134 D_FFC(CLKOUT_D5, "clkout_d5", CLKOUT, 5),
135 D_FFC(CLKOUT_D8, "clkout_d8", CLKOUT, 8),
136 D_DIV(DIV_ADC, "div_adc", CLKOUT, 77, 50, 250),
137 D_DIV(DIV_I2C, "div_i2c", CLKOUT, 78, 12, 16),
138 D_DIV(DIV_NAND, "div_nand", CLKOUT, 82, 12, 32),
139 D_DIV(DIV_P1_PG, "div_p1_pg", CLKOUT, 68, 12, 200),
140 D_DIV(DIV_P2_PG, "div_p2_pg", CLKOUT, 62, 12, 128),
141 D_DIV(DIV_P3_PG, "div_p3_pg", CLKOUT, 64, 8, 128),
142 D_DIV(DIV_P4_PG, "div_p4_pg", CLKOUT, 66, 8, 128),
143 D_DIV(DIV_P5_PG, "div_p5_pg", CLKOUT, 71, 10, 40),
144 D_DIV(DIV_P6_PG, "div_p6_pg", CLKOUT, 18, 12, 64),
145 D_DIV(DIV_QSPI0, "div_qspi0", CLKOUT, 73, 3, 7),
146 D_DIV(DIV_QSPI1, "div_qspi1", CLKOUT, 25, 3, 7),
147 D_DIV(DIV_REF_SYNC, "div_ref_sync", CLKOUT, 56, 2, 16, 2, 4, 8, 16),
148 D_DIV(DIV_SDIO0, "div_sdio0", CLKOUT, 74, 20, 128),
149 D_DIV(DIV_SDIO1, "div_sdio1", CLKOUT, 75, 20, 128),
150 D_DIV(DIV_SWITCH, "div_switch", CLKOUT, 37, 5, 40),
151 D_DIV(DIV_UART, "div_uart", CLKOUT, 79, 12, 128),
152 D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, 0x749, 0x74a, 0x74b, 0, 0xae3, 0, 0),
153 D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, 0x74c, 0x74d, 0x74e, 0, 0xae4, 0, 0),
154 D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, 0x74f, 0x750, 0x751, 0, 0xae5, 0, 0),
155 D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, 0x752, 0x753, 0x754, 0, 0xae6, 0, 0),
156 D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, 0x755, 0x756, 0x757, 0, 0xae7, 0, 0),
157 D_GATE(CLK_ADC, "clk_adc", DIV_ADC, 0x1ea, 0x1eb, 0, 0, 0, 0, 0),
158 D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, 0x405, 0, 0, 0, 0, 0, 0),
159 D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, 0x483, 0, 0, 0, 0, 0, 0),
160 D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, 0x1e6, 0x1e7, 0, 0, 0, 0, 0),
161 D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, 0x1e8, 0x1e9, 0, 0, 0, 0, 0),
162 D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, 0x342, 0, 0, 0, 0, 0, 0),
163 D_GATE(CLK_NAND, "clk_nand", DIV_NAND, 0x284, 0x285, 0, 0, 0, 0, 0),
164 D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, 0x774, 0x775, 0, 0, 0, 0, 0),
165 D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, 0x862, 0x863, 0, 0, 0, 0, 0),
166 D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, 0x864, 0x865, 0, 0, 0, 0, 0),
167 D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, 0x866, 0x867, 0, 0, 0, 0, 0),
168 D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, 0x824, 0x825, 0, 0, 0, 0, 0),
169 D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, 0x826, 0x827, 0, 0, 0, 0, 0),
170 D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, 0x8a0, 0x8a1, 0x8a2, 0, 0xb60, 0, 0),
171 D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, 0x8a3, 0x8a4, 0x8a5, 0, 0xb61, 0, 0),
172 D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, 0x8a6, 0x8a7, 0x8a8, 0, 0xb62, 0, 0),
173 D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, 0x8a9, 0x8aa, 0x8ab, 0, 0xb63, 0, 0),
1addd6d5 174 D_GATE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, 0xe6, 0, 0, 0, 0, 0, 0),
4c3d8852
MP		 175 D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, 0x2a4, 0x2a5, 0, 0, 0, 0, 0),
176 D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, 0x484, 0x485, 0, 0, 0, 0, 0),
177 D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, 0x340, 0, 0, 0, 0, 0, 0),
178 D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, 0x341, 0, 0, 0, 0, 0, 0),
179 D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, 0x64, 0, 0, 0, 0, 0, 0),
180 D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, 0x644, 0, 0, 0, 0, 0, 0),
181 D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, 0x425, 0, 0, 0, 0, 0, 0),
182 D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, 0x860, 0x861, 0, 0, 0, 0, 0),
183 D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, 0x7e0, 0x7e1, 0, 0, 0, 0, 0),
184 D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, 0x7e2, 0x7e3, 0, 0, 0, 0, 0),
185 D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, 0x7e4, 0x7e5, 0, 0, 0, 0, 0),
186 D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, 0x7e6, 0x7e7, 0, 0, 0, 0, 0),
187 D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, 0x820, 0x821, 0, 0, 0, 0, 0),
188 D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, 0x822, 0x823, 0, 0, 0, 0, 0),
189 D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, 0x982, 0x983, 0, 0, 0, 0, 0),
190 D_DIV(DIV_MOTOR, "div_motor", CLKOUT_D5, 84, 2, 8),
191 D_GATE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, 0x400, 0x401, 0, 0x402, 0, 0x440, 0x441),
192 D_GATE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, 0x740, 0x741, 0x742, 0, 0xae0, 0, 0),
193 D_GATE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, 0x420, 0x422, 0, 0x421, 0, 0x460, 0x461),
194 D_GATE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, 0x8c3, 0x8c4, 0x8c5, 0, 0xb41, 0, 0),
195 D_GATE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, 0x8c6, 0x8c7, 0x8c8, 0, 0xb42, 0, 0),
196 D_GATE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, 0x8c9, 0x8ca, 0x8cb, 0, 0xb43, 0, 0),
197 D_GATE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, 0x743, 0x744, 0x745, 0, 0xae1, 0, 0),
198 D_GATE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, 0x746, 0x747, 0x748, 0, 0xae2, 0, 0),
199 D_GATE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, 0xe3, 0, 0, 0xe4, 0, 0x102, 0x103),
200 D_GATE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, 0xe0, 0xe1, 0, 0xe2, 0, 0x100, 0x101),
201 D_GATE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, 0xe5, 0, 0, 0, 0, 0, 0),
202 D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, 0x78c, 0x78d, 0, 0x78e, 0, 0xb04, 0xb05),
203 D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, 0x789, 0x78a, 0x78b, 0, 0xb03, 0, 0),
204 D_FFC(CLK_DDRPHY_PLLCLK_D4, "clk_ddrphy_pllclk_d4", CLK_DDRPHY_PLLCLK, 4),
205 D_FFC(CLK_ECAT100_D4, "clk_ecat100_d4", CLK_ECAT100, 4),
206 D_FFC(CLK_HSR100_D2, "clk_hsr100_d2", CLK_HSR100, 2),
207 D_FFC(CLK_REF_SYNC_D4, "clk_ref_sync_d4", CLK_REF_SYNC, 4),
208 D_FFC(CLK_REF_SYNC_D8, "clk_ref_sync_d8", CLK_REF_SYNC, 8),
209 D_FFC(CLK_SERCOS100_D2, "clk_sercos100_d2", CLK_SERCOS100, 2),
210 D_DIV(DIV_CA7, "div_ca7", CLK_REF_SYNC, 57, 1, 4, 1, 2, 4),
211 D_GATE(HCLK_CAN0, "hclk_can0", CLK_48, 0x783, 0x784, 0x785, 0, 0xb01, 0, 0),
212 D_GATE(HCLK_CAN1, "hclk_can1", CLK_48, 0x786, 0x787, 0x788, 0, 0xb02, 0, 0),
213 D_GATE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, 0x1ef, 0x1f0, 0x1f1, 0, 0, 0, 0),
214 D_GATE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, 0x1ec, 0x1ed, 0x1ee, 0, 0, 0, 0),
215 D_GATE(HCLK_RSV, "hclk_rsv", CLK_48, 0x780, 0x781, 0x782, 0, 0xb00, 0, 0),
216 D_GATE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, 0x1e0, 0x1e1, 0x1e2, 0, 0, 0, 0),
217 D_GATE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, 0x1e3, 0x1e4, 0x1e5, 0, 0, 0, 0),
218 D_DIV(RTOS_MDC, "rtos_mdc", CLK_REF_SYNC, 100, 80, 640, 80, 160, 320, 640),
219 D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, 0xba0, 0xba1, 0, 0xba2, 0, 0xbc0, 0xbc1),
220 D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, 0x323, 0x324, 0, 0, 0, 0, 0),
221 D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, 0x403, 0x404, 0, 0, 0, 0, 0),
222 D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, 0x484, 0x485, 0, 0, 0, 0, 0),
223 D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, 0xc60, 0xc61, 0, 0, 0, 0, 0),
224 D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, 0x424, 0x423, 0, 0, 0, 0, 0),
225 D_GATE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, 0x1af, 0x1b0, 0x1b1, 0, 0, 0, 0),
226 D_GATE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, 0xc20, 0xc21, 0xc22, 0, 0, 0, 0),
227 D_GATE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, 0x123, 0x124, 0x125, 0, 0x142, 0, 0),
228 D_GATE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, 0x120, 0x121, 0, 0x122, 0, 0x140, 0x141),
229 D_GATE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, 0x320, 0x322, 0, 0x321, 0, 0x3a0, 0x3a1),
230 D_GATE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, 0x260, 0x261, 0x262, 0x263, 0x2c0, 0x2c1, 0x2c2),
231 D_GATE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, 0x264, 0x265, 0x266, 0x267, 0x2c3, 0x2c4, 0x2c5),
232 D_GATE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, 0x360, 0x361, 0x362, 0x363, 0x3c0, 0x3c1, 0x3c2),
233 D_GATE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, 0x380, 0x381, 0x382, 0x383, 0x3e0, 0x3e1, 0x3e2),
234 D_GATE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, 0x212, 0x213, 0x214, 0, 0, 0, 0),
235 D_GATE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, 0x215, 0x216, 0x217, 0, 0, 0, 0),
236 D_GATE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, 0x229, 0x22a, 0x22b, 0, 0, 0, 0),
237 D_GATE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, 0x480, 0x482, 0, 0x481, 0, 0x4c0, 0x4c1),
238 D_GATE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, 0x1a9, 0x1aa, 0x1ab, 0, 0, 0, 0),
239 D_GATE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, 0x1ac, 0x1ad, 0x1ae, 0, 0, 0, 0),
240 D_GATE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, 0x7a0, 0x7a1, 0x7a2, 0, 0xb20, 0, 0),
241 D_GATE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, 0x164, 0x165, 0x166, 0, 0x183, 0, 0),
242 D_GATE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, 0x160, 0x161, 0x162, 0x163, 0x180, 0x181, 0x182),
243 D_GATE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, 0x280, 0x281, 0x282, 0x283, 0x2e0, 0x2e1, 0x2e2),
244 D_GATE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, 0x7ac, 0x7ad, 0, 0x7ae, 0, 0xb24, 0xb25),
245 D_GATE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, 0x22c, 0x22d, 0x22e, 0, 0, 0, 0),
246 D_GATE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, 0x22f, 0x230, 0x231, 0, 0, 0, 0),
247 D_GATE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, 0x7a6, 0x7a7, 0x7a8, 0, 0xb22, 0, 0),
248 D_GATE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, 0x7a9, 0x7aa, 0x7ab, 0, 0xb23, 0, 0),
249 D_GATE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, 0x2a0, 0x2a1, 0x2a2, 0x2a3, 0x300, 0x301, 0x302),
250 D_GATE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, 0x480, 0x481, 0x482, 0x483, 0x4c0, 0x4c1, 0x4c2),
251 D_GATE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, 0xaa0, 0xaa1, 0xaa2, 0, 0xb80, 0, 0),
252 D_GATE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, 0xa00, 0, 0, 0, 0, 0, 0),
253 D_GATE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, 0x60, 0x61, 0x62, 0x63, 0x80, 0x81, 0x82),
254 D_GATE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, 0x640, 0x641, 0x642, 0x643, 0x660, 0x661, 0x662),
255 D_GATE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, 0x7a3, 0x7a4, 0x7a5, 0, 0xb21, 0, 0),
256 D_GATE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, 0x200, 0x201, 0x202, 0, 0, 0, 0),
257 D_GATE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, 0x203, 0x204, 0x205, 0, 0, 0, 0),
258 D_GATE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, 0x206, 0x207, 0x208, 0, 0, 0, 0),
259 D_GATE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, 0x209, 0x20a, 0x20b, 0, 0, 0, 0),
260 D_GATE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, 0x20c, 0x20d, 0x20e, 0, 0, 0, 0),
261 D_GATE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, 0x20f, 0x210, 0x211, 0, 0, 0, 0),
262 D_GATE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, 0x980, 0, 0x981, 0, 0, 0, 0),
263 D_GATE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, 0xc40, 0xc41, 0xc42, 0, 0, 0, 0),
264 D_GATE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, 0x1a0, 0x1a1, 0x1a2, 0, 0, 0, 0),
265 D_GATE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, 0x1a3, 0x1a4, 0x1a5, 0, 0, 0, 0),
266 D_GATE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, 0x1a6, 0x1a7, 0x1a8, 0, 0, 0, 0),
267 D_GATE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, 0x218, 0x219, 0x21a, 0, 0, 0, 0),
268 D_GATE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, 0x21b, 0x21c, 0x21d, 0, 0, 0, 0),
269 D_GATE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, 0x220, 0x221, 0x222, 0, 0, 0, 0),
270 D_GATE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, 0x223, 0x224, 0x225, 0, 0, 0, 0),
271 D_GATE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, 0x226, 0x227, 0x228, 0, 0, 0, 0),
272 /*
273 * These are not hardware clocks, but are needed to handle the special
274 * case where we have a 'selector bit' that doesn't just change the
275 * parent for a clock, but also the gate it's suposed to use.
276 */
277 {
278 .index = R9A06G032_UART_GROUP_012,
279 .name = "uart_group_012",
280 .type = K_BITSEL,
281 .source = 1 + R9A06G032_DIV_UART,
282 /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
283 .dual.sel = ((0xec / 4) << 5) | 24,
284 .dual.group = 0,
285 },
286 {
287 .index = R9A06G032_UART_GROUP_34567,
288 .name = "uart_group_34567",
289 .type = K_BITSEL,
290 .source = 1 + R9A06G032_DIV_P2_PG,
291 /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
292 .dual.sel = ((0x34 / 4) << 5) | 30,
293 .dual.group = 1,
294 },
295 D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
296 D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 1, 0x1b6, 0x1b7, 0x1b8, 0x1b9),
297 D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 2, 0x1ba, 0x1bb, 0x1bc, 0x1bd),
298 D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0, 0x760, 0x761, 0x762, 0x763),
299 D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 1, 0x764, 0x765, 0x766, 0x767),
300 D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 2, 0x768, 0x769, 0x76a, 0x76b),
301 D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 3, 0x76c, 0x76d, 0x76e, 0x76f),
302 D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 4, 0x770, 0x771, 0x772, 0x773),
303};
304
305struct r9a06g032_priv {
306 struct clk_onecell_data data;
307 spinlock_t lock; /* protects concurent access to gates */
308 void __iomem *reg;
309};
310
311/* register/bit pairs are encoded as an uint16_t */
312static void
313clk_rdesc_set(struct r9a06g032_priv *clocks,
314 u16 one, unsigned int on)
315{
316 u32 __iomem *reg = clocks->reg + (4 * (one >> 5));
317 u32 val = readl(reg);
318
319 val = (val & ~(1U << (one & 0x1f))) | ((!!on) << (one & 0x1f));
320 writel(val, reg);
321}
322
323static int
324clk_rdesc_get(struct r9a06g032_priv *clocks,
325 uint16_t one)
326{
327 u32 __iomem *reg = clocks->reg + (4 * (one >> 5));
328 u32 val = readl(reg);
329
330 return !!(val & (1U << (one & 0x1f)));
331}
332
333/*
334 * This implements the R9A09G032 clock gate 'driver'. We cannot use the system's
335 * clock gate framework as the gates on the R9A09G032 have a special enabling
336 * sequence, therefore we use this little proxy.
337 */
338struct r9a06g032_clk_gate {
339 struct clk_hw hw;
340 struct r9a06g032_priv *clocks;
341 u16 index;
342
343 struct r9a06g032_gate gate;
344};
345
346#define to_r9a06g032_gate(_hw) container_of(_hw, struct r9a06g032_clk_gate, hw)
347
348static void
349r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks,
350 struct r9a06g032_gate *g, int on)
351{
352 unsigned long flags;
353
354 WARN_ON(!g->gate);
355
356 spin_lock_irqsave(&clocks->lock, flags);
357 clk_rdesc_set(clocks, g->gate, on);
358 /* De-assert reset */
359 if (g->reset)
360 clk_rdesc_set(clocks, g->reset, 1);
361 spin_unlock_irqrestore(&clocks->lock, flags);
362
363 /* Hardware manual recommends 5us delay after enabling clock & reset */
364 udelay(5);
365
366 /* If the peripheral is memory mapped (i.e. an AXI slave), there is an
367 * associated SLVRDY bit in the System Controller that needs to be set
368 * so that the FlexWAY bus fabric passes on the read/write requests.
369 */
370 if (g->ready || g->midle) {
371 spin_lock_irqsave(&clocks->lock, flags);
372 if (g->ready)
373 clk_rdesc_set(clocks, g->ready, on);
374 /* Clear 'Master Idle Request' bit */
375 if (g->midle)
376 clk_rdesc_set(clocks, g->midle, !on);
377 spin_unlock_irqrestore(&clocks->lock, flags);
378 }
379 /* Note: We don't wait for FlexWAY Socket Connection signal */
380}
381
382static int r9a06g032_clk_gate_enable(struct clk_hw *hw)
383{
384 struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
385
386 r9a06g032_clk_gate_set(g->clocks, &g->gate, 1);
387 return 0;
388}
389
390static void r9a06g032_clk_gate_disable(struct clk_hw *hw)
391{
392 struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
393
394 r9a06g032_clk_gate_set(g->clocks, &g->gate, 0);
395}
396
397static int r9a06g032_clk_gate_is_enabled(struct clk_hw *hw)
398{
399 struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
400
401 /* if clock is in reset, the gate might be on, and still not 'be' on */
402 if (g->gate.reset && !clk_rdesc_get(g->clocks, g->gate.reset))
403 return 0;
404
405 return clk_rdesc_get(g->clocks, g->gate.gate);
406}
407
408static const struct clk_ops r9a06g032_clk_gate_ops = {
409 .enable = r9a06g032_clk_gate_enable,
410 .disable = r9a06g032_clk_gate_disable,
411 .is_enabled = r9a06g032_clk_gate_is_enabled,
412};
413
414static struct clk *
415r9a06g032_register_gate(struct r9a06g032_priv *clocks,
416 const char *parent_name,
417 const struct r9a06g032_clkdesc *desc)
418{
419 struct clk *clk;
420 struct r9a06g032_clk_gate *g;
421 struct clk_init_data init;
422
423 g = kzalloc(sizeof(*g), GFP_KERNEL);
424 if (!g)
425 return NULL;
426
427 init.name = desc->name;
428 init.ops = &r9a06g032_clk_gate_ops;
ddbae665 429 init.flags = CLK_SET_RATE_PARENT;
4c3d8852
MP		 430 init.parent_names = parent_name ? &parent_name : NULL;
431 init.num_parents = parent_name ? 1 : 0;
432
433 g->clocks = clocks;
434 g->index = desc->index;
435 g->gate = desc->gate;
436 g->hw.init = &init;
437
438 /*
439 * important here, some clocks are already in use by the CM3, we
440 * have to assume they are not Linux's to play with and try to disable
441 * at the end of the boot!
442 */
443 if (r9a06g032_clk_gate_is_enabled(&g->hw)) {
444 init.flags |= CLK_IS_CRITICAL;
445 pr_debug("%s was enabled, making read-only\n", desc->name);
446 }
447
448 clk = clk_register(NULL, &g->hw);
449 if (IS_ERR(clk)) {
450 kfree(g);
451 return NULL;
452 }
453 return clk;
454}
455
456struct r9a06g032_clk_div {
457 struct clk_hw hw;
458 struct r9a06g032_priv *clocks;
459 u16 index;
460 u16 reg;
461 u16 min, max;
462 u8 table_size;
463 u16 table[8]; /* we know there are no more than 8 */
464};
465
466#define to_r9a06g032_div(_hw) \
467 container_of(_hw, struct r9a06g032_clk_div, hw)
468
469static unsigned long
470r9a06g032_div_recalc_rate(struct clk_hw *hw,
471 unsigned long parent_rate)
472{
473 struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
474 u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);
475 u32 div = readl(reg);
476
477 if (div < clk->min)
478 div = clk->min;
479 else if (div > clk->max)
480 div = clk->max;
481 return DIV_ROUND_UP(parent_rate, div);
482}
483
484/*
485 * Attempts to find a value that is in range of min,max,
486 * and if a table of set dividers was specified for this
487 * register, try to find the fixed divider that is the closest
488 * to the target frequency
489 */
490static long
491r9a06g032_div_clamp_div(struct r9a06g032_clk_div *clk,
492 unsigned long rate, unsigned long prate)
493{
494 /* + 1 to cope with rates that have the remainder dropped */
495 u32 div = DIV_ROUND_UP(prate, rate + 1);
496 int i;
497
498 if (div <= clk->min)
499 return clk->min;
500 if (div >= clk->max)
501 return clk->max;
502
503 for (i = 0; clk->table_size && i < clk->table_size - 1; i++) {
504 if (div >= clk->table[i] && div <= clk->table[i + 1]) {
505 unsigned long m = rate -
506 DIV_ROUND_UP(prate, clk->table[i]);
507 unsigned long p =
508 DIV_ROUND_UP(prate, clk->table[i + 1]) -
509 rate;
510 /*
511 * select the divider that generates
512 * the value closest to the ideal frequency
513 */
514 div = p >= m ? clk->table[i] : clk->table[i + 1];
515 return div;
516 }
517 }
518 return div;
519}
520
521static long
522r9a06g032_div_round_rate(struct clk_hw *hw,
523 unsigned long rate, unsigned long *prate)
524{
525 struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
526 u32 div = DIV_ROUND_UP(*prate, rate);
527
528 pr_devel("%s %pC %ld (prate %ld) (wanted div %u)\n", __func__,
529 hw->clk, rate, *prate, div);
530 pr_devel(" min %d (%ld) max %d (%ld)\n",
531 clk->min, DIV_ROUND_UP(*prate, clk->min),
532 clk->max, DIV_ROUND_UP(*prate, clk->max));
533
534 div = r9a06g032_div_clamp_div(clk, rate, *prate);
535 /*
536 * this is a hack. Currently the serial driver asks for a clock rate
537 * that is 16 times the baud rate -- and that is wildly outside the
538 * range of the UART divider, somehow there is no provision for that
539 * case of 'let the divider as is if outside range'.
540 * The serial driver *shouldn't* play with these clocks anyway, there's
541 * several uarts attached to this divider, and changing this impacts
542 * everyone.
543 */
ee02950d
PE		 544 if (clk->index == R9A06G032_DIV_UART ||
545 clk->index == R9A06G032_DIV_P2_PG) {
4c3d8852
MP		 546 pr_devel("%s div uart hack!\n", __func__);
547 return clk_get_rate(hw->clk);
548 }
549 pr_devel("%s %pC %ld / %u = %ld\n", __func__, hw->clk,
550 *prate, div, DIV_ROUND_UP(*prate, div));
551 return DIV_ROUND_UP(*prate, div);
552}
553
554static int
555r9a06g032_div_set_rate(struct clk_hw *hw,
556 unsigned long rate, unsigned long parent_rate)
557{
558 struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
559 /* + 1 to cope with rates that have the remainder dropped */
560 u32 div = DIV_ROUND_UP(parent_rate, rate + 1);
561 u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);
562
563 pr_devel("%s %pC rate %ld parent %ld div %d\n", __func__, hw->clk,
564 rate, parent_rate, div);
565
566 /*
567 * Need to write the bit 31 with the divider value to
568 * latch it. Technically we should wait until it has been
569 * cleared too.
570 * TODO: Find whether this callback is sleepable, in case
571 * the hardware /does/ require some sort of spinloop here.
572 */
573 writel(div | BIT(31), reg);
574
575 return 0;
576}
577
578static const struct clk_ops r9a06g032_clk_div_ops = {
579 .recalc_rate = r9a06g032_div_recalc_rate,
580 .round_rate = r9a06g032_div_round_rate,
581 .set_rate = r9a06g032_div_set_rate,
582};
583
584static struct clk *
585r9a06g032_register_div(struct r9a06g032_priv *clocks,
586 const char *parent_name,
587 const struct r9a06g032_clkdesc *desc)
588{
589 struct r9a06g032_clk_div *div;
590 struct clk *clk;
591 struct clk_init_data init;
592 unsigned int i;
593
594 div = kzalloc(sizeof(*div), GFP_KERNEL);
595 if (!div)
596 return NULL;
597
598 init.name = desc->name;
599 init.ops = &r9a06g032_clk_div_ops;
ddbae665 600 init.flags = CLK_SET_RATE_PARENT;
4c3d8852
MP		 601 init.parent_names = parent_name ? &parent_name : NULL;
602 init.num_parents = parent_name ? 1 : 0;
603
604 div->clocks = clocks;
605 div->index = desc->index;
606 div->reg = desc->reg;
607 div->hw.init = &init;
608 div->min = desc->div_min;
609 div->max = desc->div_max;
610 /* populate (optional) divider table fixed values */
611 for (i = 0; i < ARRAY_SIZE(div->table) &&
612 i < ARRAY_SIZE(desc->div_table) && desc->div_table[i]; i++) {
613 div->table[div->table_size++] = desc->div_table[i];
614 }
615
616 clk = clk_register(NULL, &div->hw);
617 if (IS_ERR(clk)) {
618 kfree(div);
619 return NULL;
620 }
621 return clk;
622}
623
624/*
625 * This clock provider handles the case of the R9A06G032 where you have
626 * peripherals that have two potential clock source and two gates, one for
627 * each of the clock source - the used clock source (for all sub clocks)
628 * is selected by a single bit.
629 * That single bit affects all sub-clocks, and therefore needs to change the
630 * active gate (and turn the others off) and force a recalculation of the rates.
631 *
632 * This implements two clock providers, one 'bitselect' that
633 * handles the switch between both parents, and another 'dualgate'
634 * that knows which gate to poke at, depending on the parent's bit position.
635 */
636struct r9a06g032_clk_bitsel {
637 struct clk_hw hw;
638 struct r9a06g032_priv *clocks;
639 u16 index;
640 u16 selector; /* selector register + bit */
641};
642
643#define to_clk_bitselect(_hw) \
644 container_of(_hw, struct r9a06g032_clk_bitsel, hw)
645
646static u8 r9a06g032_clk_mux_get_parent(struct clk_hw *hw)
647{
648 struct r9a06g032_clk_bitsel *set = to_clk_bitselect(hw);
649
650 return clk_rdesc_get(set->clocks, set->selector);
651}
652
653static int r9a06g032_clk_mux_set_parent(struct clk_hw *hw, u8 index)
654{
655 struct r9a06g032_clk_bitsel *set = to_clk_bitselect(hw);
656
657 /* a single bit in the register selects one of two parent clocks */
658 clk_rdesc_set(set->clocks, set->selector, !!index);
659
660 return 0;
661}
662
663static const struct clk_ops clk_bitselect_ops = {
664 .get_parent = r9a06g032_clk_mux_get_parent,
665 .set_parent = r9a06g032_clk_mux_set_parent,
666};
667
668static struct clk *
669r9a06g032_register_bitsel(struct r9a06g032_priv *clocks,
670 const char *parent_name,
671 const struct r9a06g032_clkdesc *desc)
672{
673 struct clk *clk;
674 struct r9a06g032_clk_bitsel *g;
675 struct clk_init_data init;
676 const char *names[2];
677
678 /* allocate the gate */
679 g = kzalloc(sizeof(*g), GFP_KERNEL);
680 if (!g)
681 return NULL;
682
683 names[0] = parent_name;
684 names[1] = "clk_pll_usb";
685
686 init.name = desc->name;
687 init.ops = &clk_bitselect_ops;
ddbae665 688 init.flags = CLK_SET_RATE_PARENT;
4c3d8852
MP		 689 init.parent_names = names;
690 init.num_parents = 2;
691
692 g->clocks = clocks;
693 g->index = desc->index;
694 g->selector = desc->dual.sel;
695 g->hw.init = &init;
696
697 clk = clk_register(NULL, &g->hw);
698 if (IS_ERR(clk)) {
699 kfree(g);
700 return NULL;
701 }
702 return clk;
703}
704
705struct r9a06g032_clk_dualgate {
706 struct clk_hw hw;
707 struct r9a06g032_priv *clocks;
708 u16 index;
709 u16 selector; /* selector register + bit */
710 struct r9a06g032_gate gate[2];
711};
712
713#define to_clk_dualgate(_hw) \
714 container_of(_hw, struct r9a06g032_clk_dualgate, hw)
715
716static int
717r9a06g032_clk_dualgate_setenable(struct r9a06g032_clk_dualgate *g, int enable)
718{
719 u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);
720
721 /* we always turn off the 'other' gate, regardless */
722 r9a06g032_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0);
723 r9a06g032_clk_gate_set(g->clocks, &g->gate[sel_bit], enable);
724
725 return 0;
726}
727
728static int r9a06g032_clk_dualgate_enable(struct clk_hw *hw)
729{
730 struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw);
731
732 r9a06g032_clk_dualgate_setenable(gate, 1);
733
734 return 0;
735}
736
737static void r9a06g032_clk_dualgate_disable(struct clk_hw *hw)
738{
739 struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw);
740
741 r9a06g032_clk_dualgate_setenable(gate, 0);
742}
743
744static int r9a06g032_clk_dualgate_is_enabled(struct clk_hw *hw)
745{
746 struct r9a06g032_clk_dualgate *g = to_clk_dualgate(hw);
747 u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);
748
749 return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate);
750}
751
752static const struct clk_ops r9a06g032_clk_dualgate_ops = {
753 .enable = r9a06g032_clk_dualgate_enable,
754 .disable = r9a06g032_clk_dualgate_disable,
755 .is_enabled = r9a06g032_clk_dualgate_is_enabled,
756};
757
758static struct clk *
759r9a06g032_register_dualgate(struct r9a06g032_priv *clocks,
760 const char *parent_name,
761 const struct r9a06g032_clkdesc *desc,
762 uint16_t sel)
763{
764 struct r9a06g032_clk_dualgate *g;
765 struct clk *clk;
766 struct clk_init_data init;
767
768 /* allocate the gate */
769 g = kzalloc(sizeof(*g), GFP_KERNEL);
770 if (!g)
771 return NULL;
772 g->clocks = clocks;
773 g->index = desc->index;
774 g->selector = sel;
775 g->gate[0].gate = desc->dual.g1;
776 g->gate[0].reset = desc->dual.r1;
777 g->gate[1].gate = desc->dual.g2;
778 g->gate[1].reset = desc->dual.r2;
779
780 init.name = desc->name;
781 init.ops = &r9a06g032_clk_dualgate_ops;
ddbae665 782 init.flags = CLK_SET_RATE_PARENT;
4c3d8852
MP		 783 init.parent_names = &parent_name;
784 init.num_parents = 1;
785 g->hw.init = &init;
786 /*
787 * important here, some clocks are already in use by the CM3, we
788 * have to assume they are not Linux's to play with and try to disable
789 * at the end of the boot!
790 */
791 if (r9a06g032_clk_dualgate_is_enabled(&g->hw)) {
792 init.flags |= CLK_IS_CRITICAL;
793 pr_debug("%s was enabled, making read-only\n", desc->name);
794 }
795
796 clk = clk_register(NULL, &g->hw);
797 if (IS_ERR(clk)) {
798 kfree(g);
799 return NULL;
800 }
801 return clk;
802}
803
804static void r9a06g032_clocks_del_clk_provider(void *data)
805{
806 of_clk_del_provider(data);
807}
808
809static int __init r9a06g032_clocks_probe(struct platform_device *pdev)
810{
811 struct device *dev = &pdev->dev;
812 struct device_node *np = dev->of_node;
813 struct r9a06g032_priv *clocks;
814 struct clk **clks;
815 struct clk *mclk;
816 unsigned int i;
817 u16 uart_group_sel[2];
818 int error;
819
820 clocks = devm_kzalloc(dev, sizeof(*clocks), GFP_KERNEL);
821 clks = devm_kcalloc(dev, R9A06G032_CLOCK_COUNT, sizeof(struct clk *),
822 GFP_KERNEL);
823 if (!clocks || !clks)
824 return -ENOMEM;
825
826 spin_lock_init(&clocks->lock);
827
828 clocks->data.clks = clks;
829 clocks->data.clk_num = R9A06G032_CLOCK_COUNT;
830
831 mclk = devm_clk_get(dev, "mclk");
832 if (IS_ERR(mclk))
833 return PTR_ERR(mclk);
834
835 clocks->reg = of_iomap(np, 0);
836 if (WARN_ON(!clocks->reg))
837 return -ENOMEM;
838 for (i = 0; i < ARRAY_SIZE(r9a06g032_clocks); ++i) {
839 const struct r9a06g032_clkdesc *d = &r9a06g032_clocks[i];
840 const char *parent_name = d->source ?
841 __clk_get_name(clocks->data.clks[d->source - 1]) :
842 __clk_get_name(mclk);
843 struct clk *clk = NULL;
844
845 switch (d->type) {
846 case K_FFC:
847 clk = clk_register_fixed_factor(NULL, d->name,
848 parent_name, 0,
849 d->mul, d->div);
850 break;
851 case K_GATE:
852 clk = r9a06g032_register_gate(clocks, parent_name, d);
853 break;
854 case K_DIV:
855 clk = r9a06g032_register_div(clocks, parent_name, d);
856 break;
857 case K_BITSEL:
858 /* keep that selector register around */
859 uart_group_sel[d->dual.group] = d->dual.sel;
860 clk = r9a06g032_register_bitsel(clocks, parent_name, d);
861 break;
862 case K_DUALGATE:
863 clk = r9a06g032_register_dualgate(clocks, parent_name,
864 d,
865 uart_group_sel[d->dual.group]);
866 break;
867 }
868 clocks->data.clks[d->index] = clk;
869 }
870 error = of_clk_add_provider(np, of_clk_src_onecell_get, &clocks->data);
871 if (error)
872 return error;
873
874 return devm_add_action_or_reset(dev,
875 r9a06g032_clocks_del_clk_provider, np);
876}
877
878static const struct of_device_id r9a06g032_match[] = {
879 { .compatible = "renesas,r9a06g032-sysctrl" },
880 { }
881};
882
883static struct platform_driver r9a06g032_clock_driver = {
884 .driver = {
885 .name = "renesas,r9a06g032-sysctrl",
886 .of_match_table = r9a06g032_match,
887 },
888};
889
890static int __init r9a06g032_clocks_init(void)
891{
892 return platform_driver_probe(&r9a06g032_clock_driver,
893 r9a06g032_clocks_probe);
894}
895
896subsys_initcall(r9a06g032_clocks_init);
Linux 6.x block layer and io_uring tree(s)