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e848c2ea | 1 | // SPDX-License-Identifier: GPL-2.0 |
d71e851d GU |
2 | /* |
3 | * r8a77995 Clock Pulse Generator / Module Standby and Software Reset | |
4 | * | |
5 | * Copyright (C) 2017 Glider bvba | |
6 | * | |
7 | * Based on r8a7795-cpg-mssr.c | |
8 | * | |
9 | * Copyright (C) 2015 Glider bvba | |
10 | * Copyright (C) 2015 Renesas Electronics Corp. | |
d71e851d GU |
11 | */ |
12 | ||
13 | #include <linux/device.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/soc/renesas/rcar-rst.h> | |
17 | ||
18 | #include <dt-bindings/clock/r8a77995-cpg-mssr.h> | |
19 | ||
20 | #include "renesas-cpg-mssr.h" | |
21 | #include "rcar-gen3-cpg.h" | |
22 | ||
23 | enum clk_ids { | |
24 | /* Core Clock Outputs exported to DT */ | |
6155bfa3 | 25 | LAST_DT_CORE_CLK = R8A77995_CLK_CPEX, |
d71e851d GU |
26 | |
27 | /* External Input Clocks */ | |
28 | CLK_EXTAL, | |
29 | ||
30 | /* Internal Core Clocks */ | |
31 | CLK_MAIN, | |
32 | CLK_PLL0, | |
33 | CLK_PLL1, | |
34 | CLK_PLL3, | |
35 | CLK_PLL0D2, | |
36 | CLK_PLL0D3, | |
37 | CLK_PLL0D5, | |
38 | CLK_PLL1D2, | |
39 | CLK_PE, | |
40 | CLK_S0, | |
41 | CLK_S1, | |
42 | CLK_S2, | |
43 | CLK_S3, | |
44 | CLK_SDSRC, | |
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45 | CLK_RINT, |
46 | CLK_OCO, | |
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47 | |
48 | /* Module Clocks */ | |
49 | MOD_CLK_BASE | |
50 | }; | |
51 | ||
52 | static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { | |
53 | /* External Clock Inputs */ | |
54 | DEF_INPUT("extal", CLK_EXTAL), | |
55 | ||
56 | /* Internal Core Clocks */ | |
57 | DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), | |
58 | DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), | |
59 | DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), | |
60 | ||
61 | DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250), | |
62 | DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1), | |
63 | DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1), | |
64 | DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1), | |
65 | DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1), | |
66 | DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1), | |
67 | DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1), | |
68 | DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1), | |
69 | DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1), | |
70 | DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), | |
71 | DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), | |
72 | ||
4f57998d GU |
73 | DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), |
74 | ||
75 | DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000), | |
76 | ||
d71e851d GU |
77 | /* Core Clock Outputs */ |
78 | DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1), | |
79 | DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1), | |
80 | DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1), | |
81 | DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1), | |
82 | DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1), | |
83 | DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1), | |
84 | DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1), | |
85 | DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1), | |
86 | DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1), | |
87 | DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1), | |
88 | DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1), | |
89 | DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1), | |
90 | DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1), | |
91 | DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1), | |
92 | ||
93 | DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1), | |
6e26901a | 94 | DEF_FIXED("cr", R8A77995_CLK_CR, CLK_PLL1D2, 2, 1), |
d71e851d | 95 | DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1), |
6155bfa3 | 96 | DEF_FIXED("cpex", R8A77995_CLK_CPEX, CLK_EXTAL, 4, 1), |
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97 | |
98 | DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), | |
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99 | |
100 | DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2), | |
101 | DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), | |
102 | DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2), | |
103 | DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4), | |
104 | ||
105 | DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268), | |
106 | ||
107 | DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244), | |
108 | DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014), | |
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109 | |
110 | DEF_GEN3_RCKSEL("r", R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4), | |
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111 | }; |
112 | ||
113 | static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = { | |
fa7f4797 NS |
114 | DEF_MOD("tmu4", 121, R8A77995_CLK_S1D4C), |
115 | DEF_MOD("tmu3", 122, R8A77995_CLK_S3D2C), | |
116 | DEF_MOD("tmu2", 123, R8A77995_CLK_S3D2C), | |
117 | DEF_MOD("tmu1", 124, R8A77995_CLK_S3D2C), | |
118 | DEF_MOD("tmu0", 125, R8A77995_CLK_CP), | |
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119 | DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C), |
120 | DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C), | |
121 | DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C), | |
122 | DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C), | |
123 | DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C), | |
124 | DEF_MOD("msiof3", 208, R8A77995_CLK_MSO), | |
125 | DEF_MOD("msiof2", 209, R8A77995_CLK_MSO), | |
126 | DEF_MOD("msiof1", 210, R8A77995_CLK_MSO), | |
127 | DEF_MOD("msiof0", 211, R8A77995_CLK_MSO), | |
128 | DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1), | |
129 | DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1), | |
130 | DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1), | |
6e26901a | 131 | DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR), |
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132 | DEF_MOD("cmt3", 300, R8A77995_CLK_R), |
133 | DEF_MOD("cmt2", 301, R8A77995_CLK_R), | |
134 | DEF_MOD("cmt1", 302, R8A77995_CLK_R), | |
135 | DEF_MOD("cmt0", 303, R8A77995_CLK_R), | |
136 | DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C), | |
137 | DEF_MOD("emmc0", 312, R8A77995_CLK_SD0), | |
138 | DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1), | |
139 | DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1), | |
140 | DEF_MOD("rwdt", 402, R8A77995_CLK_R), | |
141 | DEF_MOD("intc-ex", 407, R8A77995_CLK_CP), | |
0022e4a2 | 142 | DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2), |
b9df2ea2 | 143 | DEF_MOD("audmac0", 502, R8A77995_CLK_S1D2), |
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144 | DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C), |
145 | DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C), | |
146 | DEF_MOD("thermal", 522, R8A77995_CLK_CP), | |
147 | DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C), | |
148 | DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2), | |
149 | DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2), | |
150 | DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1), | |
151 | DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2), | |
152 | DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2), | |
153 | DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1), | |
154 | DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2), | |
155 | DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2), | |
fa59290e JM |
156 | DEF_MOD("cmm1", 710, R8A77995_CLK_S1D1), |
157 | DEF_MOD("cmm0", 711, R8A77995_CLK_S1D1), | |
515b2915 GU |
158 | DEF_MOD("du1", 723, R8A77995_CLK_S1D1), |
159 | DEF_MOD("du0", 724, R8A77995_CLK_S1D1), | |
d71e851d | 160 | DEF_MOD("lvds", 727, R8A77995_CLK_S2D1), |
d71e851d GU |
161 | DEF_MOD("vin4", 807, R8A77995_CLK_S1D2), |
162 | DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2), | |
163 | DEF_MOD("imr0", 823, R8A77995_CLK_S1D2), | |
164 | DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4), | |
165 | DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4), | |
166 | DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4), | |
167 | DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4), | |
168 | DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4), | |
169 | DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4), | |
170 | DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4), | |
171 | DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2), | |
172 | DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4), | |
173 | DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4), | |
174 | DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2), | |
175 | DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2), | |
176 | DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2), | |
177 | DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2), | |
178 | DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4), | |
179 | DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), | |
180 | DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), | |
181 | DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4), | |
182 | DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), | |
183 | DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), | |
184 | DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), | |
185 | DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), | |
186 | DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), | |
187 | DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), | |
188 | }; | |
189 | ||
190 | static const unsigned int r8a77995_crit_mod_clks[] __initconst = { | |
f23f1101 | 191 | MOD_CLK_ID(402), /* RWDT */ |
d71e851d GU |
192 | MOD_CLK_ID(408), /* INTC-AP (GIC) */ |
193 | }; | |
194 | ||
d71e851d GU |
195 | /* |
196 | * CPG Clock Data | |
197 | */ | |
198 | ||
199 | /* | |
200 | * MD19 EXTAL (MHz) PLL0 PLL1 PLL3 | |
201 | *-------------------------------------------------------------------- | |
202 | * 0 48 x 1 x250/4 x100/3 x100/3 | |
c0f8584f | 203 | * 1 48 x 1 x250/4 x100/3 x58/3 |
d71e851d GU |
204 | */ |
205 | #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19) | |
206 | ||
207 | static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = { | |
208 | /* EXTAL div PLL1 mult/div PLL3 mult/div */ | |
209 | { 1, 100, 3, 100, 3, }, | |
c0f8584f | 210 | { 1, 100, 3, 58, 3, }, |
d71e851d GU |
211 | }; |
212 | ||
213 | static int __init r8a77995_cpg_mssr_init(struct device *dev) | |
214 | { | |
215 | const struct rcar_gen3_cpg_pll_config *cpg_pll_config; | |
216 | u32 cpg_mode; | |
217 | int error; | |
218 | ||
219 | error = rcar_rst_read_mode_pins(&cpg_mode); | |
220 | if (error) | |
221 | return error; | |
222 | ||
223 | cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; | |
224 | ||
225 | return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode); | |
226 | } | |
227 | ||
228 | const struct cpg_mssr_info r8a77995_cpg_mssr_info __initconst = { | |
229 | /* Core Clocks */ | |
230 | .core_clks = r8a77995_core_clks, | |
231 | .num_core_clks = ARRAY_SIZE(r8a77995_core_clks), | |
232 | .last_dt_core_clk = LAST_DT_CORE_CLK, | |
233 | .num_total_core_clks = MOD_CLK_BASE, | |
234 | ||
235 | /* Module Clocks */ | |
236 | .mod_clks = r8a77995_mod_clks, | |
237 | .num_mod_clks = ARRAY_SIZE(r8a77995_mod_clks), | |
238 | .num_hw_mod_clks = 12 * 32, | |
239 | ||
240 | /* Critical Module Clocks */ | |
241 | .crit_mod_clks = r8a77995_crit_mod_clks, | |
242 | .num_crit_mod_clks = ARRAY_SIZE(r8a77995_crit_mod_clks), | |
243 | ||
244 | /* Callbacks */ | |
245 | .init = r8a77995_cpg_mssr_init, | |
246 | .cpg_clk_register = rcar_gen3_cpg_clk_register, | |
247 | }; |