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clk: renesas: cpg-mssr: Extract common R-Car Gen3 support code
[linux-2.6-block.git] / drivers / clk / renesas / r8a7795-cpg-mssr.c
CommitLineData
c5dae0df
GU		 1/*
2 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
3 *
4 * Copyright (C) 2015 Glider bvba
5 *
6 * Based on clk-rcar-gen3.c
7 *
8 * Copyright (C) 2015 Renesas Electronics Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 */
14
c5dae0df 15#include <linux/device.h>
c5dae0df 16#include <linux/init.h>
c5dae0df 17#include <linux/kernel.h>
c5dae0df
GU		 18
19#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
20
21#include "renesas-cpg-mssr.h"
5b1defde 22#include "rcar-gen3-cpg.h"
c5dae0df
GU		 23
24enum clk_ids {
25 /* Core Clock Outputs exported to DT */
26 LAST_DT_CORE_CLK = R8A7795_CLK_OSC,
27
28 /* External Input Clocks */
29 CLK_EXTAL,
30 CLK_EXTALR,
31
32 /* Internal Core Clocks */
33 CLK_MAIN,
34 CLK_PLL0,
35 CLK_PLL1,
36 CLK_PLL2,
37 CLK_PLL3,
38 CLK_PLL4,
39 CLK_PLL1_DIV2,
40 CLK_PLL1_DIV4,
41 CLK_S0,
42 CLK_S1,
43 CLK_S2,
44 CLK_S3,
45 CLK_SDSRC,
46 CLK_SSPSRC,
5524a67f 47 CLK_RINT,
c5dae0df
GU		 48
49 /* Module Clocks */
50 MOD_CLK_BASE
51};
52
c5dae0df
GU		 53static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
54 /* External Clock Inputs */
55 DEF_INPUT("extal", CLK_EXTAL),
56 DEF_INPUT("extalr", CLK_EXTALR),
57
58 /* Internal Core Clocks */
59 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
60 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
61 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
62 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
63 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
64 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
65
66 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
67 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
68 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
69 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
70 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
71 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
72
73 /* Core Clock Outputs */
74 DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
75 DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
76 DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
77 DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
78 DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
79 DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
80 DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
81 DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
82 DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
83 DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
84 DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
85 DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
86 DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
87 DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
88 DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
90c073e5 89
ba8c1a81
WS		 90 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_PLL1_DIV2, 0x0074),
91 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_PLL1_DIV2, 0x0078),
92 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_PLL1_DIV2, 0x0268),
93 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_PLL1_DIV2, 0x026c),
90c073e5 94
c5dae0df
GU		 95 DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
96 DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
97
98 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
99 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),
7e00d631 100 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
0187d321 101 DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
5524a67f
WS		 102
103 DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
104 DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
1e6237e3
WS		 105
106 DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
c5dae0df
GU		 107};
108
109static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
110 DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
111 DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
112 DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
113 DEF_MOD("scif1", 206, R8A7795_CLK_S3D4),
114 DEF_MOD("scif0", 207, R8A7795_CLK_S3D4),
115 DEF_MOD("msiof3", 208, R8A7795_CLK_MSO),
116 DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
117 DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
118 DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
119 DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
120 DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1),
121 DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S3D1),
122 DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
90c073e5
DB		 123 DEF_MOD("sdif3", 311, R8A7795_CLK_SD3),
124 DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
125 DEF_MOD("sdif1", 313, R8A7795_CLK_SD1),
126 DEF_MOD("sdif0", 314, R8A7795_CLK_SD0),
c5dae0df
GU		 127 DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
128 DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
b7c9b91d
YS		 129 DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1),
130 DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
7826c611
YS		 131 DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
132 DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
6248620b 133 DEF_MOD("rwdt0", 402, R8A7795_CLK_R),
f099aa07 134 DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
c5dae0df
GU		 135 DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
136 DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4),
137 DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4),
138 DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
139 DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
140 DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
141 DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
142 DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
847e8792 143 DEF_MOD("pwm", 523, R8A7795_CLK_S3D4),
c5f80c5f
LP		 144 DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1),
145 DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1),
146 DEF_MOD("fcpvd1", 602, R8A7795_CLK_S2D1),
147 DEF_MOD("fcpvd0", 603, R8A7795_CLK_S2D1),
148 DEF_MOD("fcpvb1", 606, R8A7795_CLK_S2D1),
149 DEF_MOD("fcpvb0", 607, R8A7795_CLK_S2D1),
150 DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1),
151 DEF_MOD("fcpvi1", 610, R8A7795_CLK_S2D1),
152 DEF_MOD("fcpvi0", 611, R8A7795_CLK_S2D1),
153 DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1),
154 DEF_MOD("fcpf1", 614, R8A7795_CLK_S2D1),
155 DEF_MOD("fcpf0", 615, R8A7795_CLK_S2D1),
156 DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1),
157 DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1),
158 DEF_MOD("fcpcs", 619, R8A7795_CLK_S2D1),
c5dae0df
GU		 159 DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1),
160 DEF_MOD("vspd2", 621, R8A7795_CLK_S2D1),
161 DEF_MOD("vspd1", 622, R8A7795_CLK_S2D1),
162 DEF_MOD("vspd0", 623, R8A7795_CLK_S2D1),
163 DEF_MOD("vspbc", 624, R8A7795_CLK_S2D1),
164 DEF_MOD("vspbd", 626, R8A7795_CLK_S2D1),
165 DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1),
166 DEF_MOD("vspi1", 630, R8A7795_CLK_S2D1),
167 DEF_MOD("vspi0", 631, R8A7795_CLK_S2D1),
168 DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
169 DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
170 DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
171 DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
0187d321
NS		 172 DEF_MOD("csi21", 713, R8A7795_CLK_CSI0),
173 DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
174 DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
175 DEF_MOD("csi40", 716, R8A7795_CLK_CSI0),
c5dae0df
GU		 176 DEF_MOD("du3", 721, R8A7795_CLK_S2D1),
177 DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
178 DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
179 DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
31aeb5a5 180 DEF_MOD("lvds", 727, R8A7795_CLK_S2D1),
c5dae0df
GU		 181 DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
182 DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
ccce262d
NS		 183 DEF_MOD("vin7", 804, R8A7795_CLK_S2D1),
184 DEF_MOD("vin6", 805, R8A7795_CLK_S2D1),
185 DEF_MOD("vin5", 806, R8A7795_CLK_S2D1),
186 DEF_MOD("vin4", 807, R8A7795_CLK_S2D1),
187 DEF_MOD("vin3", 808, R8A7795_CLK_S2D1),
188 DEF_MOD("vin2", 809, R8A7795_CLK_S2D1),
189 DEF_MOD("vin1", 810, R8A7795_CLK_S2D1),
190 DEF_MOD("vin0", 811, R8A7795_CLK_S2D1),
c5dae0df 191 DEF_MOD("etheravb", 812, R8A7795_CLK_S3D2),
c1c5864d 192 DEF_MOD("sata0", 815, R8A7795_CLK_S3D2),
c5dae0df
GU		 193 DEF_MOD("gpio7", 905, R8A7795_CLK_CP),
194 DEF_MOD("gpio6", 906, R8A7795_CLK_CP),
195 DEF_MOD("gpio5", 907, R8A7795_CLK_CP),
196 DEF_MOD("gpio4", 908, R8A7795_CLK_CP),
197 DEF_MOD("gpio3", 909, R8A7795_CLK_CP),
198 DEF_MOD("gpio2", 910, R8A7795_CLK_CP),
199 DEF_MOD("gpio1", 911, R8A7795_CLK_CP),
200 DEF_MOD("gpio0", 912, R8A7795_CLK_CP),
a080c8c3 201 DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
11c6fb78
RS		 202 DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
203 DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
c5dae0df
GU		 204 DEF_MOD("i2c6", 918, R8A7795_CLK_S3D2),
205 DEF_MOD("i2c5", 919, R8A7795_CLK_S3D2),
206 DEF_MOD("i2c4", 927, R8A7795_CLK_S3D2),
207 DEF_MOD("i2c3", 928, R8A7795_CLK_S3D2),
208 DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
209 DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
210 DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
211 DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
212 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
213 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
214 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
215 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
216 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
217 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
218 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
219 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
220 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
221 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
222 DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
223 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
224 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
225 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
226 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
227 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
228 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
229 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
230 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
231 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
232 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
233 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
234 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
235 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
236 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
237};
238
239static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
240 MOD_CLK_ID(408), /* INTC-AP (GIC) */
241};
242
c5dae0df
GU		 243
244/*
245 * CPG Clock Data
246 */
247
248/*
249 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
250 * 14 13 19 17 (MHz)
251 *-------------------------------------------------------------------
252 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
253 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
254 * 0 0 1 0 Prohibited setting
255 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
256 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
257 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
258 * 0 1 1 0 Prohibited setting
259 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
260 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
261 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
262 * 1 0 1 0 Prohibited setting
263 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
264 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
265 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
266 * 1 1 1 0 Prohibited setting
267 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
268 */
269#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
270 (((md) & BIT(13)) >> 11) | \
271 (((md) & BIT(19)) >> 18) | \
272 (((md) & BIT(17)) >> 17))
273
5b1defde 274static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
c5dae0df
GU		 275 /* EXTAL div PLL1 mult PLL3 mult */
276 { 1, 192, 192, },
277 { 1, 192, 128, },
278 { 0, /* Prohibited setting */ },
279 { 1, 192, 192, },
280 { 1, 160, 160, },
281 { 1, 160, 106, },
282 { 0, /* Prohibited setting */ },
283 { 1, 160, 160, },
284 { 1, 128, 128, },
285 { 1, 128, 84, },
286 { 0, /* Prohibited setting */ },
287 { 1, 128, 128, },
288 { 2, 192, 192, },
289 { 2, 192, 128, },
290 { 0, /* Prohibited setting */ },
291 { 2, 192, 192, },
292};
293
c5dae0df
GU		 294static int __init r8a7795_cpg_mssr_init(struct device *dev)
295{
5b1defde 296 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
c5dae0df
GU		 297 u32 cpg_mode = rcar_gen3_read_mode_pins();
298
299 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
300 if (!cpg_pll_config->extal_div) {
301 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
302 return -EINVAL;
303 }
304
5b1defde 305 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR);
c5dae0df
GU		 306}
307
308const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
309 /* Core Clocks */
310 .core_clks = r8a7795_core_clks,
311 .num_core_clks = ARRAY_SIZE(r8a7795_core_clks),
312 .last_dt_core_clk = LAST_DT_CORE_CLK,
313 .num_total_core_clks = MOD_CLK_BASE,
314
315 /* Module Clocks */
316 .mod_clks = r8a7795_mod_clks,
317 .num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks),
318 .num_hw_mod_clks = 12 * 32,
319
320 /* Critical Module Clocks */
321 .crit_mod_clks = r8a7795_crit_mod_clks,
322 .num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks),
323
324 /* Callbacks */
325 .init = r8a7795_cpg_mssr_init,
5b1defde 326 .cpg_clk_register = rcar_gen3_cpg_clk_register,
c5dae0df 327};
Linux 6.x block layer and io_uring tree(s)