Commit | Line | Data |
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c5dae0df GU |
1 | /* |
2 | * r8a7795 Clock Pulse Generator / Module Standby and Software Reset | |
3 | * | |
4 | * Copyright (C) 2015 Glider bvba | |
5 | * | |
6 | * Based on clk-rcar-gen3.c | |
7 | * | |
8 | * Copyright (C) 2015 Renesas Electronics Corp. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | */ | |
14 | ||
15 | #include <linux/bug.h> | |
1e6237e3 | 16 | #include <linux/clk.h> |
c5dae0df GU |
17 | #include <linux/clk-provider.h> |
18 | #include <linux/device.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/of.h> | |
90c073e5 | 24 | #include <linux/slab.h> |
c5dae0df GU |
25 | |
26 | #include <dt-bindings/clock/r8a7795-cpg-mssr.h> | |
27 | ||
28 | #include "renesas-cpg-mssr.h" | |
29 | ||
5524a67f | 30 | #define CPG_RCKCR 0x240 |
c5dae0df GU |
31 | |
32 | enum clk_ids { | |
33 | /* Core Clock Outputs exported to DT */ | |
34 | LAST_DT_CORE_CLK = R8A7795_CLK_OSC, | |
35 | ||
36 | /* External Input Clocks */ | |
37 | CLK_EXTAL, | |
38 | CLK_EXTALR, | |
39 | ||
40 | /* Internal Core Clocks */ | |
41 | CLK_MAIN, | |
42 | CLK_PLL0, | |
43 | CLK_PLL1, | |
44 | CLK_PLL2, | |
45 | CLK_PLL3, | |
46 | CLK_PLL4, | |
47 | CLK_PLL1_DIV2, | |
48 | CLK_PLL1_DIV4, | |
49 | CLK_S0, | |
50 | CLK_S1, | |
51 | CLK_S2, | |
52 | CLK_S3, | |
53 | CLK_SDSRC, | |
54 | CLK_SSPSRC, | |
5524a67f | 55 | CLK_RINT, |
c5dae0df GU |
56 | |
57 | /* Module Clocks */ | |
58 | MOD_CLK_BASE | |
59 | }; | |
60 | ||
61 | enum r8a7795_clk_types { | |
62 | CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM, | |
63 | CLK_TYPE_GEN3_PLL0, | |
64 | CLK_TYPE_GEN3_PLL1, | |
65 | CLK_TYPE_GEN3_PLL2, | |
66 | CLK_TYPE_GEN3_PLL3, | |
67 | CLK_TYPE_GEN3_PLL4, | |
90c073e5 | 68 | CLK_TYPE_GEN3_SD, |
1e6237e3 | 69 | CLK_TYPE_GEN3_R, |
c5dae0df GU |
70 | }; |
71 | ||
ba8c1a81 WS |
72 | #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ |
73 | DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) | |
74 | ||
c5dae0df GU |
75 | static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { |
76 | /* External Clock Inputs */ | |
77 | DEF_INPUT("extal", CLK_EXTAL), | |
78 | DEF_INPUT("extalr", CLK_EXTALR), | |
79 | ||
80 | /* Internal Core Clocks */ | |
81 | DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), | |
82 | DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), | |
83 | DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), | |
84 | DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), | |
85 | DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), | |
86 | DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), | |
87 | ||
88 | DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), | |
89 | DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), | |
90 | DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), | |
91 | DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), | |
92 | DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), | |
93 | DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), | |
94 | ||
95 | /* Core Clock Outputs */ | |
96 | DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), | |
97 | DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), | |
98 | DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), | |
99 | DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1), | |
100 | DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1), | |
101 | DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1), | |
102 | DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1), | |
103 | DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1), | |
104 | DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1), | |
105 | DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1), | |
106 | DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1), | |
107 | DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1), | |
108 | DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1), | |
109 | DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1), | |
110 | DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1), | |
90c073e5 | 111 | |
ba8c1a81 WS |
112 | DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_PLL1_DIV2, 0x0074), |
113 | DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_PLL1_DIV2, 0x0078), | |
114 | DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_PLL1_DIV2, 0x0268), | |
115 | DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_PLL1_DIV2, 0x026c), | |
90c073e5 | 116 | |
c5dae0df GU |
117 | DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1), |
118 | DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), | |
119 | ||
120 | DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), | |
121 | DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250), | |
7e00d631 | 122 | DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244), |
5524a67f WS |
123 | |
124 | DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), | |
125 | DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), | |
1e6237e3 WS |
126 | |
127 | DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), | |
c5dae0df GU |
128 | }; |
129 | ||
130 | static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { | |
131 | DEF_MOD("scif5", 202, R8A7795_CLK_S3D4), | |
132 | DEF_MOD("scif4", 203, R8A7795_CLK_S3D4), | |
133 | DEF_MOD("scif3", 204, R8A7795_CLK_S3D4), | |
134 | DEF_MOD("scif1", 206, R8A7795_CLK_S3D4), | |
135 | DEF_MOD("scif0", 207, R8A7795_CLK_S3D4), | |
136 | DEF_MOD("msiof3", 208, R8A7795_CLK_MSO), | |
137 | DEF_MOD("msiof2", 209, R8A7795_CLK_MSO), | |
138 | DEF_MOD("msiof1", 210, R8A7795_CLK_MSO), | |
139 | DEF_MOD("msiof0", 211, R8A7795_CLK_MSO), | |
140 | DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1), | |
141 | DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1), | |
142 | DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S3D1), | |
143 | DEF_MOD("scif2", 310, R8A7795_CLK_S3D4), | |
90c073e5 DB |
144 | DEF_MOD("sdif3", 311, R8A7795_CLK_SD3), |
145 | DEF_MOD("sdif2", 312, R8A7795_CLK_SD2), | |
146 | DEF_MOD("sdif1", 313, R8A7795_CLK_SD1), | |
147 | DEF_MOD("sdif0", 314, R8A7795_CLK_SD0), | |
c5dae0df GU |
148 | DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1), |
149 | DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1), | |
b7c9b91d YS |
150 | DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), |
151 | DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), | |
7826c611 YS |
152 | DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1), |
153 | DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1), | |
f099aa07 | 154 | DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), |
c5dae0df GU |
155 | DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), |
156 | DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4), | |
157 | DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4), | |
158 | DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1), | |
159 | DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1), | |
160 | DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1), | |
161 | DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1), | |
162 | DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1), | |
847e8792 | 163 | DEF_MOD("pwm", 523, R8A7795_CLK_S3D4), |
c5f80c5f LP |
164 | DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), |
165 | DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1), | |
166 | DEF_MOD("fcpvd1", 602, R8A7795_CLK_S2D1), | |
167 | DEF_MOD("fcpvd0", 603, R8A7795_CLK_S2D1), | |
168 | DEF_MOD("fcpvb1", 606, R8A7795_CLK_S2D1), | |
169 | DEF_MOD("fcpvb0", 607, R8A7795_CLK_S2D1), | |
170 | DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), | |
171 | DEF_MOD("fcpvi1", 610, R8A7795_CLK_S2D1), | |
172 | DEF_MOD("fcpvi0", 611, R8A7795_CLK_S2D1), | |
173 | DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), | |
174 | DEF_MOD("fcpf1", 614, R8A7795_CLK_S2D1), | |
175 | DEF_MOD("fcpf0", 615, R8A7795_CLK_S2D1), | |
176 | DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), | |
177 | DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), | |
178 | DEF_MOD("fcpcs", 619, R8A7795_CLK_S2D1), | |
c5dae0df GU |
179 | DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), |
180 | DEF_MOD("vspd2", 621, R8A7795_CLK_S2D1), | |
181 | DEF_MOD("vspd1", 622, R8A7795_CLK_S2D1), | |
182 | DEF_MOD("vspd0", 623, R8A7795_CLK_S2D1), | |
183 | DEF_MOD("vspbc", 624, R8A7795_CLK_S2D1), | |
184 | DEF_MOD("vspbd", 626, R8A7795_CLK_S2D1), | |
185 | DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), | |
186 | DEF_MOD("vspi1", 630, R8A7795_CLK_S2D1), | |
187 | DEF_MOD("vspi0", 631, R8A7795_CLK_S2D1), | |
188 | DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4), | |
189 | DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4), | |
190 | DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4), | |
191 | DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4), | |
192 | DEF_MOD("du3", 721, R8A7795_CLK_S2D1), | |
193 | DEF_MOD("du2", 722, R8A7795_CLK_S2D1), | |
194 | DEF_MOD("du1", 723, R8A7795_CLK_S2D1), | |
195 | DEF_MOD("du0", 724, R8A7795_CLK_S2D1), | |
31aeb5a5 | 196 | DEF_MOD("lvds", 727, R8A7795_CLK_S2D1), |
c5dae0df GU |
197 | DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI), |
198 | DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI), | |
199 | DEF_MOD("etheravb", 812, R8A7795_CLK_S3D2), | |
c1c5864d | 200 | DEF_MOD("sata0", 815, R8A7795_CLK_S3D2), |
c5dae0df GU |
201 | DEF_MOD("gpio7", 905, R8A7795_CLK_CP), |
202 | DEF_MOD("gpio6", 906, R8A7795_CLK_CP), | |
203 | DEF_MOD("gpio5", 907, R8A7795_CLK_CP), | |
204 | DEF_MOD("gpio4", 908, R8A7795_CLK_CP), | |
205 | DEF_MOD("gpio3", 909, R8A7795_CLK_CP), | |
206 | DEF_MOD("gpio2", 910, R8A7795_CLK_CP), | |
207 | DEF_MOD("gpio1", 911, R8A7795_CLK_CP), | |
208 | DEF_MOD("gpio0", 912, R8A7795_CLK_CP), | |
a080c8c3 | 209 | DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2), |
11c6fb78 RS |
210 | DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4), |
211 | DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4), | |
c5dae0df GU |
212 | DEF_MOD("i2c6", 918, R8A7795_CLK_S3D2), |
213 | DEF_MOD("i2c5", 919, R8A7795_CLK_S3D2), | |
214 | DEF_MOD("i2c4", 927, R8A7795_CLK_S3D2), | |
215 | DEF_MOD("i2c3", 928, R8A7795_CLK_S3D2), | |
216 | DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2), | |
217 | DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2), | |
218 | DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2), | |
219 | DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4), | |
220 | DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), | |
221 | DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), | |
222 | DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), | |
223 | DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), | |
224 | DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), | |
225 | DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), | |
226 | DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), | |
227 | DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), | |
228 | DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), | |
229 | DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), | |
230 | DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4), | |
231 | DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), | |
232 | DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), | |
233 | DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), | |
234 | DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), | |
235 | DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), | |
236 | DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), | |
237 | DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), | |
238 | DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), | |
239 | DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), | |
240 | DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), | |
241 | DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), | |
242 | DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), | |
243 | DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), | |
244 | DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), | |
245 | }; | |
246 | ||
247 | static const unsigned int r8a7795_crit_mod_clks[] __initconst = { | |
248 | MOD_CLK_ID(408), /* INTC-AP (GIC) */ | |
249 | }; | |
250 | ||
90c073e5 DB |
251 | /* ----------------------------------------------------------------------------- |
252 | * SDn Clock | |
253 | * | |
254 | */ | |
255 | #define CPG_SD_STP_HCK BIT(9) | |
256 | #define CPG_SD_STP_CK BIT(8) | |
257 | ||
258 | #define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK) | |
259 | #define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0) | |
260 | ||
261 | #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \ | |
262 | { \ | |
263 | .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \ | |
264 | ((stp_ck) ? CPG_SD_STP_CK : 0) | \ | |
265 | ((sd_srcfc) << 2) | \ | |
266 | ((sd_fc) << 0), \ | |
267 | .div = (sd_div), \ | |
268 | } | |
269 | ||
270 | struct sd_div_table { | |
271 | u32 val; | |
272 | unsigned int div; | |
273 | }; | |
274 | ||
275 | struct sd_clock { | |
276 | struct clk_hw hw; | |
277 | void __iomem *reg; | |
278 | const struct sd_div_table *div_table; | |
279 | unsigned int div_num; | |
280 | unsigned int div_min; | |
281 | unsigned int div_max; | |
282 | }; | |
283 | ||
284 | /* SDn divider | |
285 | * sd_srcfc sd_fc div | |
286 | * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc | |
287 | *------------------------------------------------------------------- | |
288 | * 0 0 0 (1) 1 (4) 4 | |
289 | * 0 0 1 (2) 1 (4) 8 | |
290 | * 1 0 2 (4) 1 (4) 16 | |
291 | * 1 0 3 (8) 1 (4) 32 | |
292 | * 1 0 4 (16) 1 (4) 64 | |
293 | * 0 0 0 (1) 0 (2) 2 | |
294 | * 0 0 1 (2) 0 (2) 4 | |
295 | * 1 0 2 (4) 0 (2) 8 | |
296 | * 1 0 3 (8) 0 (2) 16 | |
297 | * 1 0 4 (16) 0 (2) 32 | |
298 | */ | |
299 | static const struct sd_div_table cpg_sd_div_table[] = { | |
300 | /* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */ | |
301 | CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4), | |
302 | CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8), | |
303 | CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16), | |
304 | CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32), | |
305 | CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64), | |
306 | CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2), | |
307 | CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4), | |
308 | CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8), | |
309 | CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16), | |
310 | CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32), | |
311 | }; | |
312 | ||
313 | #define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw) | |
314 | ||
315 | static int cpg_sd_clock_enable(struct clk_hw *hw) | |
316 | { | |
317 | struct sd_clock *clock = to_sd_clock(hw); | |
318 | u32 val, sd_fc; | |
319 | unsigned int i; | |
320 | ||
321 | val = clk_readl(clock->reg); | |
322 | ||
323 | sd_fc = val & CPG_SD_FC_MASK; | |
324 | for (i = 0; i < clock->div_num; i++) | |
325 | if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK)) | |
326 | break; | |
327 | ||
328 | if (i >= clock->div_num) | |
329 | return -EINVAL; | |
330 | ||
331 | val &= ~(CPG_SD_STP_MASK); | |
332 | val |= clock->div_table[i].val & CPG_SD_STP_MASK; | |
333 | ||
334 | clk_writel(val, clock->reg); | |
335 | ||
336 | return 0; | |
337 | } | |
338 | ||
339 | static void cpg_sd_clock_disable(struct clk_hw *hw) | |
340 | { | |
341 | struct sd_clock *clock = to_sd_clock(hw); | |
342 | ||
343 | clk_writel(clk_readl(clock->reg) | CPG_SD_STP_MASK, clock->reg); | |
344 | } | |
345 | ||
346 | static int cpg_sd_clock_is_enabled(struct clk_hw *hw) | |
347 | { | |
348 | struct sd_clock *clock = to_sd_clock(hw); | |
349 | ||
350 | return !(clk_readl(clock->reg) & CPG_SD_STP_MASK); | |
351 | } | |
352 | ||
353 | static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw, | |
354 | unsigned long parent_rate) | |
355 | { | |
356 | struct sd_clock *clock = to_sd_clock(hw); | |
357 | unsigned long rate = parent_rate; | |
358 | u32 val, sd_fc; | |
359 | unsigned int i; | |
360 | ||
361 | val = clk_readl(clock->reg); | |
362 | ||
363 | sd_fc = val & CPG_SD_FC_MASK; | |
364 | for (i = 0; i < clock->div_num; i++) | |
365 | if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK)) | |
366 | break; | |
367 | ||
368 | if (i >= clock->div_num) | |
369 | return -EINVAL; | |
370 | ||
371 | return DIV_ROUND_CLOSEST(rate, clock->div_table[i].div); | |
372 | } | |
373 | ||
374 | static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock, | |
375 | unsigned long rate, | |
376 | unsigned long parent_rate) | |
377 | { | |
378 | unsigned int div; | |
379 | ||
380 | if (!rate) | |
381 | rate = 1; | |
382 | ||
383 | div = DIV_ROUND_CLOSEST(parent_rate, rate); | |
384 | ||
385 | return clamp_t(unsigned int, div, clock->div_min, clock->div_max); | |
386 | } | |
387 | ||
388 | static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, | |
389 | unsigned long *parent_rate) | |
390 | { | |
391 | struct sd_clock *clock = to_sd_clock(hw); | |
392 | unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate); | |
393 | ||
394 | return DIV_ROUND_CLOSEST(*parent_rate, div); | |
395 | } | |
396 | ||
397 | static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate, | |
398 | unsigned long parent_rate) | |
399 | { | |
400 | struct sd_clock *clock = to_sd_clock(hw); | |
401 | unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate); | |
402 | u32 val; | |
403 | unsigned int i; | |
404 | ||
405 | for (i = 0; i < clock->div_num; i++) | |
406 | if (div == clock->div_table[i].div) | |
407 | break; | |
408 | ||
409 | if (i >= clock->div_num) | |
410 | return -EINVAL; | |
411 | ||
412 | val = clk_readl(clock->reg); | |
413 | val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK); | |
414 | val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK); | |
415 | clk_writel(val, clock->reg); | |
416 | ||
417 | return 0; | |
418 | } | |
419 | ||
420 | static const struct clk_ops cpg_sd_clock_ops = { | |
421 | .enable = cpg_sd_clock_enable, | |
422 | .disable = cpg_sd_clock_disable, | |
423 | .is_enabled = cpg_sd_clock_is_enabled, | |
424 | .recalc_rate = cpg_sd_clock_recalc_rate, | |
425 | .round_rate = cpg_sd_clock_round_rate, | |
426 | .set_rate = cpg_sd_clock_set_rate, | |
427 | }; | |
428 | ||
429 | static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core, | |
430 | void __iomem *base, | |
431 | const char *parent_name) | |
432 | { | |
433 | struct clk_init_data init; | |
434 | struct sd_clock *clock; | |
435 | struct clk *clk; | |
436 | unsigned int i; | |
437 | ||
438 | clock = kzalloc(sizeof(*clock), GFP_KERNEL); | |
439 | if (!clock) | |
440 | return ERR_PTR(-ENOMEM); | |
441 | ||
442 | init.name = core->name; | |
443 | init.ops = &cpg_sd_clock_ops; | |
444 | init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT; | |
445 | init.parent_names = &parent_name; | |
446 | init.num_parents = 1; | |
447 | ||
448 | clock->reg = base + core->offset; | |
449 | clock->hw.init = &init; | |
450 | clock->div_table = cpg_sd_div_table; | |
451 | clock->div_num = ARRAY_SIZE(cpg_sd_div_table); | |
452 | ||
453 | clock->div_max = clock->div_table[0].div; | |
454 | clock->div_min = clock->div_max; | |
455 | for (i = 1; i < clock->div_num; i++) { | |
456 | clock->div_max = max(clock->div_max, clock->div_table[i].div); | |
457 | clock->div_min = min(clock->div_min, clock->div_table[i].div); | |
458 | } | |
459 | ||
460 | clk = clk_register(NULL, &clock->hw); | |
461 | if (IS_ERR(clk)) | |
462 | kfree(clock); | |
463 | ||
464 | return clk; | |
465 | } | |
c5dae0df GU |
466 | |
467 | #define CPG_PLL0CR 0x00d8 | |
468 | #define CPG_PLL2CR 0x002c | |
469 | #define CPG_PLL4CR 0x01f4 | |
470 | ||
471 | /* | |
472 | * CPG Clock Data | |
473 | */ | |
474 | ||
475 | /* | |
476 | * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 | |
477 | * 14 13 19 17 (MHz) | |
478 | *------------------------------------------------------------------- | |
479 | * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 | |
480 | * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 | |
481 | * 0 0 1 0 Prohibited setting | |
482 | * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 | |
483 | * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 | |
484 | * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 | |
485 | * 0 1 1 0 Prohibited setting | |
486 | * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 | |
487 | * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 | |
488 | * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 | |
489 | * 1 0 1 0 Prohibited setting | |
490 | * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 | |
491 | * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 | |
492 | * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 | |
493 | * 1 1 1 0 Prohibited setting | |
494 | * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 | |
495 | */ | |
496 | #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ | |
497 | (((md) & BIT(13)) >> 11) | \ | |
498 | (((md) & BIT(19)) >> 18) | \ | |
499 | (((md) & BIT(17)) >> 17)) | |
500 | ||
501 | struct cpg_pll_config { | |
502 | unsigned int extal_div; | |
503 | unsigned int pll1_mult; | |
504 | unsigned int pll3_mult; | |
505 | }; | |
506 | ||
507 | static const struct cpg_pll_config cpg_pll_configs[16] __initconst = { | |
508 | /* EXTAL div PLL1 mult PLL3 mult */ | |
509 | { 1, 192, 192, }, | |
510 | { 1, 192, 128, }, | |
511 | { 0, /* Prohibited setting */ }, | |
512 | { 1, 192, 192, }, | |
513 | { 1, 160, 160, }, | |
514 | { 1, 160, 106, }, | |
515 | { 0, /* Prohibited setting */ }, | |
516 | { 1, 160, 160, }, | |
517 | { 1, 128, 128, }, | |
518 | { 1, 128, 84, }, | |
519 | { 0, /* Prohibited setting */ }, | |
520 | { 1, 128, 128, }, | |
521 | { 2, 192, 192, }, | |
522 | { 2, 192, 128, }, | |
523 | { 0, /* Prohibited setting */ }, | |
524 | { 2, 192, 192, }, | |
525 | }; | |
526 | ||
527 | static const struct cpg_pll_config *cpg_pll_config __initdata; | |
528 | ||
529 | static | |
530 | struct clk * __init r8a7795_cpg_clk_register(struct device *dev, | |
531 | const struct cpg_core_clk *core, | |
532 | const struct cpg_mssr_info *info, | |
533 | struct clk **clks, | |
534 | void __iomem *base) | |
535 | { | |
536 | const struct clk *parent; | |
537 | unsigned int mult = 1; | |
538 | unsigned int div = 1; | |
539 | u32 value; | |
540 | ||
541 | parent = clks[core->parent]; | |
542 | if (IS_ERR(parent)) | |
543 | return ERR_CAST(parent); | |
544 | ||
545 | switch (core->type) { | |
546 | case CLK_TYPE_GEN3_MAIN: | |
547 | div = cpg_pll_config->extal_div; | |
548 | break; | |
549 | ||
550 | case CLK_TYPE_GEN3_PLL0: | |
551 | /* | |
552 | * PLL0 is a configurable multiplier clock. Register it as a | |
553 | * fixed factor clock for now as there's no generic multiplier | |
554 | * clock implementation and we currently have no need to change | |
555 | * the multiplier value. | |
556 | */ | |
557 | value = readl(base + CPG_PLL0CR); | |
558 | mult = (((value >> 24) & 0x7f) + 1) * 2; | |
559 | break; | |
560 | ||
561 | case CLK_TYPE_GEN3_PLL1: | |
562 | mult = cpg_pll_config->pll1_mult; | |
563 | break; | |
564 | ||
565 | case CLK_TYPE_GEN3_PLL2: | |
566 | /* | |
567 | * PLL2 is a configurable multiplier clock. Register it as a | |
568 | * fixed factor clock for now as there's no generic multiplier | |
569 | * clock implementation and we currently have no need to change | |
570 | * the multiplier value. | |
571 | */ | |
572 | value = readl(base + CPG_PLL2CR); | |
573 | mult = (((value >> 24) & 0x7f) + 1) * 2; | |
574 | break; | |
575 | ||
576 | case CLK_TYPE_GEN3_PLL3: | |
577 | mult = cpg_pll_config->pll3_mult; | |
578 | break; | |
579 | ||
580 | case CLK_TYPE_GEN3_PLL4: | |
581 | /* | |
582 | * PLL4 is a configurable multiplier clock. Register it as a | |
583 | * fixed factor clock for now as there's no generic multiplier | |
584 | * clock implementation and we currently have no need to change | |
585 | * the multiplier value. | |
586 | */ | |
587 | value = readl(base + CPG_PLL4CR); | |
588 | mult = (((value >> 24) & 0x7f) + 1) * 2; | |
589 | break; | |
590 | ||
90c073e5 DB |
591 | case CLK_TYPE_GEN3_SD: |
592 | return cpg_sd_clk_register(core, base, __clk_get_name(parent)); | |
593 | ||
1e6237e3 WS |
594 | case CLK_TYPE_GEN3_R: |
595 | /* RINT is default. Only if EXTALR is populated, we switch to it */ | |
596 | value = readl(base + CPG_RCKCR) & 0x3f; | |
597 | ||
598 | if (clk_get_rate(clks[CLK_EXTALR])) { | |
599 | parent = clks[CLK_EXTALR]; | |
600 | value |= BIT(15); | |
601 | } | |
602 | ||
603 | writel(value, base + CPG_RCKCR); | |
604 | break; | |
605 | ||
c5dae0df GU |
606 | default: |
607 | return ERR_PTR(-EINVAL); | |
608 | } | |
609 | ||
610 | return clk_register_fixed_factor(NULL, core->name, | |
611 | __clk_get_name(parent), 0, mult, div); | |
612 | } | |
613 | ||
614 | /* | |
615 | * Reset register definitions. | |
616 | */ | |
617 | #define MODEMR 0xe6160060 | |
618 | ||
619 | static u32 rcar_gen3_read_mode_pins(void) | |
620 | { | |
621 | void __iomem *modemr = ioremap_nocache(MODEMR, 4); | |
622 | u32 mode; | |
623 | ||
624 | BUG_ON(!modemr); | |
625 | mode = ioread32(modemr); | |
626 | iounmap(modemr); | |
627 | ||
628 | return mode; | |
629 | } | |
630 | ||
631 | static int __init r8a7795_cpg_mssr_init(struct device *dev) | |
632 | { | |
633 | u32 cpg_mode = rcar_gen3_read_mode_pins(); | |
634 | ||
635 | cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; | |
636 | if (!cpg_pll_config->extal_div) { | |
637 | dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); | |
638 | return -EINVAL; | |
639 | } | |
640 | ||
641 | return 0; | |
642 | } | |
643 | ||
644 | const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = { | |
645 | /* Core Clocks */ | |
646 | .core_clks = r8a7795_core_clks, | |
647 | .num_core_clks = ARRAY_SIZE(r8a7795_core_clks), | |
648 | .last_dt_core_clk = LAST_DT_CORE_CLK, | |
649 | .num_total_core_clks = MOD_CLK_BASE, | |
650 | ||
651 | /* Module Clocks */ | |
652 | .mod_clks = r8a7795_mod_clks, | |
653 | .num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks), | |
654 | .num_hw_mod_clks = 12 * 32, | |
655 | ||
656 | /* Critical Module Clocks */ | |
657 | .crit_mod_clks = r8a7795_crit_mod_clks, | |
658 | .num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks), | |
659 | ||
660 | /* Callbacks */ | |
661 | .init = r8a7795_cpg_mssr_init, | |
662 | .cpg_clk_register = r8a7795_cpg_clk_register, | |
663 | }; |