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9e288cef | 1 | // SPDX-License-Identifier: GPL-2.0 |
6449ab81 GU |
2 | /* |
3 | * r8a7791 Clock Pulse Generator / Module Standby and Software Reset | |
4 | * | |
5 | * Copyright (C) 2015-2017 Glider bvba | |
6 | * | |
7 | * Based on clk-rcar-gen2.c | |
8 | * | |
9 | * Copyright (C) 2013 Ideas On Board SPRL | |
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10 | */ |
11 | ||
12 | #include <linux/device.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/of.h> | |
16 | #include <linux/soc/renesas/rcar-rst.h> | |
17 | ||
18 | #include <dt-bindings/clock/r8a7791-cpg-mssr.h> | |
19 | ||
20 | #include "renesas-cpg-mssr.h" | |
21 | #include "rcar-gen2-cpg.h" | |
22 | ||
23 | enum clk_ids { | |
24 | /* Core Clock Outputs exported to DT */ | |
25 | LAST_DT_CORE_CLK = R8A7791_CLK_OSC, | |
26 | ||
27 | /* External Input Clocks */ | |
28 | CLK_EXTAL, | |
29 | CLK_USB_EXTAL, | |
30 | ||
31 | /* Internal Core Clocks */ | |
32 | CLK_MAIN, | |
33 | CLK_PLL0, | |
34 | CLK_PLL1, | |
35 | CLK_PLL3, | |
36 | CLK_PLL1_DIV2, | |
37 | ||
38 | /* Module Clocks */ | |
39 | MOD_CLK_BASE | |
40 | }; | |
41 | ||
42 | static struct cpg_core_clk r8a7791_core_clks[] __initdata = { | |
43 | /* External Clock Inputs */ | |
44 | DEF_INPUT("extal", CLK_EXTAL), | |
45 | DEF_INPUT("usb_extal", CLK_USB_EXTAL), | |
46 | ||
47 | /* Internal Core Clocks */ | |
48 | DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), | |
49 | DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), | |
50 | DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), | |
51 | DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN), | |
52 | ||
53 | DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), | |
54 | ||
55 | /* Core Clock Outputs */ | |
56 | DEF_BASE("z", R8A7791_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0), | |
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57 | DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1), |
58 | DEF_BASE("sdh", R8A7791_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), | |
59 | DEF_BASE("sd0", R8A7791_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), | |
60 | DEF_BASE("qspi", R8A7791_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), | |
61 | DEF_BASE("rcan", R8A7791_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL), | |
62 | ||
63 | DEF_FIXED("zg", R8A7791_CLK_ZG, CLK_PLL1, 3, 1), | |
64 | DEF_FIXED("zx", R8A7791_CLK_ZX, CLK_PLL1, 3, 1), | |
65 | DEF_FIXED("zs", R8A7791_CLK_ZS, CLK_PLL1, 6, 1), | |
66 | DEF_FIXED("hp", R8A7791_CLK_HP, CLK_PLL1, 12, 1), | |
67 | DEF_FIXED("i", R8A7791_CLK_I, CLK_PLL1, 2, 1), | |
68 | DEF_FIXED("b", R8A7791_CLK_B, CLK_PLL1, 12, 1), | |
6041ce57 | 69 | DEF_FIXED("lb", R8A7791_CLK_LB, CLK_PLL1, 24, 1), |
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70 | DEF_FIXED("p", R8A7791_CLK_P, CLK_PLL1, 24, 1), |
71 | DEF_FIXED("cl", R8A7791_CLK_CL, CLK_PLL1, 48, 1), | |
72 | DEF_FIXED("m2", R8A7791_CLK_M2, CLK_PLL1, 8, 1), | |
73 | DEF_FIXED("zb3", R8A7791_CLK_ZB3, CLK_PLL3, 4, 1), | |
74 | DEF_FIXED("zb3d2", R8A7791_CLK_ZB3D2, CLK_PLL3, 8, 1), | |
75 | DEF_FIXED("ddr", R8A7791_CLK_DDR, CLK_PLL3, 8, 1), | |
76 | DEF_FIXED("mp", R8A7791_CLK_MP, CLK_PLL1_DIV2, 15, 1), | |
77 | DEF_FIXED("cp", R8A7791_CLK_CP, CLK_EXTAL, 2, 1), | |
78 | DEF_FIXED("r", R8A7791_CLK_R, CLK_PLL1, 49152, 1), | |
79 | DEF_FIXED("osc", R8A7791_CLK_OSC, CLK_PLL1, 12288, 1), | |
80 | ||
81 | DEF_DIV6P1("sd2", R8A7791_CLK_SD2, CLK_PLL1_DIV2, 0x078), | |
82 | DEF_DIV6P1("sd3", R8A7791_CLK_SD3, CLK_PLL1_DIV2, 0x26c), | |
83 | DEF_DIV6P1("mmc0", R8A7791_CLK_MMC0, CLK_PLL1_DIV2, 0x240), | |
84 | DEF_DIV6P1("ssp", R8A7791_CLK_SSP, CLK_PLL1_DIV2, 0x248), | |
85 | DEF_DIV6P1("ssprs", R8A7791_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c), | |
86 | }; | |
87 | ||
88 | static const struct mssr_mod_clk r8a7791_mod_clks[] __initconst = { | |
89 | DEF_MOD("msiof0", 0, R8A7791_CLK_MP), | |
90 | DEF_MOD("vcp0", 101, R8A7791_CLK_ZS), | |
91 | DEF_MOD("vpc0", 103, R8A7791_CLK_ZS), | |
92 | DEF_MOD("jpu", 106, R8A7791_CLK_M2), | |
93 | DEF_MOD("ssp1", 109, R8A7791_CLK_ZS), | |
94 | DEF_MOD("tmu1", 111, R8A7791_CLK_P), | |
95 | DEF_MOD("3dg", 112, R8A7791_CLK_ZG), | |
96 | DEF_MOD("2d-dmac", 115, R8A7791_CLK_ZS), | |
97 | DEF_MOD("fdp1-1", 118, R8A7791_CLK_ZS), | |
98 | DEF_MOD("fdp1-0", 119, R8A7791_CLK_ZS), | |
99 | DEF_MOD("tmu3", 121, R8A7791_CLK_P), | |
100 | DEF_MOD("tmu2", 122, R8A7791_CLK_P), | |
101 | DEF_MOD("cmt0", 124, R8A7791_CLK_R), | |
102 | DEF_MOD("tmu0", 125, R8A7791_CLK_CP), | |
103 | DEF_MOD("vsp1du1", 127, R8A7791_CLK_ZS), | |
104 | DEF_MOD("vsp1du0", 128, R8A7791_CLK_ZS), | |
e41cb217 | 105 | DEF_MOD("vsps", 131, R8A7791_CLK_ZS), |
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106 | DEF_MOD("scifa2", 202, R8A7791_CLK_MP), |
107 | DEF_MOD("scifa1", 203, R8A7791_CLK_MP), | |
108 | DEF_MOD("scifa0", 204, R8A7791_CLK_MP), | |
109 | DEF_MOD("msiof2", 205, R8A7791_CLK_MP), | |
110 | DEF_MOD("scifb0", 206, R8A7791_CLK_MP), | |
111 | DEF_MOD("scifb1", 207, R8A7791_CLK_MP), | |
112 | DEF_MOD("msiof1", 208, R8A7791_CLK_MP), | |
113 | DEF_MOD("scifb2", 216, R8A7791_CLK_MP), | |
114 | DEF_MOD("sys-dmac1", 218, R8A7791_CLK_ZS), | |
115 | DEF_MOD("sys-dmac0", 219, R8A7791_CLK_ZS), | |
116 | DEF_MOD("tpu0", 304, R8A7791_CLK_CP), | |
117 | DEF_MOD("sdhi3", 311, R8A7791_CLK_SD3), | |
118 | DEF_MOD("sdhi2", 312, R8A7791_CLK_SD2), | |
119 | DEF_MOD("sdhi0", 314, R8A7791_CLK_SD0), | |
120 | DEF_MOD("mmcif0", 315, R8A7791_CLK_MMC0), | |
121 | DEF_MOD("iic0", 318, R8A7791_CLK_HP), | |
122 | DEF_MOD("pciec", 319, R8A7791_CLK_MP), | |
123 | DEF_MOD("iic1", 323, R8A7791_CLK_HP), | |
124 | DEF_MOD("usb3.0", 328, R8A7791_CLK_MP), | |
125 | DEF_MOD("cmt1", 329, R8A7791_CLK_R), | |
126 | DEF_MOD("usbhs-dmac0", 330, R8A7791_CLK_HP), | |
127 | DEF_MOD("usbhs-dmac1", 331, R8A7791_CLK_HP), | |
5ada6bee | 128 | DEF_MOD("rwdt", 402, R8A7791_CLK_R), |
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129 | DEF_MOD("irqc", 407, R8A7791_CLK_CP), |
130 | DEF_MOD("intc-sys", 408, R8A7791_CLK_ZS), | |
131 | DEF_MOD("audio-dmac1", 501, R8A7791_CLK_HP), | |
132 | DEF_MOD("audio-dmac0", 502, R8A7791_CLK_HP), | |
133 | DEF_MOD("adsp_mod", 506, R8A7791_CLK_ADSP), | |
134 | DEF_MOD("thermal", 522, CLK_EXTAL), | |
135 | DEF_MOD("pwm", 523, R8A7791_CLK_P), | |
136 | DEF_MOD("usb-ehci", 703, R8A7791_CLK_MP), | |
137 | DEF_MOD("usbhs", 704, R8A7791_CLK_HP), | |
138 | DEF_MOD("hscif2", 713, R8A7791_CLK_ZS), | |
139 | DEF_MOD("scif5", 714, R8A7791_CLK_P), | |
140 | DEF_MOD("scif4", 715, R8A7791_CLK_P), | |
141 | DEF_MOD("hscif1", 716, R8A7791_CLK_ZS), | |
142 | DEF_MOD("hscif0", 717, R8A7791_CLK_ZS), | |
143 | DEF_MOD("scif3", 718, R8A7791_CLK_P), | |
144 | DEF_MOD("scif2", 719, R8A7791_CLK_P), | |
145 | DEF_MOD("scif1", 720, R8A7791_CLK_P), | |
146 | DEF_MOD("scif0", 721, R8A7791_CLK_P), | |
147 | DEF_MOD("du1", 723, R8A7791_CLK_ZX), | |
148 | DEF_MOD("du0", 724, R8A7791_CLK_ZX), | |
149 | DEF_MOD("lvds0", 726, R8A7791_CLK_ZX), | |
150 | DEF_MOD("ipmmu-sgx", 800, R8A7791_CLK_ZX), | |
151 | DEF_MOD("mlb", 802, R8A7791_CLK_HP), | |
152 | DEF_MOD("vin2", 809, R8A7791_CLK_ZG), | |
153 | DEF_MOD("vin1", 810, R8A7791_CLK_ZG), | |
154 | DEF_MOD("vin0", 811, R8A7791_CLK_ZG), | |
155 | DEF_MOD("etheravb", 812, R8A7791_CLK_HP), | |
156 | DEF_MOD("ether", 813, R8A7791_CLK_P), | |
157 | DEF_MOD("sata1", 814, R8A7791_CLK_ZS), | |
158 | DEF_MOD("sata0", 815, R8A7791_CLK_ZS), | |
159 | DEF_MOD("gyro-adc", 901, R8A7791_CLK_P), | |
160 | DEF_MOD("gpio7", 904, R8A7791_CLK_CP), | |
161 | DEF_MOD("gpio6", 905, R8A7791_CLK_CP), | |
162 | DEF_MOD("gpio5", 907, R8A7791_CLK_CP), | |
163 | DEF_MOD("gpio4", 908, R8A7791_CLK_CP), | |
164 | DEF_MOD("gpio3", 909, R8A7791_CLK_CP), | |
165 | DEF_MOD("gpio2", 910, R8A7791_CLK_CP), | |
166 | DEF_MOD("gpio1", 911, R8A7791_CLK_CP), | |
167 | DEF_MOD("gpio0", 912, R8A7791_CLK_CP), | |
168 | DEF_MOD("can1", 915, R8A7791_CLK_P), | |
169 | DEF_MOD("can0", 916, R8A7791_CLK_P), | |
170 | DEF_MOD("qspi_mod", 917, R8A7791_CLK_QSPI), | |
171 | DEF_MOD("i2c5", 925, R8A7791_CLK_HP), | |
172 | DEF_MOD("iicdvfs", 926, R8A7791_CLK_CP), | |
173 | DEF_MOD("i2c4", 927, R8A7791_CLK_HP), | |
174 | DEF_MOD("i2c3", 928, R8A7791_CLK_HP), | |
175 | DEF_MOD("i2c2", 929, R8A7791_CLK_HP), | |
176 | DEF_MOD("i2c1", 930, R8A7791_CLK_HP), | |
177 | DEF_MOD("i2c0", 931, R8A7791_CLK_HP), | |
178 | DEF_MOD("ssi-all", 1005, R8A7791_CLK_P), | |
179 | DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), | |
180 | DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), | |
181 | DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), | |
182 | DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), | |
183 | DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), | |
184 | DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), | |
185 | DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), | |
186 | DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), | |
187 | DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), | |
188 | DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), | |
189 | DEF_MOD("scu-all", 1017, R8A7791_CLK_P), | |
190 | DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), | |
191 | DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), | |
192 | DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), | |
193 | DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), | |
194 | DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), | |
195 | DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), | |
196 | DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), | |
197 | DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), | |
198 | DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), | |
199 | DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), | |
200 | DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), | |
201 | DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), | |
202 | DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), | |
203 | DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), | |
204 | DEF_MOD("scifa3", 1106, R8A7791_CLK_MP), | |
205 | DEF_MOD("scifa4", 1107, R8A7791_CLK_MP), | |
206 | DEF_MOD("scifa5", 1108, R8A7791_CLK_MP), | |
207 | }; | |
208 | ||
209 | static const unsigned int r8a7791_crit_mod_clks[] __initconst = { | |
5ada6bee | 210 | MOD_CLK_ID(402), /* RWDT */ |
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211 | MOD_CLK_ID(408), /* INTC-SYS (GIC) */ |
212 | }; | |
213 | ||
214 | /* | |
215 | * CPG Clock Data | |
216 | */ | |
217 | ||
218 | /* | |
219 | * MD EXTAL PLL0 PLL1 PLL3 | |
220 | * 14 13 19 (MHz) *1 *1 | |
221 | *--------------------------------------------------- | |
222 | * 0 0 0 15 x172/2 x208/2 x106 | |
223 | * 0 0 1 15 x172/2 x208/2 x88 | |
224 | * 0 1 0 20 x130/2 x156/2 x80 | |
225 | * 0 1 1 20 x130/2 x156/2 x66 | |
226 | * 1 0 0 26 / 2 x200/2 x240/2 x122 | |
227 | * 1 0 1 26 / 2 x200/2 x240/2 x102 | |
228 | * 1 1 0 30 / 2 x172/2 x208/2 x106 | |
229 | * 1 1 1 30 / 2 x172/2 x208/2 x88 | |
230 | * | |
231 | * *1 : Table 7.5a indicates VCO output (PLLx = VCO/2) | |
232 | */ | |
233 | #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ | |
234 | (((md) & BIT(13)) >> 12) | \ | |
235 | (((md) & BIT(19)) >> 19)) | |
236 | static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = { | |
237 | { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 }, | |
238 | { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 }, | |
239 | }; | |
240 | ||
241 | static int __init r8a7791_cpg_mssr_init(struct device *dev) | |
242 | { | |
243 | const struct rcar_gen2_cpg_pll_config *cpg_pll_config; | |
244 | struct device_node *np = dev->of_node; | |
245 | unsigned int i; | |
246 | u32 cpg_mode; | |
247 | int error; | |
248 | ||
249 | error = rcar_rst_read_mode_pins(&cpg_mode); | |
250 | if (error) | |
251 | return error; | |
252 | ||
253 | cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; | |
254 | ||
255 | if (of_device_is_compatible(np, "renesas,r8a7793-cpg-mssr")) { | |
256 | /* R-Car M2-N uses a 1/5 divider for ZG */ | |
257 | for (i = 0; i < ARRAY_SIZE(r8a7791_core_clks); i++) | |
258 | if (r8a7791_core_clks[i].id == R8A7791_CLK_ZG) { | |
259 | r8a7791_core_clks[i].div = 5; | |
260 | break; | |
261 | } | |
262 | } | |
263 | return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode); | |
264 | } | |
265 | ||
266 | const struct cpg_mssr_info r8a7791_cpg_mssr_info __initconst = { | |
267 | /* Core Clocks */ | |
268 | .core_clks = r8a7791_core_clks, | |
269 | .num_core_clks = ARRAY_SIZE(r8a7791_core_clks), | |
270 | .last_dt_core_clk = LAST_DT_CORE_CLK, | |
271 | .num_total_core_clks = MOD_CLK_BASE, | |
272 | ||
273 | /* Module Clocks */ | |
274 | .mod_clks = r8a7791_mod_clks, | |
275 | .num_mod_clks = ARRAY_SIZE(r8a7791_mod_clks), | |
276 | .num_hw_mod_clks = 12 * 32, | |
277 | ||
278 | /* Critical Module Clocks */ | |
279 | .crit_mod_clks = r8a7791_crit_mod_clks, | |
280 | .num_crit_mod_clks = ARRAY_SIZE(r8a7791_crit_mod_clks), | |
281 | ||
282 | /* Callbacks */ | |
283 | .init = r8a7791_cpg_mssr_init, | |
284 | .cpg_clk_register = rcar_gen2_cpg_clk_register, | |
285 | }; |