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9e288cef | 1 | // SPDX-License-Identifier: GPL-2.0 |
9127d54b SS |
2 | /* |
3 | * r8a7745 Clock Pulse Generator / Module Standby and Software Reset | |
4 | * | |
5 | * Copyright (C) 2016 Cogent Embedded Inc. | |
9127d54b SS |
6 | */ |
7 | ||
8 | #include <linux/device.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/soc/renesas/rcar-rst.h> | |
12 | ||
13 | #include <dt-bindings/clock/r8a7745-cpg-mssr.h> | |
14 | ||
15 | #include "renesas-cpg-mssr.h" | |
16 | #include "rcar-gen2-cpg.h" | |
17 | ||
18 | enum clk_ids { | |
19 | /* Core Clock Outputs exported to DT */ | |
20 | LAST_DT_CORE_CLK = R8A7745_CLK_OSC, | |
21 | ||
22 | /* External Input Clocks */ | |
23 | CLK_EXTAL, | |
24 | CLK_USB_EXTAL, | |
25 | ||
26 | /* Internal Core Clocks */ | |
27 | CLK_MAIN, | |
28 | CLK_PLL0, | |
29 | CLK_PLL1, | |
30 | CLK_PLL3, | |
31 | CLK_PLL1_DIV2, | |
32 | ||
33 | /* Module Clocks */ | |
34 | MOD_CLK_BASE | |
35 | }; | |
36 | ||
37 | static const struct cpg_core_clk r8a7745_core_clks[] __initconst = { | |
38 | /* External Clock Inputs */ | |
39 | DEF_INPUT("extal", CLK_EXTAL), | |
40 | DEF_INPUT("usb_extal", CLK_USB_EXTAL), | |
41 | ||
42 | /* Internal Core Clocks */ | |
43 | DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), | |
44 | DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), | |
45 | DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), | |
46 | DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN), | |
47 | ||
48 | DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), | |
49 | ||
50 | /* Core Clock Outputs */ | |
9127d54b SS |
51 | DEF_BASE("sdh", R8A7745_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), |
52 | DEF_BASE("sd0", R8A7745_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), | |
53 | DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), | |
54 | DEF_BASE("rcan", R8A7745_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL), | |
55 | ||
56 | DEF_FIXED("z2", R8A7745_CLK_Z2, CLK_PLL0, 1, 1), | |
57 | DEF_FIXED("zg", R8A7745_CLK_ZG, CLK_PLL1, 6, 1), | |
58 | DEF_FIXED("zx", R8A7745_CLK_ZX, CLK_PLL1, 3, 1), | |
59 | DEF_FIXED("zs", R8A7745_CLK_ZS, CLK_PLL1, 6, 1), | |
60 | DEF_FIXED("hp", R8A7745_CLK_HP, CLK_PLL1, 12, 1), | |
61 | DEF_FIXED("b", R8A7745_CLK_B, CLK_PLL1, 12, 1), | |
83fab8ea | 62 | DEF_FIXED("lb", R8A7745_CLK_LB, CLK_PLL1, 24, 1), |
9127d54b SS |
63 | DEF_FIXED("p", R8A7745_CLK_P, CLK_PLL1, 24, 1), |
64 | DEF_FIXED("cl", R8A7745_CLK_CL, CLK_PLL1, 48, 1), | |
65 | DEF_FIXED("cp", R8A7745_CLK_CP, CLK_PLL1, 48, 1), | |
66 | DEF_FIXED("m2", R8A7745_CLK_M2, CLK_PLL1, 8, 1), | |
67 | DEF_FIXED("zb3", R8A7745_CLK_ZB3, CLK_PLL3, 4, 1), | |
68 | DEF_FIXED("zb3d2", R8A7745_CLK_ZB3D2, CLK_PLL3, 8, 1), | |
69 | DEF_FIXED("ddr", R8A7745_CLK_DDR, CLK_PLL3, 8, 1), | |
70 | DEF_FIXED("mp", R8A7745_CLK_MP, CLK_PLL1_DIV2, 15, 1), | |
71 | DEF_FIXED("cpex", R8A7745_CLK_CPEX, CLK_EXTAL, 2, 1), | |
72 | DEF_FIXED("r", R8A7745_CLK_R, CLK_PLL1, 49152, 1), | |
73 | DEF_FIXED("osc", R8A7745_CLK_OSC, CLK_PLL1, 12288, 1), | |
74 | ||
75 | DEF_DIV6P1("sd2", R8A7745_CLK_SD2, CLK_PLL1_DIV2, 0x078), | |
76 | DEF_DIV6P1("sd3", R8A7745_CLK_SD3, CLK_PLL1_DIV2, 0x26c), | |
77 | DEF_DIV6P1("mmc0", R8A7745_CLK_MMC0, CLK_PLL1_DIV2, 0x240), | |
78 | }; | |
79 | ||
80 | static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = { | |
81 | DEF_MOD("msiof0", 0, R8A7745_CLK_MP), | |
82 | DEF_MOD("vcp0", 101, R8A7745_CLK_ZS), | |
83 | DEF_MOD("vpc0", 103, R8A7745_CLK_ZS), | |
84 | DEF_MOD("tmu1", 111, R8A7745_CLK_P), | |
85 | DEF_MOD("3dg", 112, R8A7745_CLK_ZG), | |
86 | DEF_MOD("2d-dmac", 115, R8A7745_CLK_ZS), | |
87 | DEF_MOD("fdp1-0", 119, R8A7745_CLK_ZS), | |
88 | DEF_MOD("tmu3", 121, R8A7745_CLK_P), | |
89 | DEF_MOD("tmu2", 122, R8A7745_CLK_P), | |
90 | DEF_MOD("cmt0", 124, R8A7745_CLK_R), | |
91 | DEF_MOD("tmu0", 125, R8A7745_CLK_CP), | |
92 | DEF_MOD("vsp1du0", 128, R8A7745_CLK_ZS), | |
e41cb217 | 93 | DEF_MOD("vsps", 131, R8A7745_CLK_ZS), |
9127d54b SS |
94 | DEF_MOD("scifa2", 202, R8A7745_CLK_MP), |
95 | DEF_MOD("scifa1", 203, R8A7745_CLK_MP), | |
96 | DEF_MOD("scifa0", 204, R8A7745_CLK_MP), | |
97 | DEF_MOD("msiof2", 205, R8A7745_CLK_MP), | |
98 | DEF_MOD("scifb0", 206, R8A7745_CLK_MP), | |
99 | DEF_MOD("scifb1", 207, R8A7745_CLK_MP), | |
100 | DEF_MOD("msiof1", 208, R8A7745_CLK_MP), | |
101 | DEF_MOD("scifb2", 216, R8A7745_CLK_MP), | |
102 | DEF_MOD("sys-dmac1", 218, R8A7745_CLK_ZS), | |
103 | DEF_MOD("sys-dmac0", 219, R8A7745_CLK_ZS), | |
104 | DEF_MOD("tpu0", 304, R8A7745_CLK_CP), | |
105 | DEF_MOD("sdhi3", 311, R8A7745_CLK_SD3), | |
106 | DEF_MOD("sdhi2", 312, R8A7745_CLK_SD2), | |
107 | DEF_MOD("sdhi0", 314, R8A7745_CLK_SD0), | |
108 | DEF_MOD("mmcif0", 315, R8A7745_CLK_MMC0), | |
109 | DEF_MOD("iic0", 318, R8A7745_CLK_HP), | |
110 | DEF_MOD("iic1", 323, R8A7745_CLK_HP), | |
111 | DEF_MOD("cmt1", 329, R8A7745_CLK_R), | |
112 | DEF_MOD("usbhs-dmac0", 330, R8A7745_CLK_HP), | |
113 | DEF_MOD("usbhs-dmac1", 331, R8A7745_CLK_HP), | |
e0c0a2c4 | 114 | DEF_MOD("rwdt", 402, R8A7745_CLK_R), |
9127d54b SS |
115 | DEF_MOD("irqc", 407, R8A7745_CLK_CP), |
116 | DEF_MOD("intc-sys", 408, R8A7745_CLK_ZS), | |
117 | DEF_MOD("audio-dmac0", 502, R8A7745_CLK_HP), | |
118 | DEF_MOD("pwm", 523, R8A7745_CLK_P), | |
119 | DEF_MOD("usb-ehci", 703, R8A7745_CLK_MP), | |
120 | DEF_MOD("usbhs", 704, R8A7745_CLK_HP), | |
121 | DEF_MOD("hscif2", 713, R8A7745_CLK_ZS), | |
122 | DEF_MOD("scif5", 714, R8A7745_CLK_P), | |
123 | DEF_MOD("scif4", 715, R8A7745_CLK_P), | |
124 | DEF_MOD("hscif1", 716, R8A7745_CLK_ZS), | |
125 | DEF_MOD("hscif0", 717, R8A7745_CLK_ZS), | |
126 | DEF_MOD("scif3", 718, R8A7745_CLK_P), | |
127 | DEF_MOD("scif2", 719, R8A7745_CLK_P), | |
128 | DEF_MOD("scif1", 720, R8A7745_CLK_P), | |
129 | DEF_MOD("scif0", 721, R8A7745_CLK_P), | |
9dc0ddee | 130 | DEF_MOD("du1", 723, R8A7745_CLK_ZX), |
9127d54b SS |
131 | DEF_MOD("du0", 724, R8A7745_CLK_ZX), |
132 | DEF_MOD("ipmmu-sgx", 800, R8A7745_CLK_ZX), | |
133 | DEF_MOD("vin1", 810, R8A7745_CLK_ZG), | |
134 | DEF_MOD("vin0", 811, R8A7745_CLK_ZG), | |
135 | DEF_MOD("etheravb", 812, R8A7745_CLK_HP), | |
136 | DEF_MOD("ether", 813, R8A7745_CLK_P), | |
137 | DEF_MOD("gpio6", 905, R8A7745_CLK_CP), | |
138 | DEF_MOD("gpio5", 907, R8A7745_CLK_CP), | |
139 | DEF_MOD("gpio4", 908, R8A7745_CLK_CP), | |
140 | DEF_MOD("gpio3", 909, R8A7745_CLK_CP), | |
141 | DEF_MOD("gpio2", 910, R8A7745_CLK_CP), | |
142 | DEF_MOD("gpio1", 911, R8A7745_CLK_CP), | |
143 | DEF_MOD("gpio0", 912, R8A7745_CLK_CP), | |
144 | DEF_MOD("can1", 915, R8A7745_CLK_P), | |
145 | DEF_MOD("can0", 916, R8A7745_CLK_P), | |
146 | DEF_MOD("qspi_mod", 917, R8A7745_CLK_QSPI), | |
147 | DEF_MOD("i2c5", 925, R8A7745_CLK_HP), | |
148 | DEF_MOD("i2c4", 927, R8A7745_CLK_HP), | |
149 | DEF_MOD("i2c3", 928, R8A7745_CLK_HP), | |
150 | DEF_MOD("i2c2", 929, R8A7745_CLK_HP), | |
151 | DEF_MOD("i2c1", 930, R8A7745_CLK_HP), | |
152 | DEF_MOD("i2c0", 931, R8A7745_CLK_HP), | |
153 | DEF_MOD("ssi-all", 1005, R8A7745_CLK_P), | |
154 | DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), | |
155 | DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), | |
156 | DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), | |
157 | DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), | |
158 | DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), | |
159 | DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), | |
160 | DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), | |
161 | DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), | |
162 | DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), | |
163 | DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), | |
164 | DEF_MOD("scu-all", 1017, R8A7745_CLK_P), | |
165 | DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), | |
166 | DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), | |
167 | DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), | |
168 | DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), | |
9127d54b SS |
169 | DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), |
170 | DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), | |
171 | DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), | |
172 | DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), | |
173 | DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), | |
174 | DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), | |
9127d54b SS |
175 | DEF_MOD("scifa3", 1106, R8A7745_CLK_MP), |
176 | DEF_MOD("scifa4", 1107, R8A7745_CLK_MP), | |
177 | DEF_MOD("scifa5", 1108, R8A7745_CLK_MP), | |
178 | }; | |
179 | ||
180 | static const unsigned int r8a7745_crit_mod_clks[] __initconst = { | |
e0c0a2c4 | 181 | MOD_CLK_ID(402), /* RWDT */ |
9127d54b SS |
182 | MOD_CLK_ID(408), /* INTC-SYS (GIC) */ |
183 | }; | |
184 | ||
185 | /* | |
186 | * CPG Clock Data | |
187 | */ | |
188 | ||
189 | /* | |
190 | * MD EXTAL PLL0 PLL1 PLL3 | |
191 | * 14 13 19 (MHz) *1 *2 | |
192 | *--------------------------------------------------- | |
9127d54b | 193 | * 0 0 1 15 x200/3 x208/2 x88 |
9127d54b | 194 | * 0 1 1 20 x150/3 x156/2 x66 |
9127d54b | 195 | * 1 0 1 26 / 2 x230/3 x240/2 x102 |
9127d54b SS |
196 | * 1 1 1 30 / 2 x200/3 x208/2 x88 |
197 | * | |
198 | * *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3) | |
199 | * *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2) | |
200 | */ | |
5ed793b3 GU |
201 | #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ |
202 | (((md) & BIT(13)) >> 13)) | |
9127d54b SS |
203 | |
204 | static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = { | |
205 | /* EXTAL div PLL1 mult PLL3 mult PLL0 mult */ | |
9127d54b | 206 | { 1, 208, 88, 200 }, |
9127d54b | 207 | { 1, 156, 66, 150 }, |
9127d54b | 208 | { 2, 240, 102, 230 }, |
9127d54b SS |
209 | { 2, 208, 88, 200 }, |
210 | }; | |
211 | ||
212 | static int __init r8a7745_cpg_mssr_init(struct device *dev) | |
213 | { | |
214 | const struct rcar_gen2_cpg_pll_config *cpg_pll_config; | |
215 | u32 cpg_mode; | |
216 | int error; | |
217 | ||
218 | error = rcar_rst_read_mode_pins(&cpg_mode); | |
219 | if (error) | |
220 | return error; | |
221 | ||
222 | cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; | |
223 | ||
224 | return rcar_gen2_cpg_init(cpg_pll_config, 3, cpg_mode); | |
225 | } | |
226 | ||
227 | const struct cpg_mssr_info r8a7745_cpg_mssr_info __initconst = { | |
228 | /* Core Clocks */ | |
229 | .core_clks = r8a7745_core_clks, | |
230 | .num_core_clks = ARRAY_SIZE(r8a7745_core_clks), | |
231 | .last_dt_core_clk = LAST_DT_CORE_CLK, | |
232 | .num_total_core_clks = MOD_CLK_BASE, | |
233 | ||
234 | /* Module Clocks */ | |
235 | .mod_clks = r8a7745_mod_clks, | |
236 | .num_mod_clks = ARRAY_SIZE(r8a7745_mod_clks), | |
237 | .num_hw_mod_clks = 12 * 32, | |
238 | ||
239 | /* Critical Module Clocks */ | |
240 | .crit_mod_clks = r8a7745_crit_mod_clks, | |
241 | .num_crit_mod_clks = ARRAY_SIZE(r8a7745_crit_mod_clks), | |
242 | ||
243 | /* Callbacks */ | |
244 | .init = r8a7745_cpg_mssr_init, | |
245 | .cpg_clk_register = rcar_gen2_cpg_clk_register, | |
246 | }; |