[linux-block.git] / drivers / clk / renesas / clk-rz.c

// SPDX-License-Identifier: GPL-2.0
/*
 * RZ/A1 Core CPG Clocks
 *
 * Copyright (C) 2013 Ideas On Board SPRL
 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
 */

#include <linux/clk-provider.h>
#include <linux/clk/renesas.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>

#define CPG_FRQCR	0x10
#define CPG_FRQCR2	0x14

#define PPR0		0xFCFE3200
#define PIBC0		0xFCFE7000

#define MD_CLK(x)	((x >> 2) & 1)	/* P0_2 */

/* -----------------------------------------------------------------------------
 * Initialization
 */

static u16 __init rz_cpg_read_mode_pins(void)
{
	void __iomem *ppr0, *pibc0;
	u16 modes;

	ppr0 = ioremap(PPR0, 2);
	pibc0 = ioremap(PIBC0, 2);
	BUG_ON(!ppr0 || !pibc0);
	iowrite16(4, pibc0);	/* enable input buffer */
	modes = ioread16(ppr0);
	iounmap(ppr0);
	iounmap(pibc0);

	return modes;
}

static struct clk * __init
rz_cpg_register_clock(struct device_node *np, void __iomem *base,
		      const char *name)
{
	u32 val;
	unsigned mult;
	static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 };

	if (strcmp(name, "pll") == 0) {
		unsigned int cpg_mode = MD_CLK(rz_cpg_read_mode_pins());
		const char *parent_name = of_clk_get_parent_name(np, cpg_mode);

		mult = cpg_mode ? (32 / 4) : 30;

		return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1);
	}

	/* If mapping regs failed, skip non-pll clocks. System will boot anyhow */
	if (!base)
		return ERR_PTR(-ENXIO);

	/* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)
	 * and the constraint that always g <= i. To get the rz platform started,
	 * let them run at fixed current speed and implement the details later.
	 */
	if (strcmp(name, "i") == 0)
		val = (readl(base + CPG_FRQCR) >> 8) & 3;
	else if (strcmp(name, "g") == 0)
		val = readl(base + CPG_FRQCR2) & 3;
	else
		return ERR_PTR(-EINVAL);

	mult = frqcr_tab[val];
	return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3);
}

static void __init rz_cpg_clocks_init(struct device_node *np)
{
	struct clk_onecell_data *data;
	struct clk **clks;
	void __iomem *base;
	unsigned i;
	int num_clks;

	num_clks = of_property_count_strings(np, "clock-output-names");
	if (WARN(num_clks <= 0, "can't count CPG clocks\n"))
		return;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
	BUG_ON(!data || !clks);

	data->clks = clks;
	data->clk_num = num_clks;

	base = of_iomap(np, 0);

	for (i = 0; i < num_clks; ++i) {
		const char *name;
		struct clk *clk;

		of_property_read_string_index(np, "clock-output-names", i, &name);

		clk = rz_cpg_register_clock(np, base, name);
		if (IS_ERR(clk))
			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
			       __func__, np, name, PTR_ERR(clk));
		else
			data->clks[i] = clk;
	}

	of_clk_add_provider(np, of_clk_src_onecell_get, data);

	cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);
Commit	Line	Data
9e288cef	1	// SPDX-License-Identifier: GPL-2.0
a665962e	2	/*
d454cecc	3	* RZ/A1 Core CPG Clocks
a665962e WS	4	*
	5	* Copyright (C) 2013 Ideas On Board SPRL
	6	* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
a665962e WS	7	*/
	8
	9	#include <linux/clk-provider.h>
09c32427	10	#include <linux/clk/renesas.h>
a665962e	11	#include <linux/init.h>
62e59c4e	12	#include <linux/io.h>
a665962e WS	13	#include <linux/kernel.h>
	14	#include <linux/of.h>
	15	#include <linux/of_address.h>
	16	#include <linux/slab.h>
	17
a665962e WS	18	#define CPG_FRQCR 0x10
	19	#define CPG_FRQCR2 0x14
	20
b452dfe9 CB	21	#define PPR0 0xFCFE3200
	22	#define PIBC0 0xFCFE7000
	23
	24	#define MD_CLK(x) ((x >> 2) & 1) /* P0_2 */
	25
a665962e WS	26	/* -----------------------------------------------------------------------------
	27	* Initialization
	28	*/
	29
b452dfe9 CB	30	static u16 __init rz_cpg_read_mode_pins(void)
	31	{
	32	void __iomem ppr0, pibc0;
	33	u16 modes;
	34
4bdc0d67 CH	35	ppr0 = ioremap(PPR0, 2);
4bdc0d67 CH	36	pibc0 = ioremap(PIBC0, 2);
b452dfe9 CB	37	BUG_ON(!ppr0 \|\| !pibc0);
	38	iowrite16(4, pibc0); /* enable input buffer */
	39	modes = ioread16(ppr0);
	40	iounmap(ppr0);
	41	iounmap(pibc0);
	42
	43	return modes;
	44	}
	45
a665962e	46	static struct clk * __init
980bcaf3 GU	47	rz_cpg_register_clock(struct device_node np, void __iomem base,
980bcaf3 GU	48	const char *name)
a665962e WS	49	{
	50	u32 val;
	51	unsigned mult;
	52	static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 };
	53
	54	if (strcmp(name, "pll") == 0) {
b452dfe9	55	unsigned int cpg_mode = MD_CLK(rz_cpg_read_mode_pins());
a665962e WS	56	const char *parent_name = of_clk_get_parent_name(np, cpg_mode);
	57
	58	mult = cpg_mode ? (32 / 4) : 30;
	59
	60	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1);
	61	}
	62
	63	/* If mapping regs failed, skip non-pll clocks. System will boot anyhow */
980bcaf3	64	if (!base)
a665962e WS	65	return ERR_PTR(-ENXIO);
	66
	67	/* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)
	68	* and the constraint that always g <= i. To get the rz platform started,
	69	* let them run at fixed current speed and implement the details later.
	70	*/
	71	if (strcmp(name, "i") == 0)
980bcaf3	72	val = (readl(base + CPG_FRQCR) >> 8) & 3;
a665962e	73	else if (strcmp(name, "g") == 0)
980bcaf3	74	val = readl(base + CPG_FRQCR2) & 3;
a665962e WS	75	else
	76	return ERR_PTR(-EINVAL);
	77
	78	mult = frqcr_tab[val];
	79	return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3);
	80	}
	81
	82	static void __init rz_cpg_clocks_init(struct device_node *np)
	83	{
980bcaf3	84	struct clk_onecell_data *data;
a665962e	85	struct clk **clks;
980bcaf3	86	void __iomem *base;
a665962e WS	87	unsigned i;
	88	int num_clks;
	89
	90	num_clks = of_property_count_strings(np, "clock-output-names");
	91	if (WARN(num_clks <= 0, "can't count CPG clocks\n"))
	92	return;
	93
980bcaf3	94	data = kzalloc(sizeof(*data), GFP_KERNEL);
6396bb22	95	clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
980bcaf3	96	BUG_ON(!data \|\| !clks);
a665962e	97
980bcaf3 GU	98	data->clks = clks;
980bcaf3 GU	99	data->clk_num = num_clks;
a665962e	100
980bcaf3	101	base = of_iomap(np, 0);
a665962e WS	102
	103	for (i = 0; i < num_clks; ++i) {
	104	const char *name;
	105	struct clk *clk;
	106
	107	of_property_read_string_index(np, "clock-output-names", i, &name);
	108
980bcaf3	109	clk = rz_cpg_register_clock(np, base, name);
a665962e	110	if (IS_ERR(clk))
e665f029 RH	111	pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
e665f029 RH	112	__func__, np, name, PTR_ERR(clk));
a665962e	113	else
980bcaf3	114	data->clks[i] = clk;
a665962e WS	115	}
a665962e WS	116
980bcaf3	117	of_clk_add_provider(np, of_clk_src_onecell_get, data);
f04b486d GU	118
f04b486d GU	119	cpg_mstp_add_clk_domain(np);
a665962e WS	120	}
a665962e WS	121	CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);