[linux-2.6-block.git] / drivers / clk / renesas / clk-rz.c

// SPDX-License-Identifier: GPL-2.0
/*
 * RZ/A1 Core CPG Clocks
 *
 * Copyright (C) 2013 Ideas On Board SPRL
 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
 */

#include <linux/clk-provider.h>
#include <linux/clk/renesas.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>

struct rz_cpg {
	struct clk_onecell_data data;
	void __iomem *reg;
};

#define CPG_FRQCR	0x10
#define CPG_FRQCR2	0x14

#define PPR0		0xFCFE3200
#define PIBC0		0xFCFE7000

#define MD_CLK(x)	((x >> 2) & 1)	/* P0_2 */

/* -----------------------------------------------------------------------------
 * Initialization
 */

static u16 __init rz_cpg_read_mode_pins(void)
{
	void __iomem *ppr0, *pibc0;
	u16 modes;

	ppr0 = ioremap_nocache(PPR0, 2);
	pibc0 = ioremap_nocache(PIBC0, 2);
	BUG_ON(!ppr0 || !pibc0);
	iowrite16(4, pibc0);	/* enable input buffer */
	modes = ioread16(ppr0);
	iounmap(ppr0);
	iounmap(pibc0);

	return modes;
}

static struct clk * __init
rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name)
{
	u32 val;
	unsigned mult;
	static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 };

	if (strcmp(name, "pll") == 0) {
		unsigned int cpg_mode = MD_CLK(rz_cpg_read_mode_pins());
		const char *parent_name = of_clk_get_parent_name(np, cpg_mode);

		mult = cpg_mode ? (32 / 4) : 30;

		return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1);
	}

	/* If mapping regs failed, skip non-pll clocks. System will boot anyhow */
	if (!cpg->reg)
		return ERR_PTR(-ENXIO);

	/* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)
	 * and the constraint that always g <= i. To get the rz platform started,
	 * let them run at fixed current speed and implement the details later.
	 */
	if (strcmp(name, "i") == 0)
		val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3;
	else if (strcmp(name, "g") == 0)
		val = readl(cpg->reg + CPG_FRQCR2) & 3;
	else
		return ERR_PTR(-EINVAL);

	mult = frqcr_tab[val];
	return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3);
}

static void __init rz_cpg_clocks_init(struct device_node *np)
{
	struct rz_cpg *cpg;
	struct clk **clks;
	unsigned i;
	int num_clks;

	num_clks = of_property_count_strings(np, "clock-output-names");
	if (WARN(num_clks <= 0, "can't count CPG clocks\n"))
		return;

	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
	clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
	BUG_ON(!cpg || !clks);

	cpg->data.clks = clks;
	cpg->data.clk_num = num_clks;

	cpg->reg = of_iomap(np, 0);

	for (i = 0; i < num_clks; ++i) {
		const char *name;
		struct clk *clk;

		of_property_read_string_index(np, "clock-output-names", i, &name);

		clk = rz_cpg_register_clock(np, cpg, name);
		if (IS_ERR(clk))
			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
			       __func__, np, name, PTR_ERR(clk));
		else
			cpg->data.clks[i] = clk;
	}

	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);

	cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);
Commit	Line	Data
9e288cef	1	// SPDX-License-Identifier: GPL-2.0
a665962e	2	/*
d454cecc	3	* RZ/A1 Core CPG Clocks
a665962e WS	4	*
	5	* Copyright (C) 2013 Ideas On Board SPRL
	6	* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
a665962e WS	7	*/
	8
	9	#include <linux/clk-provider.h>
09c32427	10	#include <linux/clk/renesas.h>
a665962e WS	11	#include <linux/init.h>
	12	#include <linux/kernel.h>
	13	#include <linux/of.h>
	14	#include <linux/of_address.h>
	15	#include <linux/slab.h>
	16
	17	struct rz_cpg {
	18	struct clk_onecell_data data;
	19	void __iomem *reg;
	20	};
	21
	22	#define CPG_FRQCR 0x10
	23	#define CPG_FRQCR2 0x14
	24
b452dfe9 CB	25	#define PPR0 0xFCFE3200
	26	#define PIBC0 0xFCFE7000
	27
	28	#define MD_CLK(x) ((x >> 2) & 1) /* P0_2 */
	29
a665962e WS	30	/* -----------------------------------------------------------------------------
	31	* Initialization
	32	*/
	33
b452dfe9 CB	34	static u16 __init rz_cpg_read_mode_pins(void)
	35	{
	36	void __iomem ppr0, pibc0;
	37	u16 modes;
	38
	39	ppr0 = ioremap_nocache(PPR0, 2);
	40	pibc0 = ioremap_nocache(PIBC0, 2);
	41	BUG_ON(!ppr0 \|\| !pibc0);
	42	iowrite16(4, pibc0); /* enable input buffer */
	43	modes = ioread16(ppr0);
	44	iounmap(ppr0);
	45	iounmap(pibc0);
	46
	47	return modes;
	48	}
	49
a665962e WS	50	static struct clk * __init
	51	rz_cpg_register_clock(struct device_node np, struct rz_cpg cpg, const char *name)
	52	{
	53	u32 val;
	54	unsigned mult;
	55	static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 };
	56
	57	if (strcmp(name, "pll") == 0) {
b452dfe9	58	unsigned int cpg_mode = MD_CLK(rz_cpg_read_mode_pins());
a665962e WS	59	const char *parent_name = of_clk_get_parent_name(np, cpg_mode);
	60
	61	mult = cpg_mode ? (32 / 4) : 30;
	62
	63	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1);
	64	}
	65
	66	/* If mapping regs failed, skip non-pll clocks. System will boot anyhow */
	67	if (!cpg->reg)
	68	return ERR_PTR(-ENXIO);
	69
	70	/* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)
	71	* and the constraint that always g <= i. To get the rz platform started,
	72	* let them run at fixed current speed and implement the details later.
	73	*/
	74	if (strcmp(name, "i") == 0)
fcf371b3	75	val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3;
a665962e	76	else if (strcmp(name, "g") == 0)
fcf371b3	77	val = readl(cpg->reg + CPG_FRQCR2) & 3;
a665962e WS	78	else
	79	return ERR_PTR(-EINVAL);
	80
	81	mult = frqcr_tab[val];
	82	return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3);
	83	}
	84
	85	static void __init rz_cpg_clocks_init(struct device_node *np)
	86	{
	87	struct rz_cpg *cpg;
	88	struct clk **clks;
	89	unsigned i;
	90	int num_clks;
	91
	92	num_clks = of_property_count_strings(np, "clock-output-names");
	93	if (WARN(num_clks <= 0, "can't count CPG clocks\n"))
	94	return;
	95
	96	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
6396bb22	97	clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
a665962e WS	98	BUG_ON(!cpg \|\| !clks);
	99
	100	cpg->data.clks = clks;
	101	cpg->data.clk_num = num_clks;
	102
	103	cpg->reg = of_iomap(np, 0);
	104
	105	for (i = 0; i < num_clks; ++i) {
	106	const char *name;
	107	struct clk *clk;
	108
	109	of_property_read_string_index(np, "clock-output-names", i, &name);
	110
	111	clk = rz_cpg_register_clock(np, cpg, name);
	112	if (IS_ERR(clk))
e665f029 RH	113	pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
e665f029 RH	114	__func__, np, name, PTR_ERR(clk));
a665962e WS	115	else
	116	cpg->data.clks[i] = clk;
	117	}
	118
	119	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
f04b486d GU	120
f04b486d GU	121	cpg_mstp_add_clk_domain(np);
a665962e WS	122	}
a665962e WS	123	CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);