[linux-block.git] / drivers / clk / renesas / clk-r8a73a4.c

// SPDX-License-Identifier: GPL-2.0
/*
 * r8a73a4 Core CPG Clocks
 *
 * Copyright (C) 2014  Ulrich Hecht
 */

#include <linux/clk-provider.h>
#include <linux/clk/renesas.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/spinlock.h>

struct r8a73a4_cpg {
	struct clk_onecell_data data;
	spinlock_t lock;
};

#define CPG_CKSCR	0xc0
#define CPG_FRQCRA	0x00
#define CPG_FRQCRB	0x04
#define CPG_FRQCRC	0xe0
#define CPG_PLL0CR	0xd8
#define CPG_PLL1CR	0x28
#define CPG_PLL2CR	0x2c
#define CPG_PLL2HCR	0xe4
#define CPG_PLL2SCR	0xf4

struct div4_clk {
	const char *name;
	unsigned int reg;
	unsigned int shift;
};

static struct div4_clk div4_clks[] = {
	{ "i",	CPG_FRQCRA, 20 },
	{ "m3", CPG_FRQCRA, 12 },
	{ "b",	CPG_FRQCRA,  8 },
	{ "m1", CPG_FRQCRA,  4 },
	{ "m2", CPG_FRQCRA,  0 },
	{ "zx", CPG_FRQCRB, 12 },
	{ "zs", CPG_FRQCRB,  8 },
	{ "hp", CPG_FRQCRB,  4 },
	{ NULL, 0, 0 },
};

static const struct clk_div_table div4_div_table[] = {
	{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
	{ 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
	{ 12, 10 }, { 0, 0 }
};

static struct clk * __init
r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
			   void __iomem *base, const char *name)
{
	const struct clk_div_table *table = NULL;
	const char *parent_name;
	unsigned int shift, reg;
	unsigned int mult = 1;
	unsigned int div = 1;


	if (!strcmp(name, "main")) {
		u32 ckscr = readl(base + CPG_CKSCR);

		switch ((ckscr >> 28) & 3) {
		case 0:	/* extal1 */
			parent_name = of_clk_get_parent_name(np, 0);
			break;
		case 1:	/* extal1 / 2 */
			parent_name = of_clk_get_parent_name(np, 0);
			div = 2;
			break;
		case 2: /* extal2 */
			parent_name = of_clk_get_parent_name(np, 1);
			break;
		case 3: /* extal2 / 2 */
			parent_name = of_clk_get_parent_name(np, 1);
			div = 2;
			break;
		}
	} else if (!strcmp(name, "pll0")) {
		/* PLL0/1 are configurable multiplier clocks. Register them as
		 * fixed factor clocks for now as there's no generic multiplier
		 * clock implementation and we currently have no need to change
		 * the multiplier value.
		 */
		u32 value = readl(base + CPG_PLL0CR);

		parent_name = "main";
		mult = ((value >> 24) & 0x7f) + 1;
		if (value & BIT(20))
			div = 2;
	} else if (!strcmp(name, "pll1")) {
		u32 value = readl(base + CPG_PLL1CR);

		parent_name = "main";
		/* XXX: enable bit? */
		mult = ((value >> 24) & 0x7f) + 1;
		if (value & BIT(7))
			div = 2;
	} else if (!strncmp(name, "pll2", 4)) {
		u32 value, cr;

		switch (name[4]) {
		case 0:
			cr = CPG_PLL2CR;
			break;
		case 's':
			cr = CPG_PLL2SCR;
			break;
		case 'h':
			cr = CPG_PLL2HCR;
			break;
		default:
			return ERR_PTR(-EINVAL);
		}
		value = readl(base + cr);
		switch ((value >> 5) & 7) {
		case 0:
			parent_name = "main";
			div = 2;
			break;
		case 1:
			parent_name = "extal2";
			div = 2;
			break;
		case 3:
			parent_name = "extal2";
			div = 4;
			break;
		case 4:
			parent_name = "main";
			break;
		case 5:
			parent_name = "extal2";
			break;
		default:
			pr_warn("%s: unexpected parent of %s\n", __func__,
				name);
			return ERR_PTR(-EINVAL);
		}
		/* XXX: enable bit? */
		mult = ((value >> 24) & 0x7f) + 1;
	} else if (!strcmp(name, "z") || !strcmp(name, "z2")) {
		u32 shift = 8;

		parent_name = "pll0";
		if (name[1] == '2') {
			div = 2;
			shift = 0;
		}
		div *= 32;
		mult = 0x20 - ((readl(base + CPG_FRQCRC) >> shift) & 0x1f);
	} else {
		struct div4_clk *c;

		for (c = div4_clks; c->name; c++) {
			if (!strcmp(name, c->name))
				break;
		}
		if (!c->name)
			return ERR_PTR(-EINVAL);

		parent_name = "pll1";
		table = div4_div_table;
		reg = c->reg;
		shift = c->shift;
	}

	if (!table) {
		return clk_register_fixed_factor(NULL, name, parent_name, 0,
						 mult, div);
	} else {
		return clk_register_divider_table(NULL, name, parent_name, 0,
						  base + reg, shift, 4, 0,
						  table, &cpg->lock);
	}
}

static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
{
	struct r8a73a4_cpg *cpg;
	void __iomem *base;
	struct clk **clks;
	unsigned int i;
	int num_clks;

	num_clks = of_property_count_strings(np, "clock-output-names");
	if (num_clks < 0) {
		pr_err("%s: failed to count clocks\n", __func__);
		return;
	}

	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
	clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
	if (cpg == NULL || clks == NULL) {
		/* We're leaking memory on purpose, there's no point in cleaning
		 * up as the system won't boot anyway.
		 */
		return;
	}

	spin_lock_init(&cpg->lock);

	cpg->data.clks = clks;
	cpg->data.clk_num = num_clks;

	base = of_iomap(np, 0);
	if (WARN_ON(base == NULL))
		return;

	for (i = 0; i < num_clks; ++i) {
		const char *name;
		struct clk *clk;

		of_property_read_string_index(np, "clock-output-names", i,
					      &name);

		clk = r8a73a4_cpg_register_clock(np, cpg, base, name);
		if (IS_ERR(clk))
			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
			       __func__, np, name, PTR_ERR(clk));
		else
			cpg->data.clks[i] = clk;
	}

	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
}
CLK_OF_DECLARE(r8a73a4_cpg_clks, "renesas,r8a73a4-cpg-clocks",
	       r8a73a4_cpg_clocks_init);
Commit	Line	Data
9e288cef	1	// SPDX-License-Identifier: GPL-2.0
596bdcf7 UH	2	/*
	3	* r8a73a4 Core CPG Clocks
	4	*
	5	* Copyright (C) 2014 Ulrich Hecht
596bdcf7 UH	6	*/
	7
	8	#include <linux/clk-provider.h>
09c32427	9	#include <linux/clk/renesas.h>
596bdcf7	10	#include <linux/init.h>
62e59c4e	11	#include <linux/io.h>
596bdcf7	12	#include <linux/kernel.h>
5a1cfafa	13	#include <linux/slab.h>
596bdcf7 UH	14	#include <linux/of.h>
	15	#include <linux/of_address.h>
	16	#include <linux/spinlock.h>
	17
	18	struct r8a73a4_cpg {
	19	struct clk_onecell_data data;
	20	spinlock_t lock;
596bdcf7 UH	21	};
	22
	23	#define CPG_CKSCR 0xc0
	24	#define CPG_FRQCRA 0x00
	25	#define CPG_FRQCRB 0x04
	26	#define CPG_FRQCRC 0xe0
	27	#define CPG_PLL0CR 0xd8
	28	#define CPG_PLL1CR 0x28
	29	#define CPG_PLL2CR 0x2c
	30	#define CPG_PLL2HCR 0xe4
	31	#define CPG_PLL2SCR 0xf4
	32
596bdcf7 UH	33	struct div4_clk {
	34	const char *name;
	35	unsigned int reg;
	36	unsigned int shift;
	37	};
	38
	39	static struct div4_clk div4_clks[] = {
	40	{ "i", CPG_FRQCRA, 20 },
	41	{ "m3", CPG_FRQCRA, 12 },
	42	{ "b", CPG_FRQCRA, 8 },
	43	{ "m1", CPG_FRQCRA, 4 },
	44	{ "m2", CPG_FRQCRA, 0 },
	45	{ "zx", CPG_FRQCRB, 12 },
	46	{ "zs", CPG_FRQCRB, 8 },
	47	{ "hp", CPG_FRQCRB, 4 },
	48	{ NULL, 0, 0 },
	49	};
	50
	51	static const struct clk_div_table div4_div_table[] = {
	52	{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
	53	{ 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
	54	{ 12, 10 }, { 0, 0 }
	55	};
	56
	57	static struct clk * __init
	58	r8a73a4_cpg_register_clock(struct device_node np, struct r8a73a4_cpg cpg,
65d012e4	59	void __iomem base, const char name)
596bdcf7 UH	60	{
	61	const struct clk_div_table *table = NULL;
	62	const char *parent_name;
	63	unsigned int shift, reg;
	64	unsigned int mult = 1;
	65	unsigned int div = 1;
	66
	67
	68	if (!strcmp(name, "main")) {
65d012e4	69	u32 ckscr = readl(base + CPG_CKSCR);
596bdcf7 UH	70
	71	switch ((ckscr >> 28) & 3) {
	72	case 0: /* extal1 */
	73	parent_name = of_clk_get_parent_name(np, 0);
	74	break;
	75	case 1: /* extal1 / 2 */
	76	parent_name = of_clk_get_parent_name(np, 0);
	77	div = 2;
	78	break;
	79	case 2: /* extal2 */
	80	parent_name = of_clk_get_parent_name(np, 1);
	81	break;
	82	case 3: /* extal2 / 2 */
	83	parent_name = of_clk_get_parent_name(np, 1);
	84	div = 2;
	85	break;
	86	}
	87	} else if (!strcmp(name, "pll0")) {
	88	/* PLL0/1 are configurable multiplier clocks. Register them as
	89	* fixed factor clocks for now as there's no generic multiplier
	90	* clock implementation and we currently have no need to change
	91	* the multiplier value.
	92	*/
65d012e4	93	u32 value = readl(base + CPG_PLL0CR);
596bdcf7 UH	94
	95	parent_name = "main";
	96	mult = ((value >> 24) & 0x7f) + 1;
	97	if (value & BIT(20))
	98	div = 2;
	99	} else if (!strcmp(name, "pll1")) {
65d012e4	100	u32 value = readl(base + CPG_PLL1CR);
596bdcf7 UH	101
	102	parent_name = "main";
	103	/* XXX: enable bit? */
	104	mult = ((value >> 24) & 0x7f) + 1;
	105	if (value & BIT(7))
	106	div = 2;
	107	} else if (!strncmp(name, "pll2", 4)) {
	108	u32 value, cr;
	109
	110	switch (name[4]) {
	111	case 0:
	112	cr = CPG_PLL2CR;
	113	break;
	114	case 's':
	115	cr = CPG_PLL2SCR;
	116	break;
	117	case 'h':
	118	cr = CPG_PLL2HCR;
	119	break;
	120	default:
	121	return ERR_PTR(-EINVAL);
	122	}
65d012e4	123	value = readl(base + cr);
596bdcf7 UH	124	switch ((value >> 5) & 7) {
	125	case 0:
	126	parent_name = "main";
	127	div = 2;
	128	break;
	129	case 1:
	130	parent_name = "extal2";
	131	div = 2;
	132	break;
	133	case 3:
	134	parent_name = "extal2";
	135	div = 4;
	136	break;
	137	case 4:
	138	parent_name = "main";
	139	break;
	140	case 5:
	141	parent_name = "extal2";
	142	break;
	143	default:
	144	pr_warn("%s: unexpected parent of %s\n", __func__,
	145	name);
	146	return ERR_PTR(-EINVAL);
	147	}
	148	/* XXX: enable bit? */
	149	mult = ((value >> 24) & 0x7f) + 1;
	150	} else if (!strcmp(name, "z") \|\| !strcmp(name, "z2")) {
	151	u32 shift = 8;
	152
	153	parent_name = "pll0";
	154	if (name[1] == '2') {
	155	div = 2;
	156	shift = 0;
	157	}
	158	div *= 32;
65d012e4	159	mult = 0x20 - ((readl(base + CPG_FRQCRC) >> shift) & 0x1f);
596bdcf7 UH	160	} else {
	161	struct div4_clk *c;
	162
	163	for (c = div4_clks; c->name; c++) {
	164	if (!strcmp(name, c->name))
	165	break;
	166	}
	167	if (!c->name)
	168	return ERR_PTR(-EINVAL);
	169
	170	parent_name = "pll1";
	171	table = div4_div_table;
	172	reg = c->reg;
	173	shift = c->shift;
	174	}
	175
	176	if (!table) {
	177	return clk_register_fixed_factor(NULL, name, parent_name, 0,
	178	mult, div);
	179	} else {
	180	return clk_register_divider_table(NULL, name, parent_name, 0,
65d012e4	181	base + reg, shift, 4, 0,
596bdcf7 UH	182	table, &cpg->lock);
	183	}
	184	}
	185
	186	static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
	187	{
	188	struct r8a73a4_cpg *cpg;
65d012e4	189	void __iomem *base;
596bdcf7 UH	190	struct clk **clks;
	191	unsigned int i;
	192	int num_clks;
	193
	194	num_clks = of_property_count_strings(np, "clock-output-names");
	195	if (num_clks < 0) {
	196	pr_err("%s: failed to count clocks\n", __func__);
	197	return;
	198	}
	199
	200	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
	201	clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
	202	if (cpg == NULL \|\| clks == NULL) {
	203	/* We're leaking memory on purpose, there's no point in cleaning
	204	* up as the system won't boot anyway.
	205	*/
	206	return;
	207	}
	208
	209	spin_lock_init(&cpg->lock);
	210
	211	cpg->data.clks = clks;
	212	cpg->data.clk_num = num_clks;
	213
65d012e4 GU	214	base = of_iomap(np, 0);
65d012e4 GU	215	if (WARN_ON(base == NULL))
596bdcf7 UH	216	return;
	217
	218	for (i = 0; i < num_clks; ++i) {
	219	const char *name;
	220	struct clk *clk;
	221
	222	of_property_read_string_index(np, "clock-output-names", i,
	223	&name);
	224
65d012e4	225	clk = r8a73a4_cpg_register_clock(np, cpg, base, name);
596bdcf7	226	if (IS_ERR(clk))
e665f029 RH	227	pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
e665f029 RH	228	__func__, np, name, PTR_ERR(clk));
596bdcf7 UH	229	else
	230	cpg->data.clks[i] = clk;
	231	}
	232
	233	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
	234	}
	235	CLK_OF_DECLARE(r8a73a4_cpg_clks, "renesas,r8a73a4-cpg-clocks",
	236	r8a73a4_cpg_clocks_init);