[linux-block.git] / drivers / clk / renesas / clk-r8a73a4.c

/*
 * r8a73a4 Core CPG Clocks
 *
 * Copyright (C) 2014  Ulrich Hecht
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 */

#include <linux/clk-provider.h>
#include <linux/clk/renesas.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/spinlock.h>

struct r8a73a4_cpg {
	struct clk_onecell_data data;
	spinlock_t lock;
	void __iomem *reg;
};

#define CPG_CKSCR	0xc0
#define CPG_FRQCRA	0x00
#define CPG_FRQCRB	0x04
#define CPG_FRQCRC	0xe0
#define CPG_PLL0CR	0xd8
#define CPG_PLL1CR	0x28
#define CPG_PLL2CR	0x2c
#define CPG_PLL2HCR	0xe4
#define CPG_PLL2SCR	0xf4

#define CLK_ENABLE_ON_INIT BIT(0)

struct div4_clk {
	const char *name;
	unsigned int reg;
	unsigned int shift;
};

static struct div4_clk div4_clks[] = {
	{ "i",	CPG_FRQCRA, 20 },
	{ "m3", CPG_FRQCRA, 12 },
	{ "b",	CPG_FRQCRA,  8 },
	{ "m1", CPG_FRQCRA,  4 },
	{ "m2", CPG_FRQCRA,  0 },
	{ "zx", CPG_FRQCRB, 12 },
	{ "zs", CPG_FRQCRB,  8 },
	{ "hp", CPG_FRQCRB,  4 },
	{ NULL, 0, 0 },
};

static const struct clk_div_table div4_div_table[] = {
	{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
	{ 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
	{ 12, 10 }, { 0, 0 }
};

static struct clk * __init
r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
			     const char *name)
{
	const struct clk_div_table *table = NULL;
	const char *parent_name;
	unsigned int shift, reg;
	unsigned int mult = 1;
	unsigned int div = 1;


	if (!strcmp(name, "main")) {
		u32 ckscr = readl(cpg->reg + CPG_CKSCR);

		switch ((ckscr >> 28) & 3) {
		case 0:	/* extal1 */
			parent_name = of_clk_get_parent_name(np, 0);
			break;
		case 1:	/* extal1 / 2 */
			parent_name = of_clk_get_parent_name(np, 0);
			div = 2;
			break;
		case 2: /* extal2 */
			parent_name = of_clk_get_parent_name(np, 1);
			break;
		case 3: /* extal2 / 2 */
			parent_name = of_clk_get_parent_name(np, 1);
			div = 2;
			break;
		}
	} else if (!strcmp(name, "pll0")) {
		/* PLL0/1 are configurable multiplier clocks. Register them as
		 * fixed factor clocks for now as there's no generic multiplier
		 * clock implementation and we currently have no need to change
		 * the multiplier value.
		 */
		u32 value = readl(cpg->reg + CPG_PLL0CR);

		parent_name = "main";
		mult = ((value >> 24) & 0x7f) + 1;
		if (value & BIT(20))
			div = 2;
	} else if (!strcmp(name, "pll1")) {
		u32 value = readl(cpg->reg + CPG_PLL1CR);

		parent_name = "main";
		/* XXX: enable bit? */
		mult = ((value >> 24) & 0x7f) + 1;
		if (value & BIT(7))
			div = 2;
	} else if (!strncmp(name, "pll2", 4)) {
		u32 value, cr;

		switch (name[4]) {
		case 0:
			cr = CPG_PLL2CR;
			break;
		case 's':
			cr = CPG_PLL2SCR;
			break;
		case 'h':
			cr = CPG_PLL2HCR;
			break;
		default:
			return ERR_PTR(-EINVAL);
		}
		value = readl(cpg->reg + cr);
		switch ((value >> 5) & 7) {
		case 0:
			parent_name = "main";
			div = 2;
			break;
		case 1:
			parent_name = "extal2";
			div = 2;
			break;
		case 3:
			parent_name = "extal2";
			div = 4;
			break;
		case 4:
			parent_name = "main";
			break;
		case 5:
			parent_name = "extal2";
			break;
		default:
			pr_warn("%s: unexpected parent of %s\n", __func__,
				name);
			return ERR_PTR(-EINVAL);
		}
		/* XXX: enable bit? */
		mult = ((value >> 24) & 0x7f) + 1;
	} else if (!strcmp(name, "z") || !strcmp(name, "z2")) {
		u32 shift = 8;

		parent_name = "pll0";
		if (name[1] == '2') {
			div = 2;
			shift = 0;
		}
		div *= 32;
		mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f);
	} else {
		struct div4_clk *c;

		for (c = div4_clks; c->name; c++) {
			if (!strcmp(name, c->name))
				break;
		}
		if (!c->name)
			return ERR_PTR(-EINVAL);

		parent_name = "pll1";
		table = div4_div_table;
		reg = c->reg;
		shift = c->shift;
	}

	if (!table) {
		return clk_register_fixed_factor(NULL, name, parent_name, 0,
						 mult, div);
	} else {
		return clk_register_divider_table(NULL, name, parent_name, 0,
						  cpg->reg + reg, shift, 4, 0,
						  table, &cpg->lock);
	}
}

static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
{
	struct r8a73a4_cpg *cpg;
	struct clk **clks;
	unsigned int i;
	int num_clks;

	num_clks = of_property_count_strings(np, "clock-output-names");
	if (num_clks < 0) {
		pr_err("%s: failed to count clocks\n", __func__);
		return;
	}

	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
	clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
	if (cpg == NULL || clks == NULL) {
		/* We're leaking memory on purpose, there's no point in cleaning
		 * up as the system won't boot anyway.
		 */
		return;
	}

	spin_lock_init(&cpg->lock);

	cpg->data.clks = clks;
	cpg->data.clk_num = num_clks;

	cpg->reg = of_iomap(np, 0);
	if (WARN_ON(cpg->reg == NULL))
		return;

	for (i = 0; i < num_clks; ++i) {
		const char *name;
		struct clk *clk;

		of_property_read_string_index(np, "clock-output-names", i,
					      &name);

		clk = r8a73a4_cpg_register_clock(np, cpg, name);
		if (IS_ERR(clk))
			pr_err("%s: failed to register %s %s clock (%ld)\n",
			       __func__, np->name, name, PTR_ERR(clk));
		else
			cpg->data.clks[i] = clk;
	}

	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
}
CLK_OF_DECLARE(r8a73a4_cpg_clks, "renesas,r8a73a4-cpg-clocks",
	       r8a73a4_cpg_clocks_init);
Commit	Line	Data
596bdcf7 UH	1	/*
	2	* r8a73a4 Core CPG Clocks
	3	*
	4	* Copyright (C) 2014 Ulrich Hecht
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; version 2 of the License.
	9	*/
	10
	11	#include <linux/clk-provider.h>
09c32427	12	#include <linux/clk/renesas.h>
596bdcf7 UH	13	#include <linux/init.h>
596bdcf7 UH	14	#include <linux/kernel.h>
5a1cfafa	15	#include <linux/slab.h>
596bdcf7 UH	16	#include <linux/of.h>
	17	#include <linux/of_address.h>
	18	#include <linux/spinlock.h>
	19
	20	struct r8a73a4_cpg {
	21	struct clk_onecell_data data;
	22	spinlock_t lock;
	23	void __iomem *reg;
	24	};
	25
	26	#define CPG_CKSCR 0xc0
	27	#define CPG_FRQCRA 0x00
	28	#define CPG_FRQCRB 0x04
	29	#define CPG_FRQCRC 0xe0
	30	#define CPG_PLL0CR 0xd8
	31	#define CPG_PLL1CR 0x28
	32	#define CPG_PLL2CR 0x2c
	33	#define CPG_PLL2HCR 0xe4
	34	#define CPG_PLL2SCR 0xf4
	35
	36	#define CLK_ENABLE_ON_INIT BIT(0)
	37
	38	struct div4_clk {
	39	const char *name;
	40	unsigned int reg;
	41	unsigned int shift;
	42	};
	43
	44	static struct div4_clk div4_clks[] = {
	45	{ "i", CPG_FRQCRA, 20 },
	46	{ "m3", CPG_FRQCRA, 12 },
	47	{ "b", CPG_FRQCRA, 8 },
	48	{ "m1", CPG_FRQCRA, 4 },
	49	{ "m2", CPG_FRQCRA, 0 },
	50	{ "zx", CPG_FRQCRB, 12 },
	51	{ "zs", CPG_FRQCRB, 8 },
	52	{ "hp", CPG_FRQCRB, 4 },
	53	{ NULL, 0, 0 },
	54	};
	55
	56	static const struct clk_div_table div4_div_table[] = {
	57	{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
	58	{ 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
	59	{ 12, 10 }, { 0, 0 }
	60	};
	61
	62	static struct clk * __init
	63	r8a73a4_cpg_register_clock(struct device_node np, struct r8a73a4_cpg cpg,
	64	const char *name)
	65	{
	66	const struct clk_div_table *table = NULL;
	67	const char *parent_name;
	68	unsigned int shift, reg;
	69	unsigned int mult = 1;
	70	unsigned int div = 1;
	71
	72
	73	if (!strcmp(name, "main")) {
b86b493e	74	u32 ckscr = readl(cpg->reg + CPG_CKSCR);
596bdcf7 UH	75
	76	switch ((ckscr >> 28) & 3) {
	77	case 0: /* extal1 */
	78	parent_name = of_clk_get_parent_name(np, 0);
	79	break;
	80	case 1: /* extal1 / 2 */
	81	parent_name = of_clk_get_parent_name(np, 0);
	82	div = 2;
	83	break;
	84	case 2: /* extal2 */
	85	parent_name = of_clk_get_parent_name(np, 1);
	86	break;
	87	case 3: /* extal2 / 2 */
	88	parent_name = of_clk_get_parent_name(np, 1);
	89	div = 2;
	90	break;
	91	}
	92	} else if (!strcmp(name, "pll0")) {
	93	/* PLL0/1 are configurable multiplier clocks. Register them as
	94	* fixed factor clocks for now as there's no generic multiplier
	95	* clock implementation and we currently have no need to change
	96	* the multiplier value.
	97	*/
b86b493e	98	u32 value = readl(cpg->reg + CPG_PLL0CR);
596bdcf7 UH	99
	100	parent_name = "main";
	101	mult = ((value >> 24) & 0x7f) + 1;
	102	if (value & BIT(20))
	103	div = 2;
	104	} else if (!strcmp(name, "pll1")) {
b86b493e	105	u32 value = readl(cpg->reg + CPG_PLL1CR);
596bdcf7 UH	106
	107	parent_name = "main";
	108	/* XXX: enable bit? */
	109	mult = ((value >> 24) & 0x7f) + 1;
	110	if (value & BIT(7))
	111	div = 2;
	112	} else if (!strncmp(name, "pll2", 4)) {
	113	u32 value, cr;
	114
	115	switch (name[4]) {
	116	case 0:
	117	cr = CPG_PLL2CR;
	118	break;
	119	case 's':
	120	cr = CPG_PLL2SCR;
	121	break;
	122	case 'h':
	123	cr = CPG_PLL2HCR;
	124	break;
	125	default:
	126	return ERR_PTR(-EINVAL);
	127	}
b86b493e	128	value = readl(cpg->reg + cr);
596bdcf7 UH	129	switch ((value >> 5) & 7) {
	130	case 0:
	131	parent_name = "main";
	132	div = 2;
	133	break;
	134	case 1:
	135	parent_name = "extal2";
	136	div = 2;
	137	break;
	138	case 3:
	139	parent_name = "extal2";
	140	div = 4;
	141	break;
	142	case 4:
	143	parent_name = "main";
	144	break;
	145	case 5:
	146	parent_name = "extal2";
	147	break;
	148	default:
	149	pr_warn("%s: unexpected parent of %s\n", __func__,
	150	name);
	151	return ERR_PTR(-EINVAL);
	152	}
	153	/* XXX: enable bit? */
	154	mult = ((value >> 24) & 0x7f) + 1;
	155	} else if (!strcmp(name, "z") \|\| !strcmp(name, "z2")) {
	156	u32 shift = 8;
	157
	158	parent_name = "pll0";
	159	if (name[1] == '2') {
	160	div = 2;
	161	shift = 0;
	162	}
	163	div *= 32;
b86b493e	164	mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f);
596bdcf7 UH	165	} else {
	166	struct div4_clk *c;
	167
	168	for (c = div4_clks; c->name; c++) {
	169	if (!strcmp(name, c->name))
	170	break;
	171	}
	172	if (!c->name)
	173	return ERR_PTR(-EINVAL);
	174
	175	parent_name = "pll1";
	176	table = div4_div_table;
	177	reg = c->reg;
	178	shift = c->shift;
	179	}
	180
	181	if (!table) {
	182	return clk_register_fixed_factor(NULL, name, parent_name, 0,
	183	mult, div);
	184	} else {
	185	return clk_register_divider_table(NULL, name, parent_name, 0,
	186	cpg->reg + reg, shift, 4, 0,
	187	table, &cpg->lock);
	188	}
	189	}
	190
	191	static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
	192	{
	193	struct r8a73a4_cpg *cpg;
	194	struct clk **clks;
	195	unsigned int i;
	196	int num_clks;
	197
	198	num_clks = of_property_count_strings(np, "clock-output-names");
	199	if (num_clks < 0) {
	200	pr_err("%s: failed to count clocks\n", __func__);
	201	return;
	202	}
	203
	204	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
	205	clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
	206	if (cpg == NULL \|\| clks == NULL) {
	207	/* We're leaking memory on purpose, there's no point in cleaning
	208	* up as the system won't boot anyway.
	209	*/
	210	return;
	211	}
	212
	213	spin_lock_init(&cpg->lock);
	214
	215	cpg->data.clks = clks;
	216	cpg->data.clk_num = num_clks;
	217
	218	cpg->reg = of_iomap(np, 0);
	219	if (WARN_ON(cpg->reg == NULL))
	220	return;
	221
	222	for (i = 0; i < num_clks; ++i) {
	223	const char *name;
	224	struct clk *clk;
	225
	226	of_property_read_string_index(np, "clock-output-names", i,
	227	&name);
	228
229	clk = r8a73a4_cpg_register_clock(np, cpg, name);
230	if (IS_ERR(clk))
231	pr_err("%s: failed to register %s %s clock (%ld)\n",
232	__func__, np->name, name, PTR_ERR(clk));
233	else
234	cpg->data.clks[i] = clk;
235	}
236
237	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
238	}
239	CLK_OF_DECLARE(r8a73a4_cpg_clks, "renesas,r8a73a4-cpg-clocks",
240	r8a73a4_cpg_clocks_init);