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c2526597 SB |
1 | /*x |
2 | * Copyright (c) 2015, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/bitops.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_device.h> | |
21 | #include <linux/clk-provider.h> | |
22 | #include <linux/regmap.h> | |
23 | #include <linux/reset-controller.h> | |
24 | #include <linux/clk.h> | |
25 | ||
26 | #include <dt-bindings/clock/qcom,mmcc-msm8996.h> | |
27 | ||
28 | #include "common.h" | |
29 | #include "clk-regmap.h" | |
30 | #include "clk-regmap-divider.h" | |
31 | #include "clk-alpha-pll.h" | |
32 | #include "clk-rcg.h" | |
33 | #include "clk-branch.h" | |
34 | #include "reset.h" | |
7e824d50 | 35 | #include "gdsc.h" |
c2526597 SB |
36 | |
37 | #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } | |
38 | ||
39 | enum { | |
40 | P_XO, | |
41 | P_MMPLL0, | |
42 | P_GPLL0, | |
43 | P_GPLL0_DIV, | |
44 | P_MMPLL1, | |
45 | P_MMPLL9, | |
46 | P_MMPLL2, | |
47 | P_MMPLL8, | |
48 | P_MMPLL3, | |
49 | P_DSI0PLL, | |
50 | P_DSI1PLL, | |
51 | P_MMPLL5, | |
52 | P_HDMIPLL, | |
53 | P_DSI0PLL_BYTE, | |
54 | P_DSI1PLL_BYTE, | |
55 | P_MMPLL4, | |
56 | }; | |
57 | ||
58 | static const struct parent_map mmss_xo_hdmi_map[] = { | |
59 | { P_XO, 0 }, | |
60 | { P_HDMIPLL, 1 } | |
61 | }; | |
62 | ||
63 | static const char * const mmss_xo_hdmi[] = { | |
64 | "xo", | |
65 | "hdmipll" | |
66 | }; | |
67 | ||
68 | static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = { | |
69 | { P_XO, 0 }, | |
70 | { P_DSI0PLL, 1 }, | |
71 | { P_DSI1PLL, 2 } | |
72 | }; | |
73 | ||
74 | static const char * const mmss_xo_dsi0pll_dsi1pll[] = { | |
75 | "xo", | |
76 | "dsi0pll", | |
77 | "dsi1pll" | |
78 | }; | |
79 | ||
80 | static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { | |
81 | { P_XO, 0 }, | |
82 | { P_GPLL0, 5 }, | |
83 | { P_GPLL0_DIV, 6 } | |
84 | }; | |
85 | ||
86 | static const char * const mmss_xo_gpll0_gpll0_div[] = { | |
87 | "xo", | |
88 | "gpll0", | |
89 | "gpll0_div" | |
90 | }; | |
91 | ||
92 | static const struct parent_map mmss_xo_dsibyte_map[] = { | |
93 | { P_XO, 0 }, | |
94 | { P_DSI0PLL_BYTE, 1 }, | |
95 | { P_DSI1PLL_BYTE, 2 } | |
96 | }; | |
97 | ||
98 | static const char * const mmss_xo_dsibyte[] = { | |
99 | "xo", | |
100 | "dsi0pllbyte", | |
101 | "dsi1pllbyte" | |
102 | }; | |
103 | ||
104 | static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = { | |
105 | { P_XO, 0 }, | |
106 | { P_MMPLL0, 1 }, | |
107 | { P_GPLL0, 5 }, | |
108 | { P_GPLL0_DIV, 6 } | |
109 | }; | |
110 | ||
111 | static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = { | |
112 | "xo", | |
113 | "mmpll0", | |
114 | "gpll0", | |
115 | "gpll0_div" | |
116 | }; | |
117 | ||
118 | static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = { | |
119 | { P_XO, 0 }, | |
120 | { P_MMPLL0, 1 }, | |
121 | { P_MMPLL1, 2 }, | |
122 | { P_GPLL0, 5 }, | |
123 | { P_GPLL0_DIV, 6 } | |
124 | }; | |
125 | ||
126 | static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = { | |
127 | "xo", | |
128 | "mmpll0", | |
129 | "mmpll1", | |
130 | "gpll0", | |
131 | "gpll0_div" | |
132 | }; | |
133 | ||
134 | static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = { | |
135 | { P_XO, 0 }, | |
136 | { P_MMPLL0, 1 }, | |
137 | { P_MMPLL3, 3 }, | |
138 | { P_GPLL0, 5 }, | |
139 | { P_GPLL0_DIV, 6 } | |
140 | }; | |
141 | ||
142 | static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = { | |
143 | "xo", | |
144 | "mmpll0", | |
145 | "mmpll3", | |
146 | "gpll0", | |
147 | "gpll0_div" | |
148 | }; | |
149 | ||
150 | static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = { | |
151 | { P_XO, 0 }, | |
152 | { P_MMPLL0, 1 }, | |
153 | { P_MMPLL5, 2 }, | |
154 | { P_GPLL0, 5 }, | |
155 | { P_GPLL0_DIV, 6 } | |
156 | }; | |
157 | ||
158 | static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = { | |
159 | "xo", | |
160 | "mmpll0", | |
161 | "mmpll5", | |
162 | "gpll0", | |
163 | "gpll0_div" | |
164 | }; | |
165 | ||
166 | static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = { | |
167 | { P_XO, 0 }, | |
168 | { P_MMPLL0, 1 }, | |
169 | { P_MMPLL4, 3 }, | |
170 | { P_GPLL0, 5 }, | |
171 | { P_GPLL0_DIV, 6 } | |
172 | }; | |
173 | ||
174 | static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = { | |
175 | "xo", | |
176 | "mmpll0", | |
177 | "mmpll4", | |
178 | "gpll0", | |
179 | "gpll0_div" | |
180 | }; | |
181 | ||
182 | static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = { | |
183 | { P_XO, 0 }, | |
184 | { P_MMPLL0, 1 }, | |
185 | { P_MMPLL9, 2 }, | |
186 | { P_MMPLL2, 3 }, | |
187 | { P_MMPLL8, 4 }, | |
188 | { P_GPLL0, 5 } | |
189 | }; | |
190 | ||
191 | static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = { | |
192 | "xo", | |
193 | "mmpll0", | |
194 | "mmpll9", | |
195 | "mmpll2", | |
196 | "mmpll8", | |
197 | "gpll0" | |
198 | }; | |
199 | ||
200 | static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = { | |
201 | { P_XO, 0 }, | |
202 | { P_MMPLL0, 1 }, | |
203 | { P_MMPLL9, 2 }, | |
204 | { P_MMPLL2, 3 }, | |
205 | { P_MMPLL8, 4 }, | |
206 | { P_GPLL0, 5 }, | |
207 | { P_GPLL0_DIV, 6 } | |
208 | }; | |
209 | ||
210 | static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = { | |
211 | "xo", | |
212 | "mmpll0", | |
213 | "mmpll9", | |
214 | "mmpll2", | |
215 | "mmpll8", | |
216 | "gpll0", | |
217 | "gpll0_div" | |
218 | }; | |
219 | ||
220 | static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = { | |
221 | { P_XO, 0 }, | |
222 | { P_MMPLL0, 1 }, | |
223 | { P_MMPLL1, 2 }, | |
224 | { P_MMPLL4, 3 }, | |
225 | { P_MMPLL3, 4 }, | |
226 | { P_GPLL0, 5 }, | |
227 | { P_GPLL0_DIV, 6 } | |
228 | }; | |
229 | ||
230 | static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = { | |
231 | "xo", | |
232 | "mmpll0", | |
233 | "mmpll1", | |
234 | "mmpll4", | |
235 | "mmpll3", | |
236 | "gpll0", | |
237 | "gpll0_div" | |
238 | }; | |
239 | ||
240 | static struct clk_fixed_factor gpll0_div = { | |
241 | .mult = 1, | |
242 | .div = 2, | |
243 | .hw.init = &(struct clk_init_data){ | |
244 | .name = "gpll0_div", | |
245 | .parent_names = (const char *[]){ "gpll0" }, | |
246 | .num_parents = 1, | |
247 | .ops = &clk_fixed_factor_ops, | |
248 | }, | |
249 | }; | |
250 | ||
251 | static struct pll_vco mmpll_p_vco[] = { | |
252 | { 250000000, 500000000, 3 }, | |
253 | { 500000000, 1000000000, 2 }, | |
254 | { 1000000000, 1500000000, 1 }, | |
255 | { 1500000000, 2000000000, 0 }, | |
256 | }; | |
257 | ||
258 | static struct pll_vco mmpll_gfx_vco[] = { | |
259 | { 400000000, 1000000000, 2 }, | |
260 | { 1000000000, 1500000000, 1 }, | |
261 | { 1500000000, 2000000000, 0 }, | |
262 | }; | |
263 | ||
264 | static struct pll_vco mmpll_t_vco[] = { | |
265 | { 500000000, 1500000000, 0 }, | |
266 | }; | |
267 | ||
268 | static struct clk_alpha_pll mmpll0_early = { | |
269 | .offset = 0x0, | |
28d3f06e | 270 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
c2526597 SB |
271 | .vco_table = mmpll_p_vco, |
272 | .num_vco = ARRAY_SIZE(mmpll_p_vco), | |
273 | .clkr = { | |
274 | .enable_reg = 0x100, | |
275 | .enable_mask = BIT(0), | |
276 | .hw.init = &(struct clk_init_data){ | |
277 | .name = "mmpll0_early", | |
278 | .parent_names = (const char *[]){ "xo" }, | |
279 | .num_parents = 1, | |
280 | .ops = &clk_alpha_pll_ops, | |
281 | }, | |
282 | }, | |
283 | }; | |
284 | ||
285 | static struct clk_alpha_pll_postdiv mmpll0 = { | |
286 | .offset = 0x0, | |
28d3f06e | 287 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
c2526597 SB |
288 | .width = 4, |
289 | .clkr.hw.init = &(struct clk_init_data){ | |
290 | .name = "mmpll0", | |
291 | .parent_names = (const char *[]){ "mmpll0_early" }, | |
292 | .num_parents = 1, | |
293 | .ops = &clk_alpha_pll_postdiv_ops, | |
294 | .flags = CLK_SET_RATE_PARENT, | |
295 | }, | |
296 | }; | |
297 | ||
298 | static struct clk_alpha_pll mmpll1_early = { | |
299 | .offset = 0x30, | |
28d3f06e | 300 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
c2526597 SB |
301 | .vco_table = mmpll_p_vco, |
302 | .num_vco = ARRAY_SIZE(mmpll_p_vco), | |
303 | .clkr = { | |
304 | .enable_reg = 0x100, | |
305 | .enable_mask = BIT(1), | |
306 | .hw.init = &(struct clk_init_data){ | |
307 | .name = "mmpll1_early", | |
308 | .parent_names = (const char *[]){ "xo" }, | |
309 | .num_parents = 1, | |
310 | .ops = &clk_alpha_pll_ops, | |
311 | } | |
312 | }, | |
313 | }; | |
314 | ||
315 | static struct clk_alpha_pll_postdiv mmpll1 = { | |
316 | .offset = 0x30, | |
28d3f06e | 317 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
c2526597 SB |
318 | .width = 4, |
319 | .clkr.hw.init = &(struct clk_init_data){ | |
320 | .name = "mmpll1", | |
321 | .parent_names = (const char *[]){ "mmpll1_early" }, | |
322 | .num_parents = 1, | |
323 | .ops = &clk_alpha_pll_postdiv_ops, | |
324 | .flags = CLK_SET_RATE_PARENT, | |
325 | }, | |
326 | }; | |
327 | ||
328 | static struct clk_alpha_pll mmpll2_early = { | |
329 | .offset = 0x4100, | |
28d3f06e | 330 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
c2526597 SB |
331 | .vco_table = mmpll_gfx_vco, |
332 | .num_vco = ARRAY_SIZE(mmpll_gfx_vco), | |
333 | .clkr.hw.init = &(struct clk_init_data){ | |
334 | .name = "mmpll2_early", | |
335 | .parent_names = (const char *[]){ "xo" }, | |
336 | .num_parents = 1, | |
337 | .ops = &clk_alpha_pll_ops, | |
338 | }, | |
339 | }; | |
340 | ||
341 | static struct clk_alpha_pll_postdiv mmpll2 = { | |
342 | .offset = 0x4100, | |
28d3f06e | 343 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
c2526597 SB |
344 | .width = 4, |
345 | .clkr.hw.init = &(struct clk_init_data){ | |
346 | .name = "mmpll2", | |
347 | .parent_names = (const char *[]){ "mmpll2_early" }, | |
348 | .num_parents = 1, | |
349 | .ops = &clk_alpha_pll_postdiv_ops, | |
350 | .flags = CLK_SET_RATE_PARENT, | |
351 | }, | |
352 | }; | |
353 | ||
354 | static struct clk_alpha_pll mmpll3_early = { | |
355 | .offset = 0x60, | |
28d3f06e | 356 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
c2526597 SB |
357 | .vco_table = mmpll_p_vco, |
358 | .num_vco = ARRAY_SIZE(mmpll_p_vco), | |
359 | .clkr.hw.init = &(struct clk_init_data){ | |
360 | .name = "mmpll3_early", | |
361 | .parent_names = (const char *[]){ "xo" }, | |
362 | .num_parents = 1, | |
363 | .ops = &clk_alpha_pll_ops, | |
364 | }, | |
365 | }; | |
366 | ||
367 | static struct clk_alpha_pll_postdiv mmpll3 = { | |
368 | .offset = 0x60, | |
28d3f06e | 369 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
c2526597 SB |
370 | .width = 4, |
371 | .clkr.hw.init = &(struct clk_init_data){ | |
372 | .name = "mmpll3", | |
373 | .parent_names = (const char *[]){ "mmpll3_early" }, | |
374 | .num_parents = 1, | |
375 | .ops = &clk_alpha_pll_postdiv_ops, | |
376 | .flags = CLK_SET_RATE_PARENT, | |
377 | }, | |
378 | }; | |
379 | ||
380 | static struct clk_alpha_pll mmpll4_early = { | |
381 | .offset = 0x90, | |
28d3f06e | 382 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
c2526597 SB |
383 | .vco_table = mmpll_t_vco, |
384 | .num_vco = ARRAY_SIZE(mmpll_t_vco), | |
385 | .clkr.hw.init = &(struct clk_init_data){ | |
386 | .name = "mmpll4_early", | |
387 | .parent_names = (const char *[]){ "xo" }, | |
388 | .num_parents = 1, | |
389 | .ops = &clk_alpha_pll_ops, | |
390 | }, | |
391 | }; | |
392 | ||
393 | static struct clk_alpha_pll_postdiv mmpll4 = { | |
394 | .offset = 0x90, | |
28d3f06e | 395 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
c2526597 SB |
396 | .width = 2, |
397 | .clkr.hw.init = &(struct clk_init_data){ | |
398 | .name = "mmpll4", | |
399 | .parent_names = (const char *[]){ "mmpll4_early" }, | |
400 | .num_parents = 1, | |
401 | .ops = &clk_alpha_pll_postdiv_ops, | |
402 | .flags = CLK_SET_RATE_PARENT, | |
403 | }, | |
404 | }; | |
405 | ||
406 | static struct clk_alpha_pll mmpll5_early = { | |
407 | .offset = 0xc0, | |
28d3f06e | 408 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
c2526597 SB |
409 | .vco_table = mmpll_p_vco, |
410 | .num_vco = ARRAY_SIZE(mmpll_p_vco), | |
411 | .clkr.hw.init = &(struct clk_init_data){ | |
412 | .name = "mmpll5_early", | |
413 | .parent_names = (const char *[]){ "xo" }, | |
414 | .num_parents = 1, | |
415 | .ops = &clk_alpha_pll_ops, | |
416 | }, | |
417 | }; | |
418 | ||
419 | static struct clk_alpha_pll_postdiv mmpll5 = { | |
420 | .offset = 0xc0, | |
28d3f06e | 421 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
c2526597 SB |
422 | .width = 4, |
423 | .clkr.hw.init = &(struct clk_init_data){ | |
424 | .name = "mmpll5", | |
425 | .parent_names = (const char *[]){ "mmpll5_early" }, | |
426 | .num_parents = 1, | |
427 | .ops = &clk_alpha_pll_postdiv_ops, | |
428 | .flags = CLK_SET_RATE_PARENT, | |
429 | }, | |
430 | }; | |
431 | ||
432 | static struct clk_alpha_pll mmpll8_early = { | |
433 | .offset = 0x4130, | |
28d3f06e | 434 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
c2526597 SB |
435 | .vco_table = mmpll_gfx_vco, |
436 | .num_vco = ARRAY_SIZE(mmpll_gfx_vco), | |
437 | .clkr.hw.init = &(struct clk_init_data){ | |
438 | .name = "mmpll8_early", | |
439 | .parent_names = (const char *[]){ "xo" }, | |
440 | .num_parents = 1, | |
441 | .ops = &clk_alpha_pll_ops, | |
442 | }, | |
443 | }; | |
444 | ||
445 | static struct clk_alpha_pll_postdiv mmpll8 = { | |
446 | .offset = 0x4130, | |
28d3f06e | 447 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
c2526597 SB |
448 | .width = 4, |
449 | .clkr.hw.init = &(struct clk_init_data){ | |
450 | .name = "mmpll8", | |
451 | .parent_names = (const char *[]){ "mmpll8_early" }, | |
452 | .num_parents = 1, | |
453 | .ops = &clk_alpha_pll_postdiv_ops, | |
454 | .flags = CLK_SET_RATE_PARENT, | |
455 | }, | |
456 | }; | |
457 | ||
458 | static struct clk_alpha_pll mmpll9_early = { | |
459 | .offset = 0x4200, | |
28d3f06e | 460 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
c2526597 SB |
461 | .vco_table = mmpll_t_vco, |
462 | .num_vco = ARRAY_SIZE(mmpll_t_vco), | |
463 | .clkr.hw.init = &(struct clk_init_data){ | |
464 | .name = "mmpll9_early", | |
465 | .parent_names = (const char *[]){ "xo" }, | |
466 | .num_parents = 1, | |
467 | .ops = &clk_alpha_pll_ops, | |
468 | }, | |
469 | }; | |
470 | ||
471 | static struct clk_alpha_pll_postdiv mmpll9 = { | |
472 | .offset = 0x4200, | |
28d3f06e | 473 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
c2526597 SB |
474 | .width = 2, |
475 | .clkr.hw.init = &(struct clk_init_data){ | |
476 | .name = "mmpll9", | |
477 | .parent_names = (const char *[]){ "mmpll9_early" }, | |
478 | .num_parents = 1, | |
479 | .ops = &clk_alpha_pll_postdiv_ops, | |
480 | .flags = CLK_SET_RATE_PARENT, | |
481 | }, | |
482 | }; | |
483 | ||
484 | static const struct freq_tbl ftbl_ahb_clk_src[] = { | |
485 | F(19200000, P_XO, 1, 0, 0), | |
486 | F(40000000, P_GPLL0_DIV, 7.5, 0, 0), | |
487 | F(80000000, P_MMPLL0, 10, 0, 0), | |
488 | { } | |
489 | }; | |
490 | ||
491 | static struct clk_rcg2 ahb_clk_src = { | |
492 | .cmd_rcgr = 0x5000, | |
493 | .hid_width = 5, | |
494 | .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, | |
495 | .freq_tbl = ftbl_ahb_clk_src, | |
496 | .clkr.hw.init = &(struct clk_init_data){ | |
497 | .name = "ahb_clk_src", | |
498 | .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, | |
499 | .num_parents = 4, | |
500 | .ops = &clk_rcg2_ops, | |
501 | }, | |
502 | }; | |
503 | ||
504 | static const struct freq_tbl ftbl_axi_clk_src[] = { | |
505 | F(19200000, P_XO, 1, 0, 0), | |
506 | F(75000000, P_GPLL0_DIV, 4, 0, 0), | |
507 | F(100000000, P_GPLL0, 6, 0, 0), | |
508 | F(171430000, P_GPLL0, 3.5, 0, 0), | |
509 | F(200000000, P_GPLL0, 3, 0, 0), | |
510 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
511 | F(400000000, P_MMPLL0, 2, 0, 0), | |
512 | { } | |
513 | }; | |
514 | ||
515 | static struct clk_rcg2 axi_clk_src = { | |
516 | .cmd_rcgr = 0x5040, | |
517 | .hid_width = 5, | |
518 | .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, | |
519 | .freq_tbl = ftbl_axi_clk_src, | |
520 | .clkr.hw.init = &(struct clk_init_data){ | |
521 | .name = "axi_clk_src", | |
522 | .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, | |
523 | .num_parents = 5, | |
524 | .ops = &clk_rcg2_ops, | |
525 | }, | |
526 | }; | |
527 | ||
528 | static struct clk_rcg2 maxi_clk_src = { | |
529 | .cmd_rcgr = 0x5090, | |
530 | .hid_width = 5, | |
531 | .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, | |
532 | .freq_tbl = ftbl_axi_clk_src, | |
533 | .clkr.hw.init = &(struct clk_init_data){ | |
534 | .name = "maxi_clk_src", | |
535 | .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, | |
536 | .num_parents = 5, | |
537 | .ops = &clk_rcg2_ops, | |
538 | }, | |
539 | }; | |
540 | ||
541 | static struct clk_rcg2 gfx3d_clk_src = { | |
542 | .cmd_rcgr = 0x4000, | |
543 | .hid_width = 5, | |
544 | .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map, | |
545 | .clkr.hw.init = &(struct clk_init_data){ | |
546 | .name = "gfx3d_clk_src", | |
547 | .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0, | |
548 | .num_parents = 6, | |
549 | .ops = &clk_gfx3d_ops, | |
550 | .flags = CLK_SET_RATE_PARENT, | |
551 | }, | |
552 | }; | |
553 | ||
554 | static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = { | |
555 | F(19200000, P_XO, 1, 0, 0), | |
556 | { } | |
557 | }; | |
558 | ||
559 | static struct clk_rcg2 rbbmtimer_clk_src = { | |
560 | .cmd_rcgr = 0x4090, | |
561 | .hid_width = 5, | |
562 | .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, | |
563 | .freq_tbl = ftbl_rbbmtimer_clk_src, | |
564 | .clkr.hw.init = &(struct clk_init_data){ | |
565 | .name = "rbbmtimer_clk_src", | |
566 | .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, | |
567 | .num_parents = 4, | |
568 | .ops = &clk_rcg2_ops, | |
569 | }, | |
570 | }; | |
571 | ||
572 | static struct clk_rcg2 isense_clk_src = { | |
573 | .cmd_rcgr = 0x4010, | |
574 | .hid_width = 5, | |
575 | .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map, | |
576 | .clkr.hw.init = &(struct clk_init_data){ | |
577 | .name = "isense_clk_src", | |
578 | .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div, | |
579 | .num_parents = 7, | |
580 | .ops = &clk_rcg2_ops, | |
581 | }, | |
582 | }; | |
583 | ||
584 | static const struct freq_tbl ftbl_rbcpr_clk_src[] = { | |
585 | F(19200000, P_XO, 1, 0, 0), | |
586 | F(50000000, P_GPLL0, 12, 0, 0), | |
587 | { } | |
588 | }; | |
589 | ||
590 | static struct clk_rcg2 rbcpr_clk_src = { | |
591 | .cmd_rcgr = 0x4060, | |
592 | .hid_width = 5, | |
593 | .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, | |
594 | .freq_tbl = ftbl_rbcpr_clk_src, | |
595 | .clkr.hw.init = &(struct clk_init_data){ | |
596 | .name = "rbcpr_clk_src", | |
597 | .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, | |
598 | .num_parents = 4, | |
599 | .ops = &clk_rcg2_ops, | |
600 | }, | |
601 | }; | |
602 | ||
603 | static const struct freq_tbl ftbl_video_core_clk_src[] = { | |
604 | F(75000000, P_GPLL0_DIV, 4, 0, 0), | |
605 | F(150000000, P_GPLL0, 4, 0, 0), | |
606 | F(346666667, P_MMPLL3, 3, 0, 0), | |
607 | F(520000000, P_MMPLL3, 2, 0, 0), | |
608 | { } | |
609 | }; | |
610 | ||
611 | static struct clk_rcg2 video_core_clk_src = { | |
612 | .cmd_rcgr = 0x1000, | |
613 | .mnd_width = 8, | |
614 | .hid_width = 5, | |
615 | .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, | |
616 | .freq_tbl = ftbl_video_core_clk_src, | |
617 | .clkr.hw.init = &(struct clk_init_data){ | |
618 | .name = "video_core_clk_src", | |
619 | .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, | |
620 | .num_parents = 5, | |
621 | .ops = &clk_rcg2_ops, | |
622 | }, | |
623 | }; | |
624 | ||
625 | static struct clk_rcg2 video_subcore0_clk_src = { | |
626 | .cmd_rcgr = 0x1060, | |
627 | .mnd_width = 8, | |
628 | .hid_width = 5, | |
629 | .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, | |
630 | .freq_tbl = ftbl_video_core_clk_src, | |
631 | .clkr.hw.init = &(struct clk_init_data){ | |
632 | .name = "video_subcore0_clk_src", | |
633 | .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, | |
634 | .num_parents = 5, | |
635 | .ops = &clk_rcg2_ops, | |
636 | }, | |
637 | }; | |
638 | ||
639 | static struct clk_rcg2 video_subcore1_clk_src = { | |
640 | .cmd_rcgr = 0x1080, | |
641 | .mnd_width = 8, | |
642 | .hid_width = 5, | |
643 | .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, | |
644 | .freq_tbl = ftbl_video_core_clk_src, | |
645 | .clkr.hw.init = &(struct clk_init_data){ | |
646 | .name = "video_subcore1_clk_src", | |
647 | .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, | |
648 | .num_parents = 5, | |
649 | .ops = &clk_rcg2_ops, | |
650 | }, | |
651 | }; | |
652 | ||
653 | static struct clk_rcg2 pclk0_clk_src = { | |
654 | .cmd_rcgr = 0x2000, | |
655 | .mnd_width = 8, | |
656 | .hid_width = 5, | |
657 | .parent_map = mmss_xo_dsi0pll_dsi1pll_map, | |
658 | .clkr.hw.init = &(struct clk_init_data){ | |
659 | .name = "pclk0_clk_src", | |
660 | .parent_names = mmss_xo_dsi0pll_dsi1pll, | |
661 | .num_parents = 3, | |
662 | .ops = &clk_pixel_ops, | |
663 | .flags = CLK_SET_RATE_PARENT, | |
664 | }, | |
665 | }; | |
666 | ||
667 | static struct clk_rcg2 pclk1_clk_src = { | |
668 | .cmd_rcgr = 0x2020, | |
669 | .mnd_width = 8, | |
670 | .hid_width = 5, | |
671 | .parent_map = mmss_xo_dsi0pll_dsi1pll_map, | |
672 | .clkr.hw.init = &(struct clk_init_data){ | |
673 | .name = "pclk1_clk_src", | |
674 | .parent_names = mmss_xo_dsi0pll_dsi1pll, | |
675 | .num_parents = 3, | |
676 | .ops = &clk_pixel_ops, | |
677 | .flags = CLK_SET_RATE_PARENT, | |
678 | }, | |
679 | }; | |
680 | ||
681 | static const struct freq_tbl ftbl_mdp_clk_src[] = { | |
682 | F(85714286, P_GPLL0, 7, 0, 0), | |
683 | F(100000000, P_GPLL0, 6, 0, 0), | |
684 | F(150000000, P_GPLL0, 4, 0, 0), | |
685 | F(171428571, P_GPLL0, 3.5, 0, 0), | |
686 | F(200000000, P_GPLL0, 3, 0, 0), | |
687 | F(275000000, P_MMPLL5, 3, 0, 0), | |
688 | F(300000000, P_GPLL0, 2, 0, 0), | |
689 | F(330000000, P_MMPLL5, 2.5, 0, 0), | |
690 | F(412500000, P_MMPLL5, 2, 0, 0), | |
691 | { } | |
692 | }; | |
693 | ||
694 | static struct clk_rcg2 mdp_clk_src = { | |
695 | .cmd_rcgr = 0x2040, | |
696 | .hid_width = 5, | |
697 | .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map, | |
698 | .freq_tbl = ftbl_mdp_clk_src, | |
699 | .clkr.hw.init = &(struct clk_init_data){ | |
700 | .name = "mdp_clk_src", | |
701 | .parent_names = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div, | |
702 | .num_parents = 5, | |
703 | .ops = &clk_rcg2_ops, | |
704 | }, | |
705 | }; | |
706 | ||
707 | static struct freq_tbl extpclk_freq_tbl[] = { | |
708 | { .src = P_HDMIPLL }, | |
709 | { } | |
710 | }; | |
711 | ||
712 | static struct clk_rcg2 extpclk_clk_src = { | |
713 | .cmd_rcgr = 0x2060, | |
714 | .hid_width = 5, | |
715 | .parent_map = mmss_xo_hdmi_map, | |
716 | .freq_tbl = extpclk_freq_tbl, | |
717 | .clkr.hw.init = &(struct clk_init_data){ | |
718 | .name = "extpclk_clk_src", | |
719 | .parent_names = mmss_xo_hdmi, | |
720 | .num_parents = 2, | |
721 | .ops = &clk_byte_ops, | |
722 | .flags = CLK_SET_RATE_PARENT, | |
723 | }, | |
724 | }; | |
725 | ||
726 | static struct freq_tbl ftbl_mdss_vsync_clk[] = { | |
727 | F(19200000, P_XO, 1, 0, 0), | |
728 | { } | |
729 | }; | |
730 | ||
731 | static struct clk_rcg2 vsync_clk_src = { | |
732 | .cmd_rcgr = 0x2080, | |
733 | .hid_width = 5, | |
734 | .parent_map = mmss_xo_gpll0_gpll0_div_map, | |
735 | .freq_tbl = ftbl_mdss_vsync_clk, | |
736 | .clkr.hw.init = &(struct clk_init_data){ | |
737 | .name = "vsync_clk_src", | |
738 | .parent_names = mmss_xo_gpll0_gpll0_div, | |
739 | .num_parents = 3, | |
740 | .ops = &clk_rcg2_ops, | |
741 | }, | |
742 | }; | |
743 | ||
744 | static struct freq_tbl ftbl_mdss_hdmi_clk[] = { | |
745 | F(19200000, P_XO, 1, 0, 0), | |
746 | { } | |
747 | }; | |
748 | ||
749 | static struct clk_rcg2 hdmi_clk_src = { | |
750 | .cmd_rcgr = 0x2100, | |
751 | .hid_width = 5, | |
752 | .parent_map = mmss_xo_gpll0_gpll0_div_map, | |
753 | .freq_tbl = ftbl_mdss_hdmi_clk, | |
754 | .clkr.hw.init = &(struct clk_init_data){ | |
755 | .name = "hdmi_clk_src", | |
756 | .parent_names = mmss_xo_gpll0_gpll0_div, | |
757 | .num_parents = 3, | |
758 | .ops = &clk_rcg2_ops, | |
759 | }, | |
760 | }; | |
761 | ||
762 | static struct clk_rcg2 byte0_clk_src = { | |
763 | .cmd_rcgr = 0x2120, | |
764 | .hid_width = 5, | |
765 | .parent_map = mmss_xo_dsibyte_map, | |
766 | .clkr.hw.init = &(struct clk_init_data){ | |
767 | .name = "byte0_clk_src", | |
768 | .parent_names = mmss_xo_dsibyte, | |
769 | .num_parents = 3, | |
770 | .ops = &clk_byte2_ops, | |
771 | .flags = CLK_SET_RATE_PARENT, | |
772 | }, | |
773 | }; | |
774 | ||
775 | static struct clk_rcg2 byte1_clk_src = { | |
776 | .cmd_rcgr = 0x2140, | |
777 | .hid_width = 5, | |
778 | .parent_map = mmss_xo_dsibyte_map, | |
779 | .clkr.hw.init = &(struct clk_init_data){ | |
780 | .name = "byte1_clk_src", | |
781 | .parent_names = mmss_xo_dsibyte, | |
782 | .num_parents = 3, | |
783 | .ops = &clk_byte2_ops, | |
784 | .flags = CLK_SET_RATE_PARENT, | |
785 | }, | |
786 | }; | |
787 | ||
788 | static struct freq_tbl ftbl_mdss_esc0_1_clk[] = { | |
789 | F(19200000, P_XO, 1, 0, 0), | |
790 | { } | |
791 | }; | |
792 | ||
793 | static struct clk_rcg2 esc0_clk_src = { | |
794 | .cmd_rcgr = 0x2160, | |
795 | .hid_width = 5, | |
796 | .parent_map = mmss_xo_dsibyte_map, | |
797 | .freq_tbl = ftbl_mdss_esc0_1_clk, | |
798 | .clkr.hw.init = &(struct clk_init_data){ | |
799 | .name = "esc0_clk_src", | |
800 | .parent_names = mmss_xo_dsibyte, | |
801 | .num_parents = 3, | |
802 | .ops = &clk_rcg2_ops, | |
803 | }, | |
804 | }; | |
805 | ||
806 | static struct clk_rcg2 esc1_clk_src = { | |
807 | .cmd_rcgr = 0x2180, | |
808 | .hid_width = 5, | |
809 | .parent_map = mmss_xo_dsibyte_map, | |
810 | .freq_tbl = ftbl_mdss_esc0_1_clk, | |
811 | .clkr.hw.init = &(struct clk_init_data){ | |
812 | .name = "esc1_clk_src", | |
813 | .parent_names = mmss_xo_dsibyte, | |
814 | .num_parents = 3, | |
815 | .ops = &clk_rcg2_ops, | |
816 | }, | |
817 | }; | |
818 | ||
819 | static const struct freq_tbl ftbl_camss_gp0_clk_src[] = { | |
820 | F(10000, P_XO, 16, 1, 120), | |
821 | F(24000, P_XO, 16, 1, 50), | |
822 | F(6000000, P_GPLL0_DIV, 10, 1, 5), | |
823 | F(12000000, P_GPLL0_DIV, 1, 1, 25), | |
824 | F(13000000, P_GPLL0_DIV, 2, 13, 150), | |
825 | F(24000000, P_GPLL0_DIV, 1, 2, 25), | |
826 | { } | |
827 | }; | |
828 | ||
829 | static struct clk_rcg2 camss_gp0_clk_src = { | |
830 | .cmd_rcgr = 0x3420, | |
831 | .mnd_width = 8, | |
832 | .hid_width = 5, | |
833 | .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, | |
834 | .freq_tbl = ftbl_camss_gp0_clk_src, | |
835 | .clkr.hw.init = &(struct clk_init_data){ | |
836 | .name = "camss_gp0_clk_src", | |
837 | .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, | |
838 | .num_parents = 5, | |
839 | .ops = &clk_rcg2_ops, | |
840 | }, | |
841 | }; | |
842 | ||
843 | static struct clk_rcg2 camss_gp1_clk_src = { | |
844 | .cmd_rcgr = 0x3450, | |
845 | .mnd_width = 8, | |
846 | .hid_width = 5, | |
847 | .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, | |
848 | .freq_tbl = ftbl_camss_gp0_clk_src, | |
849 | .clkr.hw.init = &(struct clk_init_data){ | |
850 | .name = "camss_gp1_clk_src", | |
851 | .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, | |
852 | .num_parents = 5, | |
853 | .ops = &clk_rcg2_ops, | |
854 | }, | |
855 | }; | |
856 | ||
857 | static const struct freq_tbl ftbl_mclk0_clk_src[] = { | |
858 | F(4800000, P_XO, 4, 0, 0), | |
859 | F(6000000, P_GPLL0_DIV, 10, 1, 5), | |
860 | F(8000000, P_GPLL0_DIV, 1, 2, 75), | |
861 | F(9600000, P_XO, 2, 0, 0), | |
862 | F(16666667, P_GPLL0_DIV, 2, 1, 9), | |
863 | F(19200000, P_XO, 1, 0, 0), | |
864 | F(24000000, P_GPLL0_DIV, 1, 2, 25), | |
865 | F(33333333, P_GPLL0_DIV, 1, 1, 9), | |
866 | F(48000000, P_GPLL0, 1, 2, 25), | |
867 | F(66666667, P_GPLL0, 1, 1, 9), | |
868 | { } | |
869 | }; | |
870 | ||
871 | static struct clk_rcg2 mclk0_clk_src = { | |
872 | .cmd_rcgr = 0x3360, | |
873 | .mnd_width = 8, | |
874 | .hid_width = 5, | |
875 | .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, | |
876 | .freq_tbl = ftbl_mclk0_clk_src, | |
877 | .clkr.hw.init = &(struct clk_init_data){ | |
878 | .name = "mclk0_clk_src", | |
879 | .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, | |
880 | .num_parents = 5, | |
881 | .ops = &clk_rcg2_ops, | |
882 | }, | |
883 | }; | |
884 | ||
885 | static struct clk_rcg2 mclk1_clk_src = { | |
886 | .cmd_rcgr = 0x3390, | |
887 | .mnd_width = 8, | |
888 | .hid_width = 5, | |
889 | .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, | |
890 | .freq_tbl = ftbl_mclk0_clk_src, | |
891 | .clkr.hw.init = &(struct clk_init_data){ | |
892 | .name = "mclk1_clk_src", | |
893 | .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, | |
894 | .num_parents = 5, | |
895 | .ops = &clk_rcg2_ops, | |
896 | }, | |
897 | }; | |
898 | ||
899 | static struct clk_rcg2 mclk2_clk_src = { | |
900 | .cmd_rcgr = 0x33c0, | |
901 | .mnd_width = 8, | |
902 | .hid_width = 5, | |
903 | .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, | |
904 | .freq_tbl = ftbl_mclk0_clk_src, | |
905 | .clkr.hw.init = &(struct clk_init_data){ | |
906 | .name = "mclk2_clk_src", | |
907 | .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, | |
908 | .num_parents = 5, | |
909 | .ops = &clk_rcg2_ops, | |
910 | }, | |
911 | }; | |
912 | ||
913 | static struct clk_rcg2 mclk3_clk_src = { | |
914 | .cmd_rcgr = 0x33f0, | |
915 | .mnd_width = 8, | |
916 | .hid_width = 5, | |
917 | .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, | |
918 | .freq_tbl = ftbl_mclk0_clk_src, | |
919 | .clkr.hw.init = &(struct clk_init_data){ | |
920 | .name = "mclk3_clk_src", | |
921 | .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, | |
922 | .num_parents = 5, | |
923 | .ops = &clk_rcg2_ops, | |
924 | }, | |
925 | }; | |
926 | ||
927 | static const struct freq_tbl ftbl_cci_clk_src[] = { | |
928 | F(19200000, P_XO, 1, 0, 0), | |
929 | F(37500000, P_GPLL0, 16, 0, 0), | |
930 | F(50000000, P_GPLL0, 12, 0, 0), | |
931 | F(100000000, P_GPLL0, 6, 0, 0), | |
932 | { } | |
933 | }; | |
934 | ||
935 | static struct clk_rcg2 cci_clk_src = { | |
936 | .cmd_rcgr = 0x3300, | |
937 | .mnd_width = 8, | |
938 | .hid_width = 5, | |
939 | .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, | |
940 | .freq_tbl = ftbl_cci_clk_src, | |
941 | .clkr.hw.init = &(struct clk_init_data){ | |
942 | .name = "cci_clk_src", | |
943 | .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, | |
944 | .num_parents = 5, | |
945 | .ops = &clk_rcg2_ops, | |
946 | }, | |
947 | }; | |
948 | ||
949 | static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = { | |
950 | F(100000000, P_GPLL0_DIV, 3, 0, 0), | |
951 | F(200000000, P_GPLL0, 3, 0, 0), | |
952 | F(266666667, P_MMPLL0, 3, 0, 0), | |
953 | { } | |
954 | }; | |
955 | ||
956 | static struct clk_rcg2 csi0phytimer_clk_src = { | |
957 | .cmd_rcgr = 0x3000, | |
958 | .hid_width = 5, | |
959 | .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, | |
960 | .freq_tbl = ftbl_csi0phytimer_clk_src, | |
961 | .clkr.hw.init = &(struct clk_init_data){ | |
962 | .name = "csi0phytimer_clk_src", | |
963 | .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, | |
964 | .num_parents = 7, | |
965 | .ops = &clk_rcg2_ops, | |
966 | }, | |
967 | }; | |
968 | ||
969 | static struct clk_rcg2 csi1phytimer_clk_src = { | |
970 | .cmd_rcgr = 0x3030, | |
971 | .hid_width = 5, | |
972 | .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, | |
973 | .freq_tbl = ftbl_csi0phytimer_clk_src, | |
974 | .clkr.hw.init = &(struct clk_init_data){ | |
975 | .name = "csi1phytimer_clk_src", | |
976 | .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, | |
977 | .num_parents = 7, | |
978 | .ops = &clk_rcg2_ops, | |
979 | }, | |
980 | }; | |
981 | ||
982 | static struct clk_rcg2 csi2phytimer_clk_src = { | |
983 | .cmd_rcgr = 0x3060, | |
984 | .hid_width = 5, | |
985 | .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, | |
986 | .freq_tbl = ftbl_csi0phytimer_clk_src, | |
987 | .clkr.hw.init = &(struct clk_init_data){ | |
988 | .name = "csi2phytimer_clk_src", | |
989 | .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, | |
990 | .num_parents = 7, | |
991 | .ops = &clk_rcg2_ops, | |
992 | }, | |
993 | }; | |
994 | ||
995 | static const struct freq_tbl ftbl_csiphy0_3p_clk_src[] = { | |
996 | F(100000000, P_GPLL0_DIV, 3, 0, 0), | |
997 | F(200000000, P_GPLL0, 3, 0, 0), | |
998 | F(320000000, P_MMPLL4, 3, 0, 0), | |
999 | F(384000000, P_MMPLL4, 2.5, 0, 0), | |
1000 | { } | |
1001 | }; | |
1002 | ||
1003 | static struct clk_rcg2 csiphy0_3p_clk_src = { | |
1004 | .cmd_rcgr = 0x3240, | |
1005 | .hid_width = 5, | |
1006 | .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, | |
1007 | .freq_tbl = ftbl_csiphy0_3p_clk_src, | |
1008 | .clkr.hw.init = &(struct clk_init_data){ | |
1009 | .name = "csiphy0_3p_clk_src", | |
1010 | .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, | |
1011 | .num_parents = 7, | |
1012 | .ops = &clk_rcg2_ops, | |
1013 | }, | |
1014 | }; | |
1015 | ||
1016 | static struct clk_rcg2 csiphy1_3p_clk_src = { | |
1017 | .cmd_rcgr = 0x3260, | |
1018 | .hid_width = 5, | |
1019 | .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, | |
1020 | .freq_tbl = ftbl_csiphy0_3p_clk_src, | |
1021 | .clkr.hw.init = &(struct clk_init_data){ | |
1022 | .name = "csiphy1_3p_clk_src", | |
1023 | .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, | |
1024 | .num_parents = 7, | |
1025 | .ops = &clk_rcg2_ops, | |
1026 | }, | |
1027 | }; | |
1028 | ||
1029 | static struct clk_rcg2 csiphy2_3p_clk_src = { | |
1030 | .cmd_rcgr = 0x3280, | |
1031 | .hid_width = 5, | |
1032 | .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, | |
1033 | .freq_tbl = ftbl_csiphy0_3p_clk_src, | |
1034 | .clkr.hw.init = &(struct clk_init_data){ | |
1035 | .name = "csiphy2_3p_clk_src", | |
1036 | .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, | |
1037 | .num_parents = 7, | |
1038 | .ops = &clk_rcg2_ops, | |
1039 | }, | |
1040 | }; | |
1041 | ||
1042 | static const struct freq_tbl ftbl_jpeg0_clk_src[] = { | |
1043 | F(75000000, P_GPLL0_DIV, 4, 0, 0), | |
1044 | F(150000000, P_GPLL0, 4, 0, 0), | |
1045 | F(228571429, P_MMPLL0, 3.5, 0, 0), | |
1046 | F(266666667, P_MMPLL0, 3, 0, 0), | |
1047 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
1048 | F(480000000, P_MMPLL4, 2, 0, 0), | |
1049 | { } | |
1050 | }; | |
1051 | ||
1052 | static struct clk_rcg2 jpeg0_clk_src = { | |
1053 | .cmd_rcgr = 0x3500, | |
1054 | .hid_width = 5, | |
1055 | .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, | |
1056 | .freq_tbl = ftbl_jpeg0_clk_src, | |
1057 | .clkr.hw.init = &(struct clk_init_data){ | |
1058 | .name = "jpeg0_clk_src", | |
1059 | .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, | |
1060 | .num_parents = 7, | |
1061 | .ops = &clk_rcg2_ops, | |
1062 | }, | |
1063 | }; | |
1064 | ||
1065 | static const struct freq_tbl ftbl_jpeg2_clk_src[] = { | |
1066 | F(75000000, P_GPLL0_DIV, 4, 0, 0), | |
1067 | F(150000000, P_GPLL0, 4, 0, 0), | |
1068 | F(228571429, P_MMPLL0, 3.5, 0, 0), | |
1069 | F(266666667, P_MMPLL0, 3, 0, 0), | |
1070 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
1071 | { } | |
1072 | }; | |
1073 | ||
1074 | static struct clk_rcg2 jpeg2_clk_src = { | |
1075 | .cmd_rcgr = 0x3540, | |
1076 | .hid_width = 5, | |
1077 | .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, | |
1078 | .freq_tbl = ftbl_jpeg2_clk_src, | |
1079 | .clkr.hw.init = &(struct clk_init_data){ | |
1080 | .name = "jpeg2_clk_src", | |
1081 | .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, | |
1082 | .num_parents = 7, | |
1083 | .ops = &clk_rcg2_ops, | |
1084 | }, | |
1085 | }; | |
1086 | ||
1087 | static struct clk_rcg2 jpeg_dma_clk_src = { | |
1088 | .cmd_rcgr = 0x3560, | |
1089 | .hid_width = 5, | |
1090 | .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, | |
1091 | .freq_tbl = ftbl_jpeg0_clk_src, | |
1092 | .clkr.hw.init = &(struct clk_init_data){ | |
1093 | .name = "jpeg_dma_clk_src", | |
1094 | .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, | |
1095 | .num_parents = 7, | |
1096 | .ops = &clk_rcg2_ops, | |
1097 | }, | |
1098 | }; | |
1099 | ||
1100 | static const struct freq_tbl ftbl_vfe0_clk_src[] = { | |
1101 | F(75000000, P_GPLL0_DIV, 4, 0, 0), | |
1102 | F(100000000, P_GPLL0_DIV, 3, 0, 0), | |
1103 | F(300000000, P_GPLL0, 2, 0, 0), | |
1104 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
1105 | F(480000000, P_MMPLL4, 2, 0, 0), | |
1106 | F(600000000, P_GPLL0, 1, 0, 0), | |
1107 | { } | |
1108 | }; | |
1109 | ||
1110 | static struct clk_rcg2 vfe0_clk_src = { | |
1111 | .cmd_rcgr = 0x3600, | |
1112 | .hid_width = 5, | |
1113 | .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, | |
1114 | .freq_tbl = ftbl_vfe0_clk_src, | |
1115 | .clkr.hw.init = &(struct clk_init_data){ | |
1116 | .name = "vfe0_clk_src", | |
1117 | .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, | |
1118 | .num_parents = 7, | |
1119 | .ops = &clk_rcg2_ops, | |
1120 | }, | |
1121 | }; | |
1122 | ||
1123 | static struct clk_rcg2 vfe1_clk_src = { | |
1124 | .cmd_rcgr = 0x3620, | |
1125 | .hid_width = 5, | |
1126 | .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, | |
1127 | .freq_tbl = ftbl_vfe0_clk_src, | |
1128 | .clkr.hw.init = &(struct clk_init_data){ | |
1129 | .name = "vfe1_clk_src", | |
1130 | .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, | |
1131 | .num_parents = 7, | |
1132 | .ops = &clk_rcg2_ops, | |
1133 | }, | |
1134 | }; | |
1135 | ||
1136 | static const struct freq_tbl ftbl_cpp_clk_src[] = { | |
1137 | F(100000000, P_GPLL0_DIV, 3, 0, 0), | |
1138 | F(200000000, P_GPLL0, 3, 0, 0), | |
1139 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
1140 | F(480000000, P_MMPLL4, 2, 0, 0), | |
1141 | F(640000000, P_MMPLL4, 1.5, 0, 0), | |
1142 | { } | |
1143 | }; | |
1144 | ||
1145 | static struct clk_rcg2 cpp_clk_src = { | |
1146 | .cmd_rcgr = 0x3640, | |
1147 | .hid_width = 5, | |
1148 | .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, | |
1149 | .freq_tbl = ftbl_cpp_clk_src, | |
1150 | .clkr.hw.init = &(struct clk_init_data){ | |
1151 | .name = "cpp_clk_src", | |
1152 | .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, | |
1153 | .num_parents = 7, | |
1154 | .ops = &clk_rcg2_ops, | |
1155 | }, | |
1156 | }; | |
1157 | ||
1158 | static const struct freq_tbl ftbl_csi0_clk_src[] = { | |
1159 | F(100000000, P_GPLL0_DIV, 3, 0, 0), | |
1160 | F(200000000, P_GPLL0, 3, 0, 0), | |
1161 | F(266666667, P_MMPLL0, 3, 0, 0), | |
1162 | F(480000000, P_MMPLL4, 2, 0, 0), | |
1163 | F(600000000, P_GPLL0, 1, 0, 0), | |
1164 | { } | |
1165 | }; | |
1166 | ||
1167 | static struct clk_rcg2 csi0_clk_src = { | |
1168 | .cmd_rcgr = 0x3090, | |
1169 | .hid_width = 5, | |
1170 | .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, | |
1171 | .freq_tbl = ftbl_csi0_clk_src, | |
1172 | .clkr.hw.init = &(struct clk_init_data){ | |
1173 | .name = "csi0_clk_src", | |
1174 | .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, | |
1175 | .num_parents = 7, | |
1176 | .ops = &clk_rcg2_ops, | |
1177 | }, | |
1178 | }; | |
1179 | ||
1180 | static struct clk_rcg2 csi1_clk_src = { | |
1181 | .cmd_rcgr = 0x3100, | |
1182 | .hid_width = 5, | |
1183 | .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, | |
1184 | .freq_tbl = ftbl_csi0_clk_src, | |
1185 | .clkr.hw.init = &(struct clk_init_data){ | |
1186 | .name = "csi1_clk_src", | |
1187 | .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, | |
1188 | .num_parents = 7, | |
1189 | .ops = &clk_rcg2_ops, | |
1190 | }, | |
1191 | }; | |
1192 | ||
1193 | static struct clk_rcg2 csi2_clk_src = { | |
1194 | .cmd_rcgr = 0x3160, | |
1195 | .hid_width = 5, | |
1196 | .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, | |
1197 | .freq_tbl = ftbl_csi0_clk_src, | |
1198 | .clkr.hw.init = &(struct clk_init_data){ | |
1199 | .name = "csi2_clk_src", | |
1200 | .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, | |
1201 | .num_parents = 7, | |
1202 | .ops = &clk_rcg2_ops, | |
1203 | }, | |
1204 | }; | |
1205 | ||
1206 | static struct clk_rcg2 csi3_clk_src = { | |
1207 | .cmd_rcgr = 0x31c0, | |
1208 | .hid_width = 5, | |
1209 | .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, | |
1210 | .freq_tbl = ftbl_csi0_clk_src, | |
1211 | .clkr.hw.init = &(struct clk_init_data){ | |
1212 | .name = "csi3_clk_src", | |
1213 | .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, | |
1214 | .num_parents = 7, | |
1215 | .ops = &clk_rcg2_ops, | |
1216 | }, | |
1217 | }; | |
1218 | ||
1219 | static const struct freq_tbl ftbl_fd_core_clk_src[] = { | |
1220 | F(100000000, P_GPLL0_DIV, 3, 0, 0), | |
1221 | F(200000000, P_GPLL0, 3, 0, 0), | |
1222 | F(400000000, P_MMPLL0, 2, 0, 0), | |
1223 | { } | |
1224 | }; | |
1225 | ||
1226 | static struct clk_rcg2 fd_core_clk_src = { | |
1227 | .cmd_rcgr = 0x3b00, | |
1228 | .hid_width = 5, | |
1229 | .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, | |
1230 | .freq_tbl = ftbl_fd_core_clk_src, | |
1231 | .clkr.hw.init = &(struct clk_init_data){ | |
1232 | .name = "fd_core_clk_src", | |
1233 | .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, | |
1234 | .num_parents = 5, | |
1235 | .ops = &clk_rcg2_ops, | |
1236 | }, | |
1237 | }; | |
1238 | ||
1239 | static struct clk_branch mmss_mmagic_ahb_clk = { | |
1240 | .halt_reg = 0x5024, | |
1241 | .clkr = { | |
1242 | .enable_reg = 0x5024, | |
1243 | .enable_mask = BIT(0), | |
1244 | .hw.init = &(struct clk_init_data){ | |
1245 | .name = "mmss_mmagic_ahb_clk", | |
1246 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
1247 | .num_parents = 1, | |
1248 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
1249 | .ops = &clk_branch2_ops, | |
1250 | }, | |
1251 | }, | |
1252 | }; | |
1253 | ||
1254 | static struct clk_branch mmss_mmagic_cfg_ahb_clk = { | |
1255 | .halt_reg = 0x5054, | |
1256 | .clkr = { | |
1257 | .enable_reg = 0x5054, | |
1258 | .enable_mask = BIT(0), | |
1259 | .hw.init = &(struct clk_init_data){ | |
1260 | .name = "mmss_mmagic_cfg_ahb_clk", | |
1261 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
1262 | .num_parents = 1, | |
1263 | .flags = CLK_SET_RATE_PARENT, | |
1264 | .ops = &clk_branch2_ops, | |
1265 | }, | |
1266 | }, | |
1267 | }; | |
1268 | ||
1269 | static struct clk_branch mmss_misc_ahb_clk = { | |
1270 | .halt_reg = 0x5018, | |
1271 | .clkr = { | |
1272 | .enable_reg = 0x5018, | |
1273 | .enable_mask = BIT(0), | |
1274 | .hw.init = &(struct clk_init_data){ | |
1275 | .name = "mmss_misc_ahb_clk", | |
1276 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
1277 | .num_parents = 1, | |
1278 | .flags = CLK_SET_RATE_PARENT, | |
1279 | .ops = &clk_branch2_ops, | |
1280 | }, | |
1281 | }, | |
1282 | }; | |
1283 | ||
1284 | static struct clk_branch mmss_misc_cxo_clk = { | |
1285 | .halt_reg = 0x5014, | |
1286 | .clkr = { | |
1287 | .enable_reg = 0x5014, | |
1288 | .enable_mask = BIT(0), | |
1289 | .hw.init = &(struct clk_init_data){ | |
1290 | .name = "mmss_misc_cxo_clk", | |
1291 | .parent_names = (const char *[]){ "xo" }, | |
1292 | .num_parents = 1, | |
1293 | .ops = &clk_branch2_ops, | |
1294 | }, | |
1295 | }, | |
1296 | }; | |
1297 | ||
c2526597 SB |
1298 | static struct clk_branch mmss_mmagic_maxi_clk = { |
1299 | .halt_reg = 0x5074, | |
1300 | .clkr = { | |
1301 | .enable_reg = 0x5074, | |
1302 | .enable_mask = BIT(0), | |
1303 | .hw.init = &(struct clk_init_data){ | |
1304 | .name = "mmss_mmagic_maxi_clk", | |
1305 | .parent_names = (const char *[]){ "maxi_clk_src" }, | |
1306 | .num_parents = 1, | |
1307 | .flags = CLK_SET_RATE_PARENT, | |
1308 | .ops = &clk_branch2_ops, | |
1309 | }, | |
1310 | }, | |
1311 | }; | |
1312 | ||
1313 | static struct clk_branch mmagic_camss_axi_clk = { | |
1314 | .halt_reg = 0x3c44, | |
1315 | .clkr = { | |
1316 | .enable_reg = 0x3c44, | |
1317 | .enable_mask = BIT(0), | |
1318 | .hw.init = &(struct clk_init_data){ | |
1319 | .name = "mmagic_camss_axi_clk", | |
1320 | .parent_names = (const char *[]){ "axi_clk_src" }, | |
1321 | .num_parents = 1, | |
1322 | .flags = CLK_SET_RATE_PARENT, | |
1323 | .ops = &clk_branch2_ops, | |
1324 | }, | |
1325 | }, | |
1326 | }; | |
1327 | ||
1328 | static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = { | |
1329 | .halt_reg = 0x3c48, | |
1330 | .clkr = { | |
1331 | .enable_reg = 0x3c48, | |
1332 | .enable_mask = BIT(0), | |
1333 | .hw.init = &(struct clk_init_data){ | |
1334 | .name = "mmagic_camss_noc_cfg_ahb_clk", | |
1335 | .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, | |
1336 | .num_parents = 1, | |
1337 | .flags = CLK_SET_RATE_PARENT, | |
1338 | .ops = &clk_branch2_ops, | |
1339 | }, | |
1340 | }, | |
1341 | }; | |
1342 | ||
1343 | static struct clk_branch smmu_vfe_ahb_clk = { | |
1344 | .halt_reg = 0x3c04, | |
1345 | .clkr = { | |
1346 | .enable_reg = 0x3c04, | |
1347 | .enable_mask = BIT(0), | |
1348 | .hw.init = &(struct clk_init_data){ | |
1349 | .name = "smmu_vfe_ahb_clk", | |
1350 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
1351 | .num_parents = 1, | |
1352 | .flags = CLK_SET_RATE_PARENT, | |
1353 | .ops = &clk_branch2_ops, | |
1354 | }, | |
1355 | }, | |
1356 | }; | |
1357 | ||
1358 | static struct clk_branch smmu_vfe_axi_clk = { | |
1359 | .halt_reg = 0x3c08, | |
1360 | .clkr = { | |
1361 | .enable_reg = 0x3c08, | |
1362 | .enable_mask = BIT(0), | |
1363 | .hw.init = &(struct clk_init_data){ | |
1364 | .name = "smmu_vfe_axi_clk", | |
1365 | .parent_names = (const char *[]){ "axi_clk_src" }, | |
1366 | .num_parents = 1, | |
1367 | .flags = CLK_SET_RATE_PARENT, | |
1368 | .ops = &clk_branch2_ops, | |
1369 | }, | |
1370 | }, | |
1371 | }; | |
1372 | ||
1373 | static struct clk_branch smmu_cpp_ahb_clk = { | |
1374 | .halt_reg = 0x3c14, | |
1375 | .clkr = { | |
1376 | .enable_reg = 0x3c14, | |
1377 | .enable_mask = BIT(0), | |
1378 | .hw.init = &(struct clk_init_data){ | |
1379 | .name = "smmu_cpp_ahb_clk", | |
1380 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
1381 | .num_parents = 1, | |
1382 | .flags = CLK_SET_RATE_PARENT, | |
1383 | .ops = &clk_branch2_ops, | |
1384 | }, | |
1385 | }, | |
1386 | }; | |
1387 | ||
1388 | static struct clk_branch smmu_cpp_axi_clk = { | |
1389 | .halt_reg = 0x3c18, | |
1390 | .clkr = { | |
1391 | .enable_reg = 0x3c18, | |
1392 | .enable_mask = BIT(0), | |
1393 | .hw.init = &(struct clk_init_data){ | |
1394 | .name = "smmu_cpp_axi_clk", | |
1395 | .parent_names = (const char *[]){ "axi_clk_src" }, | |
1396 | .num_parents = 1, | |
1397 | .flags = CLK_SET_RATE_PARENT, | |
1398 | .ops = &clk_branch2_ops, | |
1399 | }, | |
1400 | }, | |
1401 | }; | |
1402 | ||
1403 | static struct clk_branch smmu_jpeg_ahb_clk = { | |
1404 | .halt_reg = 0x3c24, | |
1405 | .clkr = { | |
1406 | .enable_reg = 0x3c24, | |
1407 | .enable_mask = BIT(0), | |
1408 | .hw.init = &(struct clk_init_data){ | |
1409 | .name = "smmu_jpeg_ahb_clk", | |
1410 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
1411 | .num_parents = 1, | |
1412 | .flags = CLK_SET_RATE_PARENT, | |
1413 | .ops = &clk_branch2_ops, | |
1414 | }, | |
1415 | }, | |
1416 | }; | |
1417 | ||
1418 | static struct clk_branch smmu_jpeg_axi_clk = { | |
1419 | .halt_reg = 0x3c28, | |
1420 | .clkr = { | |
1421 | .enable_reg = 0x3c28, | |
1422 | .enable_mask = BIT(0), | |
1423 | .hw.init = &(struct clk_init_data){ | |
1424 | .name = "smmu_jpeg_axi_clk", | |
1425 | .parent_names = (const char *[]){ "axi_clk_src" }, | |
1426 | .num_parents = 1, | |
1427 | .flags = CLK_SET_RATE_PARENT, | |
1428 | .ops = &clk_branch2_ops, | |
1429 | }, | |
1430 | }, | |
1431 | }; | |
1432 | ||
1433 | static struct clk_branch mmagic_mdss_axi_clk = { | |
1434 | .halt_reg = 0x2474, | |
1435 | .clkr = { | |
1436 | .enable_reg = 0x2474, | |
1437 | .enable_mask = BIT(0), | |
1438 | .hw.init = &(struct clk_init_data){ | |
1439 | .name = "mmagic_mdss_axi_clk", | |
1440 | .parent_names = (const char *[]){ "axi_clk_src" }, | |
1441 | .num_parents = 1, | |
1442 | .flags = CLK_SET_RATE_PARENT, | |
1443 | .ops = &clk_branch2_ops, | |
1444 | }, | |
1445 | }, | |
1446 | }; | |
1447 | ||
1448 | static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = { | |
1449 | .halt_reg = 0x2478, | |
1450 | .clkr = { | |
1451 | .enable_reg = 0x2478, | |
1452 | .enable_mask = BIT(0), | |
1453 | .hw.init = &(struct clk_init_data){ | |
1454 | .name = "mmagic_mdss_noc_cfg_ahb_clk", | |
1455 | .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, | |
1456 | .num_parents = 1, | |
1457 | .flags = CLK_SET_RATE_PARENT, | |
1458 | .ops = &clk_branch2_ops, | |
1459 | }, | |
1460 | }, | |
1461 | }; | |
1462 | ||
1463 | static struct clk_branch smmu_rot_ahb_clk = { | |
1464 | .halt_reg = 0x2444, | |
1465 | .clkr = { | |
1466 | .enable_reg = 0x2444, | |
1467 | .enable_mask = BIT(0), | |
1468 | .hw.init = &(struct clk_init_data){ | |
1469 | .name = "smmu_rot_ahb_clk", | |
1470 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
1471 | .num_parents = 1, | |
1472 | .flags = CLK_SET_RATE_PARENT, | |
1473 | .ops = &clk_branch2_ops, | |
1474 | }, | |
1475 | }, | |
1476 | }; | |
1477 | ||
1478 | static struct clk_branch smmu_rot_axi_clk = { | |
1479 | .halt_reg = 0x2448, | |
1480 | .clkr = { | |
1481 | .enable_reg = 0x2448, | |
1482 | .enable_mask = BIT(0), | |
1483 | .hw.init = &(struct clk_init_data){ | |
1484 | .name = "smmu_rot_axi_clk", | |
1485 | .parent_names = (const char *[]){ "axi_clk_src" }, | |
1486 | .num_parents = 1, | |
1487 | .flags = CLK_SET_RATE_PARENT, | |
1488 | .ops = &clk_branch2_ops, | |
1489 | }, | |
1490 | }, | |
1491 | }; | |
1492 | ||
1493 | static struct clk_branch smmu_mdp_ahb_clk = { | |
1494 | .halt_reg = 0x2454, | |
1495 | .clkr = { | |
1496 | .enable_reg = 0x2454, | |
1497 | .enable_mask = BIT(0), | |
1498 | .hw.init = &(struct clk_init_data){ | |
1499 | .name = "smmu_mdp_ahb_clk", | |
1500 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
1501 | .num_parents = 1, | |
1502 | .flags = CLK_SET_RATE_PARENT, | |
1503 | .ops = &clk_branch2_ops, | |
1504 | }, | |
1505 | }, | |
1506 | }; | |
1507 | ||
1508 | static struct clk_branch smmu_mdp_axi_clk = { | |
1509 | .halt_reg = 0x2458, | |
1510 | .clkr = { | |
1511 | .enable_reg = 0x2458, | |
1512 | .enable_mask = BIT(0), | |
1513 | .hw.init = &(struct clk_init_data){ | |
1514 | .name = "smmu_mdp_axi_clk", | |
1515 | .parent_names = (const char *[]){ "axi_clk_src" }, | |
1516 | .num_parents = 1, | |
1517 | .flags = CLK_SET_RATE_PARENT, | |
1518 | .ops = &clk_branch2_ops, | |
1519 | }, | |
1520 | }, | |
1521 | }; | |
1522 | ||
1523 | static struct clk_branch mmagic_video_axi_clk = { | |
1524 | .halt_reg = 0x1194, | |
1525 | .clkr = { | |
1526 | .enable_reg = 0x1194, | |
1527 | .enable_mask = BIT(0), | |
1528 | .hw.init = &(struct clk_init_data){ | |
1529 | .name = "mmagic_video_axi_clk", | |
1530 | .parent_names = (const char *[]){ "axi_clk_src" }, | |
1531 | .num_parents = 1, | |
1532 | .flags = CLK_SET_RATE_PARENT, | |
1533 | .ops = &clk_branch2_ops, | |
1534 | }, | |
1535 | }, | |
1536 | }; | |
1537 | ||
1538 | static struct clk_branch mmagic_video_noc_cfg_ahb_clk = { | |
1539 | .halt_reg = 0x1198, | |
1540 | .clkr = { | |
1541 | .enable_reg = 0x1198, | |
1542 | .enable_mask = BIT(0), | |
1543 | .hw.init = &(struct clk_init_data){ | |
1544 | .name = "mmagic_video_noc_cfg_ahb_clk", | |
1545 | .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, | |
1546 | .num_parents = 1, | |
1547 | .flags = CLK_SET_RATE_PARENT, | |
1548 | .ops = &clk_branch2_ops, | |
1549 | }, | |
1550 | }, | |
1551 | }; | |
1552 | ||
1553 | static struct clk_branch smmu_video_ahb_clk = { | |
1554 | .halt_reg = 0x1174, | |
1555 | .clkr = { | |
1556 | .enable_reg = 0x1174, | |
1557 | .enable_mask = BIT(0), | |
1558 | .hw.init = &(struct clk_init_data){ | |
1559 | .name = "smmu_video_ahb_clk", | |
1560 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
1561 | .num_parents = 1, | |
1562 | .flags = CLK_SET_RATE_PARENT, | |
1563 | .ops = &clk_branch2_ops, | |
1564 | }, | |
1565 | }, | |
1566 | }; | |
1567 | ||
1568 | static struct clk_branch smmu_video_axi_clk = { | |
1569 | .halt_reg = 0x1178, | |
1570 | .clkr = { | |
1571 | .enable_reg = 0x1178, | |
1572 | .enable_mask = BIT(0), | |
1573 | .hw.init = &(struct clk_init_data){ | |
1574 | .name = "smmu_video_axi_clk", | |
1575 | .parent_names = (const char *[]){ "axi_clk_src" }, | |
1576 | .num_parents = 1, | |
1577 | .flags = CLK_SET_RATE_PARENT, | |
1578 | .ops = &clk_branch2_ops, | |
1579 | }, | |
1580 | }, | |
1581 | }; | |
1582 | ||
c2526597 SB |
1583 | static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = { |
1584 | .halt_reg = 0x5298, | |
1585 | .clkr = { | |
1586 | .enable_reg = 0x5298, | |
1587 | .enable_mask = BIT(0), | |
1588 | .hw.init = &(struct clk_init_data){ | |
1589 | .name = "mmagic_bimc_noc_cfg_ahb_clk", | |
1590 | .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, | |
1591 | .num_parents = 1, | |
1592 | .flags = CLK_SET_RATE_PARENT, | |
1593 | .ops = &clk_branch2_ops, | |
1594 | }, | |
1595 | }, | |
1596 | }; | |
1597 | ||
1598 | static struct clk_branch gpu_gx_gfx3d_clk = { | |
1599 | .halt_reg = 0x4028, | |
1600 | .clkr = { | |
1601 | .enable_reg = 0x4028, | |
1602 | .enable_mask = BIT(0), | |
1603 | .hw.init = &(struct clk_init_data){ | |
1604 | .name = "gpu_gx_gfx3d_clk", | |
1605 | .parent_names = (const char *[]){ "gfx3d_clk_src" }, | |
1606 | .num_parents = 1, | |
1607 | .flags = CLK_SET_RATE_PARENT, | |
1608 | .ops = &clk_branch2_ops, | |
1609 | }, | |
1610 | }, | |
1611 | }; | |
1612 | ||
1613 | static struct clk_branch gpu_gx_rbbmtimer_clk = { | |
1614 | .halt_reg = 0x40b0, | |
1615 | .clkr = { | |
1616 | .enable_reg = 0x40b0, | |
1617 | .enable_mask = BIT(0), | |
1618 | .hw.init = &(struct clk_init_data){ | |
1619 | .name = "gpu_gx_rbbmtimer_clk", | |
1620 | .parent_names = (const char *[]){ "rbbmtimer_clk_src" }, | |
1621 | .num_parents = 1, | |
1622 | .flags = CLK_SET_RATE_PARENT, | |
1623 | .ops = &clk_branch2_ops, | |
1624 | }, | |
1625 | }, | |
1626 | }; | |
1627 | ||
1628 | static struct clk_branch gpu_ahb_clk = { | |
1629 | .halt_reg = 0x403c, | |
1630 | .clkr = { | |
1631 | .enable_reg = 0x403c, | |
1632 | .enable_mask = BIT(0), | |
1633 | .hw.init = &(struct clk_init_data){ | |
1634 | .name = "gpu_ahb_clk", | |
1635 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
1636 | .num_parents = 1, | |
1637 | .flags = CLK_SET_RATE_PARENT, | |
1638 | .ops = &clk_branch2_ops, | |
1639 | }, | |
1640 | }, | |
1641 | }; | |
1642 | ||
1643 | static struct clk_branch gpu_aon_isense_clk = { | |
1644 | .halt_reg = 0x4044, | |
1645 | .clkr = { | |
1646 | .enable_reg = 0x4044, | |
1647 | .enable_mask = BIT(0), | |
1648 | .hw.init = &(struct clk_init_data){ | |
1649 | .name = "gpu_aon_isense_clk", | |
1650 | .parent_names = (const char *[]){ "isense_clk_src" }, | |
1651 | .num_parents = 1, | |
1652 | .flags = CLK_SET_RATE_PARENT, | |
1653 | .ops = &clk_branch2_ops, | |
1654 | }, | |
1655 | }, | |
1656 | }; | |
1657 | ||
1658 | static struct clk_branch vmem_maxi_clk = { | |
1659 | .halt_reg = 0x1204, | |
1660 | .clkr = { | |
1661 | .enable_reg = 0x1204, | |
1662 | .enable_mask = BIT(0), | |
1663 | .hw.init = &(struct clk_init_data){ | |
1664 | .name = "vmem_maxi_clk", | |
1665 | .parent_names = (const char *[]){ "maxi_clk_src" }, | |
1666 | .num_parents = 1, | |
1667 | .flags = CLK_SET_RATE_PARENT, | |
1668 | .ops = &clk_branch2_ops, | |
1669 | }, | |
1670 | }, | |
1671 | }; | |
1672 | ||
1673 | static struct clk_branch vmem_ahb_clk = { | |
1674 | .halt_reg = 0x1208, | |
1675 | .clkr = { | |
1676 | .enable_reg = 0x1208, | |
1677 | .enable_mask = BIT(0), | |
1678 | .hw.init = &(struct clk_init_data){ | |
1679 | .name = "vmem_ahb_clk", | |
1680 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
1681 | .num_parents = 1, | |
1682 | .flags = CLK_SET_RATE_PARENT, | |
1683 | .ops = &clk_branch2_ops, | |
1684 | }, | |
1685 | }, | |
1686 | }; | |
1687 | ||
1688 | static struct clk_branch mmss_rbcpr_clk = { | |
1689 | .halt_reg = 0x4084, | |
1690 | .clkr = { | |
1691 | .enable_reg = 0x4084, | |
1692 | .enable_mask = BIT(0), | |
1693 | .hw.init = &(struct clk_init_data){ | |
1694 | .name = "mmss_rbcpr_clk", | |
1695 | .parent_names = (const char *[]){ "rbcpr_clk_src" }, | |
1696 | .num_parents = 1, | |
1697 | .flags = CLK_SET_RATE_PARENT, | |
1698 | .ops = &clk_branch2_ops, | |
1699 | }, | |
1700 | }, | |
1701 | }; | |
1702 | ||
1703 | static struct clk_branch mmss_rbcpr_ahb_clk = { | |
1704 | .halt_reg = 0x4088, | |
1705 | .clkr = { | |
1706 | .enable_reg = 0x4088, | |
1707 | .enable_mask = BIT(0), | |
1708 | .hw.init = &(struct clk_init_data){ | |
1709 | .name = "mmss_rbcpr_ahb_clk", | |
1710 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
1711 | .num_parents = 1, | |
1712 | .flags = CLK_SET_RATE_PARENT, | |
1713 | .ops = &clk_branch2_ops, | |
1714 | }, | |
1715 | }, | |
1716 | }; | |
1717 | ||
1718 | static struct clk_branch video_core_clk = { | |
1719 | .halt_reg = 0x1028, | |
1720 | .clkr = { | |
1721 | .enable_reg = 0x1028, | |
1722 | .enable_mask = BIT(0), | |
1723 | .hw.init = &(struct clk_init_data){ | |
1724 | .name = "video_core_clk", | |
1725 | .parent_names = (const char *[]){ "video_core_clk_src" }, | |
1726 | .num_parents = 1, | |
1727 | .flags = CLK_SET_RATE_PARENT, | |
1728 | .ops = &clk_branch2_ops, | |
1729 | }, | |
1730 | }, | |
1731 | }; | |
1732 | ||
1733 | static struct clk_branch video_axi_clk = { | |
1734 | .halt_reg = 0x1034, | |
1735 | .clkr = { | |
1736 | .enable_reg = 0x1034, | |
1737 | .enable_mask = BIT(0), | |
1738 | .hw.init = &(struct clk_init_data){ | |
1739 | .name = "video_axi_clk", | |
1740 | .parent_names = (const char *[]){ "axi_clk_src" }, | |
1741 | .num_parents = 1, | |
1742 | .flags = CLK_SET_RATE_PARENT, | |
1743 | .ops = &clk_branch2_ops, | |
1744 | }, | |
1745 | }, | |
1746 | }; | |
1747 | ||
1748 | static struct clk_branch video_maxi_clk = { | |
1749 | .halt_reg = 0x1038, | |
1750 | .clkr = { | |
1751 | .enable_reg = 0x1038, | |
1752 | .enable_mask = BIT(0), | |
1753 | .hw.init = &(struct clk_init_data){ | |
1754 | .name = "video_maxi_clk", | |
1755 | .parent_names = (const char *[]){ "maxi_clk_src" }, | |
1756 | .num_parents = 1, | |
1757 | .flags = CLK_SET_RATE_PARENT, | |
1758 | .ops = &clk_branch2_ops, | |
1759 | }, | |
1760 | }, | |
1761 | }; | |
1762 | ||
1763 | static struct clk_branch video_ahb_clk = { | |
1764 | .halt_reg = 0x1030, | |
1765 | .clkr = { | |
1766 | .enable_reg = 0x1030, | |
1767 | .enable_mask = BIT(0), | |
1768 | .hw.init = &(struct clk_init_data){ | |
1769 | .name = "video_ahb_clk", | |
1770 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
1771 | .num_parents = 1, | |
1772 | .flags = CLK_SET_RATE_PARENT, | |
1773 | .ops = &clk_branch2_ops, | |
1774 | }, | |
1775 | }, | |
1776 | }; | |
1777 | ||
1778 | static struct clk_branch video_subcore0_clk = { | |
1779 | .halt_reg = 0x1048, | |
1780 | .clkr = { | |
1781 | .enable_reg = 0x1048, | |
1782 | .enable_mask = BIT(0), | |
1783 | .hw.init = &(struct clk_init_data){ | |
1784 | .name = "video_subcore0_clk", | |
1785 | .parent_names = (const char *[]){ "video_subcore0_clk_src" }, | |
1786 | .num_parents = 1, | |
1787 | .flags = CLK_SET_RATE_PARENT, | |
1788 | .ops = &clk_branch2_ops, | |
1789 | }, | |
1790 | }, | |
1791 | }; | |
1792 | ||
1793 | static struct clk_branch video_subcore1_clk = { | |
1794 | .halt_reg = 0x104c, | |
1795 | .clkr = { | |
1796 | .enable_reg = 0x104c, | |
1797 | .enable_mask = BIT(0), | |
1798 | .hw.init = &(struct clk_init_data){ | |
1799 | .name = "video_subcore1_clk", | |
1800 | .parent_names = (const char *[]){ "video_subcore1_clk_src" }, | |
1801 | .num_parents = 1, | |
1802 | .flags = CLK_SET_RATE_PARENT, | |
1803 | .ops = &clk_branch2_ops, | |
1804 | }, | |
1805 | }, | |
1806 | }; | |
1807 | ||
1808 | static struct clk_branch mdss_ahb_clk = { | |
1809 | .halt_reg = 0x2308, | |
1810 | .clkr = { | |
1811 | .enable_reg = 0x2308, | |
1812 | .enable_mask = BIT(0), | |
1813 | .hw.init = &(struct clk_init_data){ | |
1814 | .name = "mdss_ahb_clk", | |
1815 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
1816 | .num_parents = 1, | |
1817 | .flags = CLK_SET_RATE_PARENT, | |
1818 | .ops = &clk_branch2_ops, | |
1819 | }, | |
1820 | }, | |
1821 | }; | |
1822 | ||
1823 | static struct clk_branch mdss_hdmi_ahb_clk = { | |
1824 | .halt_reg = 0x230c, | |
1825 | .clkr = { | |
1826 | .enable_reg = 0x230c, | |
1827 | .enable_mask = BIT(0), | |
1828 | .hw.init = &(struct clk_init_data){ | |
1829 | .name = "mdss_hdmi_ahb_clk", | |
1830 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
1831 | .num_parents = 1, | |
1832 | .flags = CLK_SET_RATE_PARENT, | |
1833 | .ops = &clk_branch2_ops, | |
1834 | }, | |
1835 | }, | |
1836 | }; | |
1837 | ||
1838 | static struct clk_branch mdss_axi_clk = { | |
1839 | .halt_reg = 0x2310, | |
1840 | .clkr = { | |
1841 | .enable_reg = 0x2310, | |
1842 | .enable_mask = BIT(0), | |
1843 | .hw.init = &(struct clk_init_data){ | |
1844 | .name = "mdss_axi_clk", | |
1845 | .parent_names = (const char *[]){ "axi_clk_src" }, | |
1846 | .num_parents = 1, | |
1847 | .flags = CLK_SET_RATE_PARENT, | |
1848 | .ops = &clk_branch2_ops, | |
1849 | }, | |
1850 | }, | |
1851 | }; | |
1852 | ||
1853 | static struct clk_branch mdss_pclk0_clk = { | |
1854 | .halt_reg = 0x2314, | |
1855 | .clkr = { | |
1856 | .enable_reg = 0x2314, | |
1857 | .enable_mask = BIT(0), | |
1858 | .hw.init = &(struct clk_init_data){ | |
1859 | .name = "mdss_pclk0_clk", | |
1860 | .parent_names = (const char *[]){ "pclk0_clk_src" }, | |
1861 | .num_parents = 1, | |
1862 | .flags = CLK_SET_RATE_PARENT, | |
1863 | .ops = &clk_branch2_ops, | |
1864 | }, | |
1865 | }, | |
1866 | }; | |
1867 | ||
1868 | static struct clk_branch mdss_pclk1_clk = { | |
1869 | .halt_reg = 0x2318, | |
1870 | .clkr = { | |
1871 | .enable_reg = 0x2318, | |
1872 | .enable_mask = BIT(0), | |
1873 | .hw.init = &(struct clk_init_data){ | |
1874 | .name = "mdss_pclk1_clk", | |
1875 | .parent_names = (const char *[]){ "pclk1_clk_src" }, | |
1876 | .num_parents = 1, | |
1877 | .flags = CLK_SET_RATE_PARENT, | |
1878 | .ops = &clk_branch2_ops, | |
1879 | }, | |
1880 | }, | |
1881 | }; | |
1882 | ||
1883 | static struct clk_branch mdss_mdp_clk = { | |
1884 | .halt_reg = 0x231c, | |
1885 | .clkr = { | |
1886 | .enable_reg = 0x231c, | |
1887 | .enable_mask = BIT(0), | |
1888 | .hw.init = &(struct clk_init_data){ | |
1889 | .name = "mdss_mdp_clk", | |
1890 | .parent_names = (const char *[]){ "mdp_clk_src" }, | |
1891 | .num_parents = 1, | |
1892 | .flags = CLK_SET_RATE_PARENT, | |
1893 | .ops = &clk_branch2_ops, | |
1894 | }, | |
1895 | }, | |
1896 | }; | |
1897 | ||
1898 | static struct clk_branch mdss_extpclk_clk = { | |
1899 | .halt_reg = 0x2324, | |
1900 | .clkr = { | |
1901 | .enable_reg = 0x2324, | |
1902 | .enable_mask = BIT(0), | |
1903 | .hw.init = &(struct clk_init_data){ | |
1904 | .name = "mdss_extpclk_clk", | |
1905 | .parent_names = (const char *[]){ "extpclk_clk_src" }, | |
1906 | .num_parents = 1, | |
1907 | .flags = CLK_SET_RATE_PARENT, | |
1908 | .ops = &clk_branch2_ops, | |
1909 | }, | |
1910 | }, | |
1911 | }; | |
1912 | ||
1913 | static struct clk_branch mdss_vsync_clk = { | |
1914 | .halt_reg = 0x2328, | |
1915 | .clkr = { | |
1916 | .enable_reg = 0x2328, | |
1917 | .enable_mask = BIT(0), | |
1918 | .hw.init = &(struct clk_init_data){ | |
1919 | .name = "mdss_vsync_clk", | |
1920 | .parent_names = (const char *[]){ "vsync_clk_src" }, | |
1921 | .num_parents = 1, | |
1922 | .flags = CLK_SET_RATE_PARENT, | |
1923 | .ops = &clk_branch2_ops, | |
1924 | }, | |
1925 | }, | |
1926 | }; | |
1927 | ||
1928 | static struct clk_branch mdss_hdmi_clk = { | |
1929 | .halt_reg = 0x2338, | |
1930 | .clkr = { | |
1931 | .enable_reg = 0x2338, | |
1932 | .enable_mask = BIT(0), | |
1933 | .hw.init = &(struct clk_init_data){ | |
1934 | .name = "mdss_hdmi_clk", | |
1935 | .parent_names = (const char *[]){ "hdmi_clk_src" }, | |
1936 | .num_parents = 1, | |
1937 | .flags = CLK_SET_RATE_PARENT, | |
1938 | .ops = &clk_branch2_ops, | |
1939 | }, | |
1940 | }, | |
1941 | }; | |
1942 | ||
1943 | static struct clk_branch mdss_byte0_clk = { | |
1944 | .halt_reg = 0x233c, | |
1945 | .clkr = { | |
1946 | .enable_reg = 0x233c, | |
1947 | .enable_mask = BIT(0), | |
1948 | .hw.init = &(struct clk_init_data){ | |
1949 | .name = "mdss_byte0_clk", | |
1950 | .parent_names = (const char *[]){ "byte0_clk_src" }, | |
1951 | .num_parents = 1, | |
1952 | .flags = CLK_SET_RATE_PARENT, | |
1953 | .ops = &clk_branch2_ops, | |
1954 | }, | |
1955 | }, | |
1956 | }; | |
1957 | ||
1958 | static struct clk_branch mdss_byte1_clk = { | |
1959 | .halt_reg = 0x2340, | |
1960 | .clkr = { | |
1961 | .enable_reg = 0x2340, | |
1962 | .enable_mask = BIT(0), | |
1963 | .hw.init = &(struct clk_init_data){ | |
1964 | .name = "mdss_byte1_clk", | |
1965 | .parent_names = (const char *[]){ "byte1_clk_src" }, | |
1966 | .num_parents = 1, | |
1967 | .flags = CLK_SET_RATE_PARENT, | |
1968 | .ops = &clk_branch2_ops, | |
1969 | }, | |
1970 | }, | |
1971 | }; | |
1972 | ||
1973 | static struct clk_branch mdss_esc0_clk = { | |
1974 | .halt_reg = 0x2344, | |
1975 | .clkr = { | |
1976 | .enable_reg = 0x2344, | |
1977 | .enable_mask = BIT(0), | |
1978 | .hw.init = &(struct clk_init_data){ | |
1979 | .name = "mdss_esc0_clk", | |
1980 | .parent_names = (const char *[]){ "esc0_clk_src" }, | |
1981 | .num_parents = 1, | |
1982 | .flags = CLK_SET_RATE_PARENT, | |
1983 | .ops = &clk_branch2_ops, | |
1984 | }, | |
1985 | }, | |
1986 | }; | |
1987 | ||
1988 | static struct clk_branch mdss_esc1_clk = { | |
1989 | .halt_reg = 0x2348, | |
1990 | .clkr = { | |
1991 | .enable_reg = 0x2348, | |
1992 | .enable_mask = BIT(0), | |
1993 | .hw.init = &(struct clk_init_data){ | |
1994 | .name = "mdss_esc1_clk", | |
1995 | .parent_names = (const char *[]){ "esc1_clk_src" }, | |
1996 | .num_parents = 1, | |
1997 | .flags = CLK_SET_RATE_PARENT, | |
1998 | .ops = &clk_branch2_ops, | |
1999 | }, | |
2000 | }, | |
2001 | }; | |
2002 | ||
2003 | static struct clk_branch camss_top_ahb_clk = { | |
2004 | .halt_reg = 0x3484, | |
2005 | .clkr = { | |
2006 | .enable_reg = 0x3484, | |
2007 | .enable_mask = BIT(0), | |
2008 | .hw.init = &(struct clk_init_data){ | |
2009 | .name = "camss_top_ahb_clk", | |
2010 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
2011 | .num_parents = 1, | |
2012 | .flags = CLK_SET_RATE_PARENT, | |
2013 | .ops = &clk_branch2_ops, | |
2014 | }, | |
2015 | }, | |
2016 | }; | |
2017 | ||
2018 | static struct clk_branch camss_ahb_clk = { | |
2019 | .halt_reg = 0x348c, | |
2020 | .clkr = { | |
2021 | .enable_reg = 0x348c, | |
2022 | .enable_mask = BIT(0), | |
2023 | .hw.init = &(struct clk_init_data){ | |
2024 | .name = "camss_ahb_clk", | |
2025 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
2026 | .num_parents = 1, | |
2027 | .flags = CLK_SET_RATE_PARENT, | |
2028 | .ops = &clk_branch2_ops, | |
2029 | }, | |
2030 | }, | |
2031 | }; | |
2032 | ||
2033 | static struct clk_branch camss_micro_ahb_clk = { | |
2034 | .halt_reg = 0x3494, | |
2035 | .clkr = { | |
2036 | .enable_reg = 0x3494, | |
2037 | .enable_mask = BIT(0), | |
2038 | .hw.init = &(struct clk_init_data){ | |
2039 | .name = "camss_micro_ahb_clk", | |
2040 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
2041 | .num_parents = 1, | |
2042 | .flags = CLK_SET_RATE_PARENT, | |
2043 | .ops = &clk_branch2_ops, | |
2044 | }, | |
2045 | }, | |
2046 | }; | |
2047 | ||
2048 | static struct clk_branch camss_gp0_clk = { | |
2049 | .halt_reg = 0x3444, | |
2050 | .clkr = { | |
2051 | .enable_reg = 0x3444, | |
2052 | .enable_mask = BIT(0), | |
2053 | .hw.init = &(struct clk_init_data){ | |
2054 | .name = "camss_gp0_clk", | |
2055 | .parent_names = (const char *[]){ "camss_gp0_clk_src" }, | |
2056 | .num_parents = 1, | |
2057 | .flags = CLK_SET_RATE_PARENT, | |
2058 | .ops = &clk_branch2_ops, | |
2059 | }, | |
2060 | }, | |
2061 | }; | |
2062 | ||
2063 | static struct clk_branch camss_gp1_clk = { | |
2064 | .halt_reg = 0x3474, | |
2065 | .clkr = { | |
2066 | .enable_reg = 0x3474, | |
2067 | .enable_mask = BIT(0), | |
2068 | .hw.init = &(struct clk_init_data){ | |
2069 | .name = "camss_gp1_clk", | |
2070 | .parent_names = (const char *[]){ "camss_gp1_clk_src" }, | |
2071 | .num_parents = 1, | |
2072 | .flags = CLK_SET_RATE_PARENT, | |
2073 | .ops = &clk_branch2_ops, | |
2074 | }, | |
2075 | }, | |
2076 | }; | |
2077 | ||
2078 | static struct clk_branch camss_mclk0_clk = { | |
2079 | .halt_reg = 0x3384, | |
2080 | .clkr = { | |
2081 | .enable_reg = 0x3384, | |
2082 | .enable_mask = BIT(0), | |
2083 | .hw.init = &(struct clk_init_data){ | |
2084 | .name = "camss_mclk0_clk", | |
2085 | .parent_names = (const char *[]){ "mclk0_clk_src" }, | |
2086 | .num_parents = 1, | |
2087 | .flags = CLK_SET_RATE_PARENT, | |
2088 | .ops = &clk_branch2_ops, | |
2089 | }, | |
2090 | }, | |
2091 | }; | |
2092 | ||
2093 | static struct clk_branch camss_mclk1_clk = { | |
2094 | .halt_reg = 0x33b4, | |
2095 | .clkr = { | |
2096 | .enable_reg = 0x33b4, | |
2097 | .enable_mask = BIT(0), | |
2098 | .hw.init = &(struct clk_init_data){ | |
2099 | .name = "camss_mclk1_clk", | |
2100 | .parent_names = (const char *[]){ "mclk1_clk_src" }, | |
2101 | .num_parents = 1, | |
2102 | .flags = CLK_SET_RATE_PARENT, | |
2103 | .ops = &clk_branch2_ops, | |
2104 | }, | |
2105 | }, | |
2106 | }; | |
2107 | ||
2108 | static struct clk_branch camss_mclk2_clk = { | |
2109 | .halt_reg = 0x33e4, | |
2110 | .clkr = { | |
2111 | .enable_reg = 0x33e4, | |
2112 | .enable_mask = BIT(0), | |
2113 | .hw.init = &(struct clk_init_data){ | |
2114 | .name = "camss_mclk2_clk", | |
2115 | .parent_names = (const char *[]){ "mclk2_clk_src" }, | |
2116 | .num_parents = 1, | |
2117 | .flags = CLK_SET_RATE_PARENT, | |
2118 | .ops = &clk_branch2_ops, | |
2119 | }, | |
2120 | }, | |
2121 | }; | |
2122 | ||
2123 | static struct clk_branch camss_mclk3_clk = { | |
2124 | .halt_reg = 0x3414, | |
2125 | .clkr = { | |
2126 | .enable_reg = 0x3414, | |
2127 | .enable_mask = BIT(0), | |
2128 | .hw.init = &(struct clk_init_data){ | |
2129 | .name = "camss_mclk3_clk", | |
2130 | .parent_names = (const char *[]){ "mclk3_clk_src" }, | |
2131 | .num_parents = 1, | |
2132 | .flags = CLK_SET_RATE_PARENT, | |
2133 | .ops = &clk_branch2_ops, | |
2134 | }, | |
2135 | }, | |
2136 | }; | |
2137 | ||
2138 | static struct clk_branch camss_cci_clk = { | |
2139 | .halt_reg = 0x3344, | |
2140 | .clkr = { | |
2141 | .enable_reg = 0x3344, | |
2142 | .enable_mask = BIT(0), | |
2143 | .hw.init = &(struct clk_init_data){ | |
2144 | .name = "camss_cci_clk", | |
2145 | .parent_names = (const char *[]){ "cci_clk_src" }, | |
2146 | .num_parents = 1, | |
2147 | .flags = CLK_SET_RATE_PARENT, | |
2148 | .ops = &clk_branch2_ops, | |
2149 | }, | |
2150 | }, | |
2151 | }; | |
2152 | ||
2153 | static struct clk_branch camss_cci_ahb_clk = { | |
2154 | .halt_reg = 0x3348, | |
2155 | .clkr = { | |
2156 | .enable_reg = 0x3348, | |
2157 | .enable_mask = BIT(0), | |
2158 | .hw.init = &(struct clk_init_data){ | |
2159 | .name = "camss_cci_ahb_clk", | |
2160 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
2161 | .num_parents = 1, | |
2162 | .flags = CLK_SET_RATE_PARENT, | |
2163 | .ops = &clk_branch2_ops, | |
2164 | }, | |
2165 | }, | |
2166 | }; | |
2167 | ||
2168 | static struct clk_branch camss_csi0phytimer_clk = { | |
2169 | .halt_reg = 0x3024, | |
2170 | .clkr = { | |
2171 | .enable_reg = 0x3024, | |
2172 | .enable_mask = BIT(0), | |
2173 | .hw.init = &(struct clk_init_data){ | |
2174 | .name = "camss_csi0phytimer_clk", | |
2175 | .parent_names = (const char *[]){ "csi0phytimer_clk_src" }, | |
2176 | .num_parents = 1, | |
2177 | .flags = CLK_SET_RATE_PARENT, | |
2178 | .ops = &clk_branch2_ops, | |
2179 | }, | |
2180 | }, | |
2181 | }; | |
2182 | ||
2183 | static struct clk_branch camss_csi1phytimer_clk = { | |
2184 | .halt_reg = 0x3054, | |
2185 | .clkr = { | |
2186 | .enable_reg = 0x3054, | |
2187 | .enable_mask = BIT(0), | |
2188 | .hw.init = &(struct clk_init_data){ | |
2189 | .name = "camss_csi1phytimer_clk", | |
2190 | .parent_names = (const char *[]){ "csi1phytimer_clk_src" }, | |
2191 | .num_parents = 1, | |
2192 | .flags = CLK_SET_RATE_PARENT, | |
2193 | .ops = &clk_branch2_ops, | |
2194 | }, | |
2195 | }, | |
2196 | }; | |
2197 | ||
2198 | static struct clk_branch camss_csi2phytimer_clk = { | |
2199 | .halt_reg = 0x3084, | |
2200 | .clkr = { | |
2201 | .enable_reg = 0x3084, | |
2202 | .enable_mask = BIT(0), | |
2203 | .hw.init = &(struct clk_init_data){ | |
2204 | .name = "camss_csi2phytimer_clk", | |
2205 | .parent_names = (const char *[]){ "csi2phytimer_clk_src" }, | |
2206 | .num_parents = 1, | |
2207 | .flags = CLK_SET_RATE_PARENT, | |
2208 | .ops = &clk_branch2_ops, | |
2209 | }, | |
2210 | }, | |
2211 | }; | |
2212 | ||
2213 | static struct clk_branch camss_csiphy0_3p_clk = { | |
2214 | .halt_reg = 0x3234, | |
2215 | .clkr = { | |
2216 | .enable_reg = 0x3234, | |
2217 | .enable_mask = BIT(0), | |
2218 | .hw.init = &(struct clk_init_data){ | |
2219 | .name = "camss_csiphy0_3p_clk", | |
2220 | .parent_names = (const char *[]){ "csiphy0_3p_clk_src" }, | |
2221 | .num_parents = 1, | |
2222 | .flags = CLK_SET_RATE_PARENT, | |
2223 | .ops = &clk_branch2_ops, | |
2224 | }, | |
2225 | }, | |
2226 | }; | |
2227 | ||
2228 | static struct clk_branch camss_csiphy1_3p_clk = { | |
2229 | .halt_reg = 0x3254, | |
2230 | .clkr = { | |
2231 | .enable_reg = 0x3254, | |
2232 | .enable_mask = BIT(0), | |
2233 | .hw.init = &(struct clk_init_data){ | |
2234 | .name = "camss_csiphy1_3p_clk", | |
2235 | .parent_names = (const char *[]){ "csiphy1_3p_clk_src" }, | |
2236 | .num_parents = 1, | |
2237 | .flags = CLK_SET_RATE_PARENT, | |
2238 | .ops = &clk_branch2_ops, | |
2239 | }, | |
2240 | }, | |
2241 | }; | |
2242 | ||
2243 | static struct clk_branch camss_csiphy2_3p_clk = { | |
2244 | .halt_reg = 0x3274, | |
2245 | .clkr = { | |
2246 | .enable_reg = 0x3274, | |
2247 | .enable_mask = BIT(0), | |
2248 | .hw.init = &(struct clk_init_data){ | |
2249 | .name = "camss_csiphy2_3p_clk", | |
2250 | .parent_names = (const char *[]){ "csiphy2_3p_clk_src" }, | |
2251 | .num_parents = 1, | |
2252 | .flags = CLK_SET_RATE_PARENT, | |
2253 | .ops = &clk_branch2_ops, | |
2254 | }, | |
2255 | }, | |
2256 | }; | |
2257 | ||
2258 | static struct clk_branch camss_jpeg0_clk = { | |
2259 | .halt_reg = 0x35a8, | |
2260 | .clkr = { | |
2261 | .enable_reg = 0x35a8, | |
2262 | .enable_mask = BIT(0), | |
2263 | .hw.init = &(struct clk_init_data){ | |
2264 | .name = "camss_jpeg0_clk", | |
2265 | .parent_names = (const char *[]){ "jpeg0_clk_src" }, | |
2266 | .num_parents = 1, | |
2267 | .flags = CLK_SET_RATE_PARENT, | |
2268 | .ops = &clk_branch2_ops, | |
2269 | }, | |
2270 | }, | |
2271 | }; | |
2272 | ||
2273 | static struct clk_branch camss_jpeg2_clk = { | |
2274 | .halt_reg = 0x35b0, | |
2275 | .clkr = { | |
2276 | .enable_reg = 0x35b0, | |
2277 | .enable_mask = BIT(0), | |
2278 | .hw.init = &(struct clk_init_data){ | |
2279 | .name = "camss_jpeg2_clk", | |
2280 | .parent_names = (const char *[]){ "jpeg2_clk_src" }, | |
2281 | .num_parents = 1, | |
2282 | .flags = CLK_SET_RATE_PARENT, | |
2283 | .ops = &clk_branch2_ops, | |
2284 | }, | |
2285 | }, | |
2286 | }; | |
2287 | ||
2288 | static struct clk_branch camss_jpeg_dma_clk = { | |
2289 | .halt_reg = 0x35c0, | |
2290 | .clkr = { | |
2291 | .enable_reg = 0x35c0, | |
2292 | .enable_mask = BIT(0), | |
2293 | .hw.init = &(struct clk_init_data){ | |
2294 | .name = "camss_jpeg_dma_clk", | |
2295 | .parent_names = (const char *[]){ "jpeg_dma_clk_src" }, | |
2296 | .num_parents = 1, | |
2297 | .flags = CLK_SET_RATE_PARENT, | |
2298 | .ops = &clk_branch2_ops, | |
2299 | }, | |
2300 | }, | |
2301 | }; | |
2302 | ||
2303 | static struct clk_branch camss_jpeg_ahb_clk = { | |
2304 | .halt_reg = 0x35b4, | |
2305 | .clkr = { | |
2306 | .enable_reg = 0x35b4, | |
2307 | .enable_mask = BIT(0), | |
2308 | .hw.init = &(struct clk_init_data){ | |
2309 | .name = "camss_jpeg_ahb_clk", | |
2310 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
2311 | .num_parents = 1, | |
2312 | .flags = CLK_SET_RATE_PARENT, | |
2313 | .ops = &clk_branch2_ops, | |
2314 | }, | |
2315 | }, | |
2316 | }; | |
2317 | ||
2318 | static struct clk_branch camss_jpeg_axi_clk = { | |
2319 | .halt_reg = 0x35b8, | |
2320 | .clkr = { | |
2321 | .enable_reg = 0x35b8, | |
2322 | .enable_mask = BIT(0), | |
2323 | .hw.init = &(struct clk_init_data){ | |
2324 | .name = "camss_jpeg_axi_clk", | |
2325 | .parent_names = (const char *[]){ "axi_clk_src" }, | |
2326 | .num_parents = 1, | |
2327 | .flags = CLK_SET_RATE_PARENT, | |
2328 | .ops = &clk_branch2_ops, | |
2329 | }, | |
2330 | }, | |
2331 | }; | |
2332 | ||
2333 | static struct clk_branch camss_vfe_ahb_clk = { | |
2334 | .halt_reg = 0x36b8, | |
2335 | .clkr = { | |
2336 | .enable_reg = 0x36b8, | |
2337 | .enable_mask = BIT(0), | |
2338 | .hw.init = &(struct clk_init_data){ | |
2339 | .name = "camss_vfe_ahb_clk", | |
2340 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
2341 | .num_parents = 1, | |
2342 | .flags = CLK_SET_RATE_PARENT, | |
2343 | .ops = &clk_branch2_ops, | |
2344 | }, | |
2345 | }, | |
2346 | }; | |
2347 | ||
2348 | static struct clk_branch camss_vfe_axi_clk = { | |
2349 | .halt_reg = 0x36bc, | |
2350 | .clkr = { | |
2351 | .enable_reg = 0x36bc, | |
2352 | .enable_mask = BIT(0), | |
2353 | .hw.init = &(struct clk_init_data){ | |
2354 | .name = "camss_vfe_axi_clk", | |
2355 | .parent_names = (const char *[]){ "axi_clk_src" }, | |
2356 | .num_parents = 1, | |
2357 | .flags = CLK_SET_RATE_PARENT, | |
2358 | .ops = &clk_branch2_ops, | |
2359 | }, | |
2360 | }, | |
2361 | }; | |
2362 | ||
2363 | static struct clk_branch camss_vfe0_clk = { | |
2364 | .halt_reg = 0x36a8, | |
2365 | .clkr = { | |
2366 | .enable_reg = 0x36a8, | |
2367 | .enable_mask = BIT(0), | |
2368 | .hw.init = &(struct clk_init_data){ | |
2369 | .name = "camss_vfe0_clk", | |
2370 | .parent_names = (const char *[]){ "vfe0_clk_src" }, | |
2371 | .num_parents = 1, | |
2372 | .flags = CLK_SET_RATE_PARENT, | |
2373 | .ops = &clk_branch2_ops, | |
2374 | }, | |
2375 | }, | |
2376 | }; | |
2377 | ||
2378 | static struct clk_branch camss_vfe0_stream_clk = { | |
2379 | .halt_reg = 0x3720, | |
2380 | .clkr = { | |
2381 | .enable_reg = 0x3720, | |
2382 | .enable_mask = BIT(0), | |
2383 | .hw.init = &(struct clk_init_data){ | |
2384 | .name = "camss_vfe0_stream_clk", | |
2385 | .parent_names = (const char *[]){ "vfe0_clk_src" }, | |
2386 | .num_parents = 1, | |
2387 | .flags = CLK_SET_RATE_PARENT, | |
2388 | .ops = &clk_branch2_ops, | |
2389 | }, | |
2390 | }, | |
2391 | }; | |
2392 | ||
2393 | static struct clk_branch camss_vfe0_ahb_clk = { | |
2394 | .halt_reg = 0x3668, | |
2395 | .clkr = { | |
2396 | .enable_reg = 0x3668, | |
2397 | .enable_mask = BIT(0), | |
2398 | .hw.init = &(struct clk_init_data){ | |
2399 | .name = "camss_vfe0_ahb_clk", | |
2400 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
2401 | .num_parents = 1, | |
2402 | .flags = CLK_SET_RATE_PARENT, | |
2403 | .ops = &clk_branch2_ops, | |
2404 | }, | |
2405 | }, | |
2406 | }; | |
2407 | ||
2408 | static struct clk_branch camss_vfe1_clk = { | |
2409 | .halt_reg = 0x36ac, | |
2410 | .clkr = { | |
2411 | .enable_reg = 0x36ac, | |
2412 | .enable_mask = BIT(0), | |
2413 | .hw.init = &(struct clk_init_data){ | |
2414 | .name = "camss_vfe1_clk", | |
2415 | .parent_names = (const char *[]){ "vfe1_clk_src" }, | |
2416 | .num_parents = 1, | |
2417 | .flags = CLK_SET_RATE_PARENT, | |
2418 | .ops = &clk_branch2_ops, | |
2419 | }, | |
2420 | }, | |
2421 | }; | |
2422 | ||
2423 | static struct clk_branch camss_vfe1_stream_clk = { | |
2424 | .halt_reg = 0x3724, | |
2425 | .clkr = { | |
2426 | .enable_reg = 0x3724, | |
2427 | .enable_mask = BIT(0), | |
2428 | .hw.init = &(struct clk_init_data){ | |
2429 | .name = "camss_vfe1_stream_clk", | |
2430 | .parent_names = (const char *[]){ "vfe1_clk_src" }, | |
2431 | .num_parents = 1, | |
2432 | .flags = CLK_SET_RATE_PARENT, | |
2433 | .ops = &clk_branch2_ops, | |
2434 | }, | |
2435 | }, | |
2436 | }; | |
2437 | ||
2438 | static struct clk_branch camss_vfe1_ahb_clk = { | |
2439 | .halt_reg = 0x3678, | |
2440 | .clkr = { | |
2441 | .enable_reg = 0x3678, | |
2442 | .enable_mask = BIT(0), | |
2443 | .hw.init = &(struct clk_init_data){ | |
2444 | .name = "camss_vfe1_ahb_clk", | |
2445 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
2446 | .num_parents = 1, | |
2447 | .flags = CLK_SET_RATE_PARENT, | |
2448 | .ops = &clk_branch2_ops, | |
2449 | }, | |
2450 | }, | |
2451 | }; | |
2452 | ||
2453 | static struct clk_branch camss_csi_vfe0_clk = { | |
2454 | .halt_reg = 0x3704, | |
2455 | .clkr = { | |
2456 | .enable_reg = 0x3704, | |
2457 | .enable_mask = BIT(0), | |
2458 | .hw.init = &(struct clk_init_data){ | |
2459 | .name = "camss_csi_vfe0_clk", | |
2460 | .parent_names = (const char *[]){ "vfe0_clk_src" }, | |
2461 | .num_parents = 1, | |
2462 | .flags = CLK_SET_RATE_PARENT, | |
2463 | .ops = &clk_branch2_ops, | |
2464 | }, | |
2465 | }, | |
2466 | }; | |
2467 | ||
2468 | static struct clk_branch camss_csi_vfe1_clk = { | |
2469 | .halt_reg = 0x3714, | |
2470 | .clkr = { | |
2471 | .enable_reg = 0x3714, | |
2472 | .enable_mask = BIT(0), | |
2473 | .hw.init = &(struct clk_init_data){ | |
2474 | .name = "camss_csi_vfe1_clk", | |
2475 | .parent_names = (const char *[]){ "vfe1_clk_src" }, | |
2476 | .num_parents = 1, | |
2477 | .flags = CLK_SET_RATE_PARENT, | |
2478 | .ops = &clk_branch2_ops, | |
2479 | }, | |
2480 | }, | |
2481 | }; | |
2482 | ||
2483 | static struct clk_branch camss_cpp_vbif_ahb_clk = { | |
2484 | .halt_reg = 0x36c8, | |
2485 | .clkr = { | |
2486 | .enable_reg = 0x36c8, | |
2487 | .enable_mask = BIT(0), | |
2488 | .hw.init = &(struct clk_init_data){ | |
2489 | .name = "camss_cpp_vbif_ahb_clk", | |
2490 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
2491 | .num_parents = 1, | |
2492 | .flags = CLK_SET_RATE_PARENT, | |
2493 | .ops = &clk_branch2_ops, | |
2494 | }, | |
2495 | }, | |
2496 | }; | |
2497 | ||
2498 | static struct clk_branch camss_cpp_axi_clk = { | |
2499 | .halt_reg = 0x36c4, | |
2500 | .clkr = { | |
2501 | .enable_reg = 0x36c4, | |
2502 | .enable_mask = BIT(0), | |
2503 | .hw.init = &(struct clk_init_data){ | |
2504 | .name = "camss_cpp_axi_clk", | |
2505 | .parent_names = (const char *[]){ "axi_clk_src" }, | |
2506 | .num_parents = 1, | |
2507 | .flags = CLK_SET_RATE_PARENT, | |
2508 | .ops = &clk_branch2_ops, | |
2509 | }, | |
2510 | }, | |
2511 | }; | |
2512 | ||
2513 | static struct clk_branch camss_cpp_clk = { | |
2514 | .halt_reg = 0x36b0, | |
2515 | .clkr = { | |
2516 | .enable_reg = 0x36b0, | |
2517 | .enable_mask = BIT(0), | |
2518 | .hw.init = &(struct clk_init_data){ | |
2519 | .name = "camss_cpp_clk", | |
2520 | .parent_names = (const char *[]){ "cpp_clk_src" }, | |
2521 | .num_parents = 1, | |
2522 | .flags = CLK_SET_RATE_PARENT, | |
2523 | .ops = &clk_branch2_ops, | |
2524 | }, | |
2525 | }, | |
2526 | }; | |
2527 | ||
2528 | static struct clk_branch camss_cpp_ahb_clk = { | |
2529 | .halt_reg = 0x36b4, | |
2530 | .clkr = { | |
2531 | .enable_reg = 0x36b4, | |
2532 | .enable_mask = BIT(0), | |
2533 | .hw.init = &(struct clk_init_data){ | |
2534 | .name = "camss_cpp_ahb_clk", | |
2535 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
2536 | .num_parents = 1, | |
2537 | .flags = CLK_SET_RATE_PARENT, | |
2538 | .ops = &clk_branch2_ops, | |
2539 | }, | |
2540 | }, | |
2541 | }; | |
2542 | ||
2543 | static struct clk_branch camss_csi0_clk = { | |
2544 | .halt_reg = 0x30b4, | |
2545 | .clkr = { | |
2546 | .enable_reg = 0x30b4, | |
2547 | .enable_mask = BIT(0), | |
2548 | .hw.init = &(struct clk_init_data){ | |
2549 | .name = "camss_csi0_clk", | |
2550 | .parent_names = (const char *[]){ "csi0_clk_src" }, | |
2551 | .num_parents = 1, | |
2552 | .flags = CLK_SET_RATE_PARENT, | |
2553 | .ops = &clk_branch2_ops, | |
2554 | }, | |
2555 | }, | |
2556 | }; | |
2557 | ||
2558 | static struct clk_branch camss_csi0_ahb_clk = { | |
2559 | .halt_reg = 0x30bc, | |
2560 | .clkr = { | |
2561 | .enable_reg = 0x30bc, | |
2562 | .enable_mask = BIT(0), | |
2563 | .hw.init = &(struct clk_init_data){ | |
2564 | .name = "camss_csi0_ahb_clk", | |
2565 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
2566 | .num_parents = 1, | |
2567 | .flags = CLK_SET_RATE_PARENT, | |
2568 | .ops = &clk_branch2_ops, | |
2569 | }, | |
2570 | }, | |
2571 | }; | |
2572 | ||
2573 | static struct clk_branch camss_csi0phy_clk = { | |
2574 | .halt_reg = 0x30c4, | |
2575 | .clkr = { | |
2576 | .enable_reg = 0x30c4, | |
2577 | .enable_mask = BIT(0), | |
2578 | .hw.init = &(struct clk_init_data){ | |
2579 | .name = "camss_csi0phy_clk", | |
2580 | .parent_names = (const char *[]){ "csi0_clk_src" }, | |
2581 | .num_parents = 1, | |
2582 | .flags = CLK_SET_RATE_PARENT, | |
2583 | .ops = &clk_branch2_ops, | |
2584 | }, | |
2585 | }, | |
2586 | }; | |
2587 | ||
2588 | static struct clk_branch camss_csi0rdi_clk = { | |
2589 | .halt_reg = 0x30d4, | |
2590 | .clkr = { | |
2591 | .enable_reg = 0x30d4, | |
2592 | .enable_mask = BIT(0), | |
2593 | .hw.init = &(struct clk_init_data){ | |
2594 | .name = "camss_csi0rdi_clk", | |
2595 | .parent_names = (const char *[]){ "csi0_clk_src" }, | |
2596 | .num_parents = 1, | |
2597 | .flags = CLK_SET_RATE_PARENT, | |
2598 | .ops = &clk_branch2_ops, | |
2599 | }, | |
2600 | }, | |
2601 | }; | |
2602 | ||
2603 | static struct clk_branch camss_csi0pix_clk = { | |
2604 | .halt_reg = 0x30e4, | |
2605 | .clkr = { | |
2606 | .enable_reg = 0x30e4, | |
2607 | .enable_mask = BIT(0), | |
2608 | .hw.init = &(struct clk_init_data){ | |
2609 | .name = "camss_csi0pix_clk", | |
2610 | .parent_names = (const char *[]){ "csi0_clk_src" }, | |
2611 | .num_parents = 1, | |
2612 | .flags = CLK_SET_RATE_PARENT, | |
2613 | .ops = &clk_branch2_ops, | |
2614 | }, | |
2615 | }, | |
2616 | }; | |
2617 | ||
2618 | static struct clk_branch camss_csi1_clk = { | |
2619 | .halt_reg = 0x3124, | |
2620 | .clkr = { | |
2621 | .enable_reg = 0x3124, | |
2622 | .enable_mask = BIT(0), | |
2623 | .hw.init = &(struct clk_init_data){ | |
2624 | .name = "camss_csi1_clk", | |
2625 | .parent_names = (const char *[]){ "csi1_clk_src" }, | |
2626 | .num_parents = 1, | |
2627 | .flags = CLK_SET_RATE_PARENT, | |
2628 | .ops = &clk_branch2_ops, | |
2629 | }, | |
2630 | }, | |
2631 | }; | |
2632 | ||
2633 | static struct clk_branch camss_csi1_ahb_clk = { | |
2634 | .halt_reg = 0x3128, | |
2635 | .clkr = { | |
2636 | .enable_reg = 0x3128, | |
2637 | .enable_mask = BIT(0), | |
2638 | .hw.init = &(struct clk_init_data){ | |
2639 | .name = "camss_csi1_ahb_clk", | |
2640 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
2641 | .num_parents = 1, | |
2642 | .flags = CLK_SET_RATE_PARENT, | |
2643 | .ops = &clk_branch2_ops, | |
2644 | }, | |
2645 | }, | |
2646 | }; | |
2647 | ||
2648 | static struct clk_branch camss_csi1phy_clk = { | |
2649 | .halt_reg = 0x3134, | |
2650 | .clkr = { | |
2651 | .enable_reg = 0x3134, | |
2652 | .enable_mask = BIT(0), | |
2653 | .hw.init = &(struct clk_init_data){ | |
2654 | .name = "camss_csi1phy_clk", | |
2655 | .parent_names = (const char *[]){ "csi1_clk_src" }, | |
2656 | .num_parents = 1, | |
2657 | .flags = CLK_SET_RATE_PARENT, | |
2658 | .ops = &clk_branch2_ops, | |
2659 | }, | |
2660 | }, | |
2661 | }; | |
2662 | ||
2663 | static struct clk_branch camss_csi1rdi_clk = { | |
2664 | .halt_reg = 0x3144, | |
2665 | .clkr = { | |
2666 | .enable_reg = 0x3144, | |
2667 | .enable_mask = BIT(0), | |
2668 | .hw.init = &(struct clk_init_data){ | |
2669 | .name = "camss_csi1rdi_clk", | |
2670 | .parent_names = (const char *[]){ "csi1_clk_src" }, | |
2671 | .num_parents = 1, | |
2672 | .flags = CLK_SET_RATE_PARENT, | |
2673 | .ops = &clk_branch2_ops, | |
2674 | }, | |
2675 | }, | |
2676 | }; | |
2677 | ||
2678 | static struct clk_branch camss_csi1pix_clk = { | |
2679 | .halt_reg = 0x3154, | |
2680 | .clkr = { | |
2681 | .enable_reg = 0x3154, | |
2682 | .enable_mask = BIT(0), | |
2683 | .hw.init = &(struct clk_init_data){ | |
2684 | .name = "camss_csi1pix_clk", | |
2685 | .parent_names = (const char *[]){ "csi1_clk_src" }, | |
2686 | .num_parents = 1, | |
2687 | .flags = CLK_SET_RATE_PARENT, | |
2688 | .ops = &clk_branch2_ops, | |
2689 | }, | |
2690 | }, | |
2691 | }; | |
2692 | ||
2693 | static struct clk_branch camss_csi2_clk = { | |
2694 | .halt_reg = 0x3184, | |
2695 | .clkr = { | |
2696 | .enable_reg = 0x3184, | |
2697 | .enable_mask = BIT(0), | |
2698 | .hw.init = &(struct clk_init_data){ | |
2699 | .name = "camss_csi2_clk", | |
2700 | .parent_names = (const char *[]){ "csi2_clk_src" }, | |
2701 | .num_parents = 1, | |
2702 | .flags = CLK_SET_RATE_PARENT, | |
2703 | .ops = &clk_branch2_ops, | |
2704 | }, | |
2705 | }, | |
2706 | }; | |
2707 | ||
2708 | static struct clk_branch camss_csi2_ahb_clk = { | |
2709 | .halt_reg = 0x3188, | |
2710 | .clkr = { | |
2711 | .enable_reg = 0x3188, | |
2712 | .enable_mask = BIT(0), | |
2713 | .hw.init = &(struct clk_init_data){ | |
2714 | .name = "camss_csi2_ahb_clk", | |
2715 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
2716 | .num_parents = 1, | |
2717 | .flags = CLK_SET_RATE_PARENT, | |
2718 | .ops = &clk_branch2_ops, | |
2719 | }, | |
2720 | }, | |
2721 | }; | |
2722 | ||
2723 | static struct clk_branch camss_csi2phy_clk = { | |
2724 | .halt_reg = 0x3194, | |
2725 | .clkr = { | |
2726 | .enable_reg = 0x3194, | |
2727 | .enable_mask = BIT(0), | |
2728 | .hw.init = &(struct clk_init_data){ | |
2729 | .name = "camss_csi2phy_clk", | |
2730 | .parent_names = (const char *[]){ "csi2_clk_src" }, | |
2731 | .num_parents = 1, | |
2732 | .flags = CLK_SET_RATE_PARENT, | |
2733 | .ops = &clk_branch2_ops, | |
2734 | }, | |
2735 | }, | |
2736 | }; | |
2737 | ||
2738 | static struct clk_branch camss_csi2rdi_clk = { | |
2739 | .halt_reg = 0x31a4, | |
2740 | .clkr = { | |
2741 | .enable_reg = 0x31a4, | |
2742 | .enable_mask = BIT(0), | |
2743 | .hw.init = &(struct clk_init_data){ | |
2744 | .name = "camss_csi2rdi_clk", | |
2745 | .parent_names = (const char *[]){ "csi2_clk_src" }, | |
2746 | .num_parents = 1, | |
2747 | .flags = CLK_SET_RATE_PARENT, | |
2748 | .ops = &clk_branch2_ops, | |
2749 | }, | |
2750 | }, | |
2751 | }; | |
2752 | ||
2753 | static struct clk_branch camss_csi2pix_clk = { | |
2754 | .halt_reg = 0x31b4, | |
2755 | .clkr = { | |
2756 | .enable_reg = 0x31b4, | |
2757 | .enable_mask = BIT(0), | |
2758 | .hw.init = &(struct clk_init_data){ | |
2759 | .name = "camss_csi2pix_clk", | |
2760 | .parent_names = (const char *[]){ "csi2_clk_src" }, | |
2761 | .num_parents = 1, | |
2762 | .flags = CLK_SET_RATE_PARENT, | |
2763 | .ops = &clk_branch2_ops, | |
2764 | }, | |
2765 | }, | |
2766 | }; | |
2767 | ||
2768 | static struct clk_branch camss_csi3_clk = { | |
2769 | .halt_reg = 0x31e4, | |
2770 | .clkr = { | |
2771 | .enable_reg = 0x31e4, | |
2772 | .enable_mask = BIT(0), | |
2773 | .hw.init = &(struct clk_init_data){ | |
2774 | .name = "camss_csi3_clk", | |
2775 | .parent_names = (const char *[]){ "csi3_clk_src" }, | |
2776 | .num_parents = 1, | |
2777 | .flags = CLK_SET_RATE_PARENT, | |
2778 | .ops = &clk_branch2_ops, | |
2779 | }, | |
2780 | }, | |
2781 | }; | |
2782 | ||
2783 | static struct clk_branch camss_csi3_ahb_clk = { | |
2784 | .halt_reg = 0x31e8, | |
2785 | .clkr = { | |
2786 | .enable_reg = 0x31e8, | |
2787 | .enable_mask = BIT(0), | |
2788 | .hw.init = &(struct clk_init_data){ | |
2789 | .name = "camss_csi3_ahb_clk", | |
2790 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
2791 | .num_parents = 1, | |
2792 | .flags = CLK_SET_RATE_PARENT, | |
2793 | .ops = &clk_branch2_ops, | |
2794 | }, | |
2795 | }, | |
2796 | }; | |
2797 | ||
2798 | static struct clk_branch camss_csi3phy_clk = { | |
2799 | .halt_reg = 0x31f4, | |
2800 | .clkr = { | |
2801 | .enable_reg = 0x31f4, | |
2802 | .enable_mask = BIT(0), | |
2803 | .hw.init = &(struct clk_init_data){ | |
2804 | .name = "camss_csi3phy_clk", | |
2805 | .parent_names = (const char *[]){ "csi3_clk_src" }, | |
2806 | .num_parents = 1, | |
2807 | .flags = CLK_SET_RATE_PARENT, | |
2808 | .ops = &clk_branch2_ops, | |
2809 | }, | |
2810 | }, | |
2811 | }; | |
2812 | ||
2813 | static struct clk_branch camss_csi3rdi_clk = { | |
2814 | .halt_reg = 0x3204, | |
2815 | .clkr = { | |
2816 | .enable_reg = 0x3204, | |
2817 | .enable_mask = BIT(0), | |
2818 | .hw.init = &(struct clk_init_data){ | |
2819 | .name = "camss_csi3rdi_clk", | |
2820 | .parent_names = (const char *[]){ "csi3_clk_src" }, | |
2821 | .num_parents = 1, | |
2822 | .flags = CLK_SET_RATE_PARENT, | |
2823 | .ops = &clk_branch2_ops, | |
2824 | }, | |
2825 | }, | |
2826 | }; | |
2827 | ||
2828 | static struct clk_branch camss_csi3pix_clk = { | |
2829 | .halt_reg = 0x3214, | |
2830 | .clkr = { | |
2831 | .enable_reg = 0x3214, | |
2832 | .enable_mask = BIT(0), | |
2833 | .hw.init = &(struct clk_init_data){ | |
2834 | .name = "camss_csi3pix_clk", | |
2835 | .parent_names = (const char *[]){ "csi3_clk_src" }, | |
2836 | .num_parents = 1, | |
2837 | .flags = CLK_SET_RATE_PARENT, | |
2838 | .ops = &clk_branch2_ops, | |
2839 | }, | |
2840 | }, | |
2841 | }; | |
2842 | ||
2843 | static struct clk_branch camss_ispif_ahb_clk = { | |
2844 | .halt_reg = 0x3224, | |
2845 | .clkr = { | |
2846 | .enable_reg = 0x3224, | |
2847 | .enable_mask = BIT(0), | |
2848 | .hw.init = &(struct clk_init_data){ | |
2849 | .name = "camss_ispif_ahb_clk", | |
2850 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
2851 | .num_parents = 1, | |
2852 | .flags = CLK_SET_RATE_PARENT, | |
2853 | .ops = &clk_branch2_ops, | |
2854 | }, | |
2855 | }, | |
2856 | }; | |
2857 | ||
2858 | static struct clk_branch fd_core_clk = { | |
2859 | .halt_reg = 0x3b68, | |
2860 | .clkr = { | |
2861 | .enable_reg = 0x3b68, | |
2862 | .enable_mask = BIT(0), | |
2863 | .hw.init = &(struct clk_init_data){ | |
2864 | .name = "fd_core_clk", | |
2865 | .parent_names = (const char *[]){ "fd_core_clk_src" }, | |
2866 | .num_parents = 1, | |
2867 | .flags = CLK_SET_RATE_PARENT, | |
2868 | .ops = &clk_branch2_ops, | |
2869 | }, | |
2870 | }, | |
2871 | }; | |
2872 | ||
2873 | static struct clk_branch fd_core_uar_clk = { | |
2874 | .halt_reg = 0x3b6c, | |
2875 | .clkr = { | |
2876 | .enable_reg = 0x3b6c, | |
2877 | .enable_mask = BIT(0), | |
2878 | .hw.init = &(struct clk_init_data){ | |
2879 | .name = "fd_core_uar_clk", | |
2880 | .parent_names = (const char *[]){ "fd_core_clk_src" }, | |
2881 | .num_parents = 1, | |
2882 | .flags = CLK_SET_RATE_PARENT, | |
2883 | .ops = &clk_branch2_ops, | |
2884 | }, | |
2885 | }, | |
2886 | }; | |
2887 | ||
2888 | static struct clk_branch fd_ahb_clk = { | |
2889 | .halt_reg = 0x3ba74, | |
2890 | .clkr = { | |
2891 | .enable_reg = 0x3ba74, | |
2892 | .enable_mask = BIT(0), | |
2893 | .hw.init = &(struct clk_init_data){ | |
2894 | .name = "fd_ahb_clk", | |
2895 | .parent_names = (const char *[]){ "ahb_clk_src" }, | |
2896 | .num_parents = 1, | |
2897 | .flags = CLK_SET_RATE_PARENT, | |
2898 | .ops = &clk_branch2_ops, | |
2899 | }, | |
2900 | }, | |
2901 | }; | |
2902 | ||
2903 | static struct clk_hw *mmcc_msm8996_hws[] = { | |
2904 | &gpll0_div.hw, | |
2905 | }; | |
2906 | ||
63bb4fd6 RN |
2907 | static struct gdsc mmagic_bimc_gdsc = { |
2908 | .gdscr = 0x529c, | |
2909 | .pd = { | |
2910 | .name = "mmagic_bimc", | |
2911 | }, | |
2912 | .pwrsts = PWRSTS_OFF_ON, | |
2913 | }; | |
2914 | ||
7e824d50 RN |
2915 | static struct gdsc mmagic_video_gdsc = { |
2916 | .gdscr = 0x119c, | |
2917 | .gds_hw_ctrl = 0x120c, | |
2918 | .pd = { | |
2919 | .name = "mmagic_video", | |
2920 | }, | |
2921 | .pwrsts = PWRSTS_OFF_ON, | |
2922 | .flags = VOTABLE, | |
2923 | }; | |
2924 | ||
2925 | static struct gdsc mmagic_mdss_gdsc = { | |
2926 | .gdscr = 0x247c, | |
2927 | .gds_hw_ctrl = 0x2480, | |
2928 | .pd = { | |
2929 | .name = "mmagic_mdss", | |
2930 | }, | |
2931 | .pwrsts = PWRSTS_OFF_ON, | |
2932 | .flags = VOTABLE, | |
2933 | }; | |
2934 | ||
2935 | static struct gdsc mmagic_camss_gdsc = { | |
2936 | .gdscr = 0x3c4c, | |
2937 | .gds_hw_ctrl = 0x3c50, | |
2938 | .pd = { | |
2939 | .name = "mmagic_camss", | |
2940 | }, | |
2941 | .pwrsts = PWRSTS_OFF_ON, | |
2942 | .flags = VOTABLE, | |
2943 | }; | |
2944 | ||
2945 | static struct gdsc venus_gdsc = { | |
2946 | .gdscr = 0x1024, | |
2947 | .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 }, | |
2948 | .cxc_count = 3, | |
2949 | .pd = { | |
2950 | .name = "venus", | |
2951 | }, | |
2952 | .parent = &mmagic_video_gdsc.pd, | |
2953 | .pwrsts = PWRSTS_OFF_ON, | |
2954 | }; | |
2955 | ||
2956 | static struct gdsc venus_core0_gdsc = { | |
2957 | .gdscr = 0x1040, | |
2958 | .cxcs = (unsigned int []){ 0x1048 }, | |
2959 | .cxc_count = 1, | |
2960 | .pd = { | |
2961 | .name = "venus_core0", | |
2962 | }, | |
4a43e35d | 2963 | .parent = &venus_gdsc.pd, |
7e824d50 | 2964 | .pwrsts = PWRSTS_OFF_ON, |
96893e10 | 2965 | .flags = HW_CTRL, |
7e824d50 RN |
2966 | }; |
2967 | ||
2968 | static struct gdsc venus_core1_gdsc = { | |
2969 | .gdscr = 0x1044, | |
2970 | .cxcs = (unsigned int []){ 0x104c }, | |
2971 | .cxc_count = 1, | |
2972 | .pd = { | |
2973 | .name = "venus_core1", | |
2974 | }, | |
4a43e35d | 2975 | .parent = &venus_gdsc.pd, |
7e824d50 | 2976 | .pwrsts = PWRSTS_OFF_ON, |
96893e10 | 2977 | .flags = HW_CTRL, |
7e824d50 RN |
2978 | }; |
2979 | ||
2980 | static struct gdsc camss_gdsc = { | |
2981 | .gdscr = 0x34a0, | |
2982 | .cxcs = (unsigned int []){ 0x36bc, 0x36c4 }, | |
2983 | .cxc_count = 2, | |
2984 | .pd = { | |
2985 | .name = "camss", | |
2986 | }, | |
2987 | .parent = &mmagic_camss_gdsc.pd, | |
2988 | .pwrsts = PWRSTS_OFF_ON, | |
2989 | }; | |
2990 | ||
2991 | static struct gdsc vfe0_gdsc = { | |
2992 | .gdscr = 0x3664, | |
2993 | .cxcs = (unsigned int []){ 0x36a8 }, | |
2994 | .cxc_count = 1, | |
2995 | .pd = { | |
2996 | .name = "vfe0", | |
2997 | }, | |
2998 | .parent = &camss_gdsc.pd, | |
2999 | .pwrsts = PWRSTS_OFF_ON, | |
3000 | }; | |
3001 | ||
3002 | static struct gdsc vfe1_gdsc = { | |
3003 | .gdscr = 0x3674, | |
3004 | .cxcs = (unsigned int []){ 0x36ac }, | |
3005 | .cxc_count = 1, | |
3006 | .pd = { | |
a62ca337 | 3007 | .name = "vfe1", |
7e824d50 RN |
3008 | }, |
3009 | .parent = &camss_gdsc.pd, | |
3010 | .pwrsts = PWRSTS_OFF_ON, | |
3011 | }; | |
3012 | ||
3013 | static struct gdsc jpeg_gdsc = { | |
3014 | .gdscr = 0x35a4, | |
3015 | .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 }, | |
3016 | .cxc_count = 4, | |
3017 | .pd = { | |
3018 | .name = "jpeg", | |
3019 | }, | |
3020 | .parent = &camss_gdsc.pd, | |
3021 | .pwrsts = PWRSTS_OFF_ON, | |
3022 | }; | |
3023 | ||
3024 | static struct gdsc cpp_gdsc = { | |
3025 | .gdscr = 0x36d4, | |
3026 | .cxcs = (unsigned int []){ 0x36b0 }, | |
3027 | .cxc_count = 1, | |
3028 | .pd = { | |
3029 | .name = "cpp", | |
3030 | }, | |
3031 | .parent = &camss_gdsc.pd, | |
3032 | .pwrsts = PWRSTS_OFF_ON, | |
3033 | }; | |
3034 | ||
3035 | static struct gdsc fd_gdsc = { | |
3036 | .gdscr = 0x3b64, | |
3037 | .cxcs = (unsigned int []){ 0x3b68, 0x3b6c }, | |
3038 | .cxc_count = 2, | |
3039 | .pd = { | |
3040 | .name = "fd", | |
3041 | }, | |
3042 | .parent = &camss_gdsc.pd, | |
3043 | .pwrsts = PWRSTS_OFF_ON, | |
3044 | }; | |
3045 | ||
3046 | static struct gdsc mdss_gdsc = { | |
3047 | .gdscr = 0x2304, | |
3048 | .cxcs = (unsigned int []){ 0x2310, 0x231c }, | |
3049 | .cxc_count = 2, | |
3050 | .pd = { | |
3051 | .name = "mdss", | |
3052 | }, | |
3053 | .parent = &mmagic_mdss_gdsc.pd, | |
3054 | .pwrsts = PWRSTS_OFF_ON, | |
3055 | }; | |
3056 | ||
4154f619 RN |
3057 | static struct gdsc gpu_gdsc = { |
3058 | .gdscr = 0x4034, | |
3059 | .gds_hw_ctrl = 0x4038, | |
3060 | .pd = { | |
3061 | .name = "gpu", | |
3062 | }, | |
3063 | .pwrsts = PWRSTS_OFF_ON, | |
3064 | .flags = VOTABLE, | |
3065 | }; | |
3066 | ||
3067 | static struct gdsc gpu_gx_gdsc = { | |
3068 | .gdscr = 0x4024, | |
3069 | .clamp_io_ctrl = 0x4300, | |
3070 | .cxcs = (unsigned int []){ 0x4028 }, | |
3071 | .cxc_count = 1, | |
3072 | .pd = { | |
3073 | .name = "gpu_gx", | |
3074 | }, | |
3075 | .pwrsts = PWRSTS_OFF_ON, | |
3076 | .flags = CLAMP_IO, | |
3077 | }; | |
3078 | ||
c2526597 SB |
3079 | static struct clk_regmap *mmcc_msm8996_clocks[] = { |
3080 | [MMPLL0_EARLY] = &mmpll0_early.clkr, | |
3081 | [MMPLL0_PLL] = &mmpll0.clkr, | |
3082 | [MMPLL1_EARLY] = &mmpll1_early.clkr, | |
3083 | [MMPLL1_PLL] = &mmpll1.clkr, | |
3084 | [MMPLL2_EARLY] = &mmpll2_early.clkr, | |
3085 | [MMPLL2_PLL] = &mmpll2.clkr, | |
3086 | [MMPLL3_EARLY] = &mmpll3_early.clkr, | |
3087 | [MMPLL3_PLL] = &mmpll3.clkr, | |
3088 | [MMPLL4_EARLY] = &mmpll4_early.clkr, | |
3089 | [MMPLL4_PLL] = &mmpll4.clkr, | |
3090 | [MMPLL5_EARLY] = &mmpll5_early.clkr, | |
3091 | [MMPLL5_PLL] = &mmpll5.clkr, | |
3092 | [MMPLL8_EARLY] = &mmpll8_early.clkr, | |
3093 | [MMPLL8_PLL] = &mmpll8.clkr, | |
3094 | [MMPLL9_EARLY] = &mmpll9_early.clkr, | |
3095 | [MMPLL9_PLL] = &mmpll9.clkr, | |
3096 | [AHB_CLK_SRC] = &ahb_clk_src.clkr, | |
3097 | [AXI_CLK_SRC] = &axi_clk_src.clkr, | |
3098 | [MAXI_CLK_SRC] = &maxi_clk_src.clkr, | |
3099 | [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, | |
3100 | [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, | |
3101 | [ISENSE_CLK_SRC] = &isense_clk_src.clkr, | |
3102 | [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, | |
3103 | [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr, | |
3104 | [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr, | |
3105 | [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr, | |
3106 | [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, | |
3107 | [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, | |
3108 | [MDP_CLK_SRC] = &mdp_clk_src.clkr, | |
3109 | [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr, | |
3110 | [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, | |
3111 | [HDMI_CLK_SRC] = &hdmi_clk_src.clkr, | |
3112 | [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, | |
3113 | [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, | |
3114 | [ESC0_CLK_SRC] = &esc0_clk_src.clkr, | |
3115 | [ESC1_CLK_SRC] = &esc1_clk_src.clkr, | |
3116 | [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, | |
3117 | [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, | |
3118 | [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, | |
3119 | [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, | |
3120 | [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, | |
3121 | [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, | |
3122 | [CCI_CLK_SRC] = &cci_clk_src.clkr, | |
3123 | [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, | |
3124 | [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, | |
3125 | [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, | |
3126 | [CSIPHY0_3P_CLK_SRC] = &csiphy0_3p_clk_src.clkr, | |
3127 | [CSIPHY1_3P_CLK_SRC] = &csiphy1_3p_clk_src.clkr, | |
3128 | [CSIPHY2_3P_CLK_SRC] = &csiphy2_3p_clk_src.clkr, | |
3129 | [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, | |
3130 | [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr, | |
3131 | [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr, | |
3132 | [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, | |
3133 | [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, | |
3134 | [CPP_CLK_SRC] = &cpp_clk_src.clkr, | |
3135 | [CSI0_CLK_SRC] = &csi0_clk_src.clkr, | |
3136 | [CSI1_CLK_SRC] = &csi1_clk_src.clkr, | |
3137 | [CSI2_CLK_SRC] = &csi2_clk_src.clkr, | |
3138 | [CSI3_CLK_SRC] = &csi3_clk_src.clkr, | |
3139 | [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr, | |
3140 | [MMSS_MMAGIC_AHB_CLK] = &mmss_mmagic_ahb_clk.clkr, | |
3141 | [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr, | |
3142 | [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, | |
3143 | [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr, | |
c2526597 SB |
3144 | [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr, |
3145 | [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr, | |
3146 | [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr, | |
3147 | [SMMU_VFE_AHB_CLK] = &smmu_vfe_ahb_clk.clkr, | |
3148 | [SMMU_VFE_AXI_CLK] = &smmu_vfe_axi_clk.clkr, | |
3149 | [SMMU_CPP_AHB_CLK] = &smmu_cpp_ahb_clk.clkr, | |
3150 | [SMMU_CPP_AXI_CLK] = &smmu_cpp_axi_clk.clkr, | |
3151 | [SMMU_JPEG_AHB_CLK] = &smmu_jpeg_ahb_clk.clkr, | |
3152 | [SMMU_JPEG_AXI_CLK] = &smmu_jpeg_axi_clk.clkr, | |
3153 | [MMAGIC_MDSS_AXI_CLK] = &mmagic_mdss_axi_clk.clkr, | |
3154 | [MMAGIC_MDSS_NOC_CFG_AHB_CLK] = &mmagic_mdss_noc_cfg_ahb_clk.clkr, | |
3155 | [SMMU_ROT_AHB_CLK] = &smmu_rot_ahb_clk.clkr, | |
3156 | [SMMU_ROT_AXI_CLK] = &smmu_rot_axi_clk.clkr, | |
3157 | [SMMU_MDP_AHB_CLK] = &smmu_mdp_ahb_clk.clkr, | |
3158 | [SMMU_MDP_AXI_CLK] = &smmu_mdp_axi_clk.clkr, | |
3159 | [MMAGIC_VIDEO_AXI_CLK] = &mmagic_video_axi_clk.clkr, | |
3160 | [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr, | |
3161 | [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr, | |
3162 | [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr, | |
c2526597 SB |
3163 | [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr, |
3164 | [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr, | |
3165 | [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr, | |
3166 | [GPU_AHB_CLK] = &gpu_ahb_clk.clkr, | |
3167 | [GPU_AON_ISENSE_CLK] = &gpu_aon_isense_clk.clkr, | |
3168 | [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr, | |
3169 | [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr, | |
3170 | [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr, | |
3171 | [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr, | |
3172 | [VIDEO_CORE_CLK] = &video_core_clk.clkr, | |
3173 | [VIDEO_AXI_CLK] = &video_axi_clk.clkr, | |
3174 | [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr, | |
3175 | [VIDEO_AHB_CLK] = &video_ahb_clk.clkr, | |
3176 | [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr, | |
3177 | [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr, | |
3178 | [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr, | |
3179 | [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr, | |
3180 | [MDSS_AXI_CLK] = &mdss_axi_clk.clkr, | |
3181 | [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr, | |
3182 | [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr, | |
3183 | [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr, | |
3184 | [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr, | |
3185 | [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr, | |
3186 | [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr, | |
3187 | [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr, | |
3188 | [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr, | |
3189 | [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr, | |
3190 | [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr, | |
3191 | [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr, | |
3192 | [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr, | |
3193 | [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr, | |
3194 | [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr, | |
3195 | [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr, | |
3196 | [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr, | |
3197 | [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr, | |
3198 | [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr, | |
3199 | [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr, | |
3200 | [CAMSS_CCI_CLK] = &camss_cci_clk.clkr, | |
3201 | [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr, | |
3202 | [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr, | |
3203 | [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr, | |
3204 | [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr, | |
3205 | [CAMSS_CSIPHY0_3P_CLK] = &camss_csiphy0_3p_clk.clkr, | |
3206 | [CAMSS_CSIPHY1_3P_CLK] = &camss_csiphy1_3p_clk.clkr, | |
3207 | [CAMSS_CSIPHY2_3P_CLK] = &camss_csiphy2_3p_clk.clkr, | |
3208 | [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr, | |
3209 | [CAMSS_JPEG2_CLK] = &camss_jpeg2_clk.clkr, | |
3210 | [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr, | |
3211 | [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr, | |
3212 | [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr, | |
3213 | [CAMSS_VFE_AHB_CLK] = &camss_vfe_ahb_clk.clkr, | |
3214 | [CAMSS_VFE_AXI_CLK] = &camss_vfe_axi_clk.clkr, | |
3215 | [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr, | |
3216 | [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr, | |
3217 | [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr, | |
3218 | [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr, | |
3219 | [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr, | |
3220 | [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr, | |
3221 | [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr, | |
3222 | [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr, | |
3223 | [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr, | |
3224 | [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr, | |
3225 | [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr, | |
3226 | [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr, | |
3227 | [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr, | |
3228 | [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr, | |
3229 | [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr, | |
3230 | [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr, | |
3231 | [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr, | |
3232 | [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr, | |
3233 | [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr, | |
3234 | [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr, | |
3235 | [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr, | |
3236 | [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr, | |
3237 | [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr, | |
3238 | [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr, | |
3239 | [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr, | |
3240 | [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr, | |
3241 | [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr, | |
3242 | [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr, | |
3243 | [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr, | |
3244 | [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr, | |
3245 | [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr, | |
3246 | [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr, | |
3247 | [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr, | |
3248 | [FD_CORE_CLK] = &fd_core_clk.clkr, | |
3249 | [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr, | |
3250 | [FD_AHB_CLK] = &fd_ahb_clk.clkr, | |
3251 | }; | |
3252 | ||
7e824d50 | 3253 | static struct gdsc *mmcc_msm8996_gdscs[] = { |
63bb4fd6 | 3254 | [MMAGIC_BIMC_GDSC] = &mmagic_bimc_gdsc, |
7e824d50 RN |
3255 | [MMAGIC_VIDEO_GDSC] = &mmagic_video_gdsc, |
3256 | [MMAGIC_MDSS_GDSC] = &mmagic_mdss_gdsc, | |
3257 | [MMAGIC_CAMSS_GDSC] = &mmagic_camss_gdsc, | |
3258 | [VENUS_GDSC] = &venus_gdsc, | |
3259 | [VENUS_CORE0_GDSC] = &venus_core0_gdsc, | |
3260 | [VENUS_CORE1_GDSC] = &venus_core1_gdsc, | |
3261 | [CAMSS_GDSC] = &camss_gdsc, | |
3262 | [VFE0_GDSC] = &vfe0_gdsc, | |
3263 | [VFE1_GDSC] = &vfe1_gdsc, | |
3264 | [JPEG_GDSC] = &jpeg_gdsc, | |
3265 | [CPP_GDSC] = &cpp_gdsc, | |
3266 | [FD_GDSC] = &fd_gdsc, | |
3267 | [MDSS_GDSC] = &mdss_gdsc, | |
4154f619 RN |
3268 | [GPU_GDSC] = &gpu_gdsc, |
3269 | [GPU_GX_GDSC] = &gpu_gx_gdsc, | |
7e824d50 RN |
3270 | }; |
3271 | ||
c2526597 SB |
3272 | static const struct qcom_reset_map mmcc_msm8996_resets[] = { |
3273 | [MMAGICAHB_BCR] = { 0x5020 }, | |
3274 | [MMAGIC_CFG_BCR] = { 0x5050 }, | |
3275 | [MISC_BCR] = { 0x5010 }, | |
3276 | [BTO_BCR] = { 0x5030 }, | |
3277 | [MMAGICAXI_BCR] = { 0x5060 }, | |
3278 | [MMAGICMAXI_BCR] = { 0x5070 }, | |
3279 | [DSA_BCR] = { 0x50a0 }, | |
3280 | [MMAGIC_CAMSS_BCR] = { 0x3c40 }, | |
3281 | [THROTTLE_CAMSS_BCR] = { 0x3c30 }, | |
3282 | [SMMU_VFE_BCR] = { 0x3c00 }, | |
3283 | [SMMU_CPP_BCR] = { 0x3c10 }, | |
3284 | [SMMU_JPEG_BCR] = { 0x3c20 }, | |
3285 | [MMAGIC_MDSS_BCR] = { 0x2470 }, | |
3286 | [THROTTLE_MDSS_BCR] = { 0x2460 }, | |
3287 | [SMMU_ROT_BCR] = { 0x2440 }, | |
3288 | [SMMU_MDP_BCR] = { 0x2450 }, | |
3289 | [MMAGIC_VIDEO_BCR] = { 0x1190 }, | |
3290 | [THROTTLE_VIDEO_BCR] = { 0x1180 }, | |
3291 | [SMMU_VIDEO_BCR] = { 0x1170 }, | |
3292 | [MMAGIC_BIMC_BCR] = { 0x5290 }, | |
3293 | [GPU_GX_BCR] = { 0x4020 }, | |
3294 | [GPU_BCR] = { 0x4030 }, | |
3295 | [GPU_AON_BCR] = { 0x4040 }, | |
3296 | [VMEM_BCR] = { 0x1200 }, | |
3297 | [MMSS_RBCPR_BCR] = { 0x4080 }, | |
3298 | [VIDEO_BCR] = { 0x1020 }, | |
3299 | [MDSS_BCR] = { 0x2300 }, | |
3300 | [CAMSS_TOP_BCR] = { 0x3480 }, | |
3301 | [CAMSS_AHB_BCR] = { 0x3488 }, | |
3302 | [CAMSS_MICRO_BCR] = { 0x3490 }, | |
3303 | [CAMSS_CCI_BCR] = { 0x3340 }, | |
3304 | [CAMSS_PHY0_BCR] = { 0x3020 }, | |
3305 | [CAMSS_PHY1_BCR] = { 0x3050 }, | |
3306 | [CAMSS_PHY2_BCR] = { 0x3080 }, | |
3307 | [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 }, | |
3308 | [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 }, | |
3309 | [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 }, | |
3310 | [CAMSS_JPEG_BCR] = { 0x35a0 }, | |
3311 | [CAMSS_VFE_BCR] = { 0x36a0 }, | |
3312 | [CAMSS_VFE0_BCR] = { 0x3660 }, | |
3313 | [CAMSS_VFE1_BCR] = { 0x3670 }, | |
3314 | [CAMSS_CSI_VFE0_BCR] = { 0x3700 }, | |
3315 | [CAMSS_CSI_VFE1_BCR] = { 0x3710 }, | |
3316 | [CAMSS_CPP_TOP_BCR] = { 0x36c0 }, | |
3317 | [CAMSS_CPP_BCR] = { 0x36d0 }, | |
3318 | [CAMSS_CSI0_BCR] = { 0x30b0 }, | |
3319 | [CAMSS_CSI0RDI_BCR] = { 0x30d0 }, | |
3320 | [CAMSS_CSI0PIX_BCR] = { 0x30e0 }, | |
3321 | [CAMSS_CSI1_BCR] = { 0x3120 }, | |
3322 | [CAMSS_CSI1RDI_BCR] = { 0x3140 }, | |
3323 | [CAMSS_CSI1PIX_BCR] = { 0x3150 }, | |
3324 | [CAMSS_CSI2_BCR] = { 0x3180 }, | |
3325 | [CAMSS_CSI2RDI_BCR] = { 0x31a0 }, | |
3326 | [CAMSS_CSI2PIX_BCR] = { 0x31b0 }, | |
3327 | [CAMSS_CSI3_BCR] = { 0x31e0 }, | |
3328 | [CAMSS_CSI3RDI_BCR] = { 0x3200 }, | |
3329 | [CAMSS_CSI3PIX_BCR] = { 0x3210 }, | |
3330 | [CAMSS_ISPIF_BCR] = { 0x3220 }, | |
3331 | [FD_BCR] = { 0x3b60 }, | |
3332 | [MMSS_SPDM_RM_BCR] = { 0x300 }, | |
3333 | }; | |
3334 | ||
3335 | static const struct regmap_config mmcc_msm8996_regmap_config = { | |
3336 | .reg_bits = 32, | |
3337 | .reg_stride = 4, | |
3338 | .val_bits = 32, | |
3339 | .max_register = 0xb008, | |
3340 | .fast_io = true, | |
3341 | }; | |
3342 | ||
3343 | static const struct qcom_cc_desc mmcc_msm8996_desc = { | |
3344 | .config = &mmcc_msm8996_regmap_config, | |
3345 | .clks = mmcc_msm8996_clocks, | |
3346 | .num_clks = ARRAY_SIZE(mmcc_msm8996_clocks), | |
3347 | .resets = mmcc_msm8996_resets, | |
3348 | .num_resets = ARRAY_SIZE(mmcc_msm8996_resets), | |
7e824d50 RN |
3349 | .gdscs = mmcc_msm8996_gdscs, |
3350 | .num_gdscs = ARRAY_SIZE(mmcc_msm8996_gdscs), | |
c2526597 SB |
3351 | }; |
3352 | ||
3353 | static const struct of_device_id mmcc_msm8996_match_table[] = { | |
3354 | { .compatible = "qcom,mmcc-msm8996" }, | |
3355 | { } | |
3356 | }; | |
3357 | MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table); | |
3358 | ||
3359 | static int mmcc_msm8996_probe(struct platform_device *pdev) | |
3360 | { | |
c2526597 | 3361 | struct device *dev = &pdev->dev; |
120c1552 | 3362 | int i, ret; |
c2526597 SB |
3363 | struct regmap *regmap; |
3364 | ||
3365 | regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc); | |
3366 | if (IS_ERR(regmap)) | |
3367 | return PTR_ERR(regmap); | |
3368 | ||
3369 | /* Disable the AHB DCD */ | |
3370 | regmap_update_bits(regmap, 0x50d8, BIT(31), 0); | |
3371 | /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */ | |
3372 | regmap_update_bits(regmap, 0x5054, BIT(15), 0); | |
3373 | ||
3374 | for (i = 0; i < ARRAY_SIZE(mmcc_msm8996_hws); i++) { | |
120c1552 SB |
3375 | ret = devm_clk_hw_register(dev, mmcc_msm8996_hws[i]); |
3376 | if (ret) | |
3377 | return ret; | |
c2526597 SB |
3378 | } |
3379 | ||
3380 | return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap); | |
3381 | } | |
3382 | ||
3383 | static struct platform_driver mmcc_msm8996_driver = { | |
3384 | .probe = mmcc_msm8996_probe, | |
3385 | .driver = { | |
3386 | .name = "mmcc-msm8996", | |
3387 | .of_match_table = mmcc_msm8996_match_table, | |
3388 | }, | |
3389 | }; | |
3390 | module_platform_driver(mmcc_msm8996_driver); | |
3391 | ||
3392 | MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver"); | |
3393 | MODULE_LICENSE("GPL v2"); | |
3394 | MODULE_ALIAS("platform:mmcc-msm8996"); |