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6d00b56f SB |
1 | /* |
2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/bitops.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/of_device.h> | |
88036090 | 22 | #include <linux/clk.h> |
6d00b56f SB |
23 | #include <linux/clk-provider.h> |
24 | #include <linux/regmap.h> | |
25 | #include <linux/reset-controller.h> | |
26 | ||
27 | #include <dt-bindings/clock/qcom,mmcc-msm8960.h> | |
28 | #include <dt-bindings/reset/qcom,mmcc-msm8960.h> | |
29 | ||
49fc825f | 30 | #include "common.h" |
6d00b56f SB |
31 | #include "clk-regmap.h" |
32 | #include "clk-pll.h" | |
33 | #include "clk-rcg.h" | |
34 | #include "clk-branch.h" | |
35 | #include "reset.h" | |
36 | ||
293d2e97 GD |
37 | enum { |
38 | P_PXO, | |
39 | P_PLL8, | |
40 | P_PLL2, | |
41 | P_PLL3, | |
42 | P_PLL15, | |
43 | P_HDMI_PLL, | |
5532cfb5 AT |
44 | P_DSI1_PLL_DSICLK, |
45 | P_DSI2_PLL_DSICLK, | |
46 | P_DSI1_PLL_BYTECLK, | |
47 | P_DSI2_PLL_BYTECLK, | |
293d2e97 | 48 | }; |
6d00b56f | 49 | |
ff20783f | 50 | #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n } |
6d00b56f | 51 | |
293d2e97 GD |
52 | static const struct parent_map mmcc_pxo_pll8_pll2_map[] = { |
53 | { P_PXO, 0 }, | |
54 | { P_PLL8, 2 }, | |
55 | { P_PLL2, 1 } | |
6d00b56f SB |
56 | }; |
57 | ||
adb11a40 | 58 | static const char * const mmcc_pxo_pll8_pll2[] = { |
6d00b56f SB |
59 | "pxo", |
60 | "pll8_vote", | |
61 | "pll2", | |
62 | }; | |
63 | ||
293d2e97 GD |
64 | static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = { |
65 | { P_PXO, 0 }, | |
66 | { P_PLL8, 2 }, | |
67 | { P_PLL2, 1 }, | |
68 | { P_PLL3, 3 } | |
6d00b56f SB |
69 | }; |
70 | ||
adb11a40 | 71 | static const char * const mmcc_pxo_pll8_pll2_pll15[] = { |
6d00b56f | 72 | "pxo", |
e216ce60 | 73 | "pll8_vote", |
6d00b56f | 74 | "pll2", |
e216ce60 SB |
75 | "pll15", |
76 | }; | |
77 | ||
293d2e97 GD |
78 | static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = { |
79 | { P_PXO, 0 }, | |
80 | { P_PLL8, 2 }, | |
81 | { P_PLL2, 1 }, | |
82 | { P_PLL15, 3 } | |
e216ce60 SB |
83 | }; |
84 | ||
adb11a40 | 85 | static const char * const mmcc_pxo_pll8_pll2_pll3[] = { |
6d00b56f | 86 | "pxo", |
6d00b56f | 87 | "pll8_vote", |
ff20783f | 88 | "pll2", |
6d00b56f SB |
89 | "pll3", |
90 | }; | |
91 | ||
5532cfb5 AT |
92 | static const struct parent_map mmcc_pxo_dsi2_dsi1_map[] = { |
93 | { P_PXO, 0 }, | |
94 | { P_DSI2_PLL_DSICLK, 1 }, | |
95 | { P_DSI1_PLL_DSICLK, 3 }, | |
96 | }; | |
97 | ||
98 | static const char * const mmcc_pxo_dsi2_dsi1[] = { | |
99 | "pxo", | |
100 | "dsi2pll", | |
101 | "dsi1pll", | |
102 | }; | |
103 | ||
104 | static const struct parent_map mmcc_pxo_dsi1_dsi2_byte_map[] = { | |
105 | { P_PXO, 0 }, | |
106 | { P_DSI1_PLL_BYTECLK, 1 }, | |
107 | { P_DSI2_PLL_BYTECLK, 2 }, | |
108 | }; | |
109 | ||
110 | static const char * const mmcc_pxo_dsi1_dsi2_byte[] = { | |
111 | "pxo", | |
112 | "dsi1pllbyte", | |
113 | "dsi2pllbyte", | |
114 | }; | |
115 | ||
6d00b56f SB |
116 | static struct clk_pll pll2 = { |
117 | .l_reg = 0x320, | |
118 | .m_reg = 0x324, | |
119 | .n_reg = 0x328, | |
120 | .config_reg = 0x32c, | |
121 | .mode_reg = 0x31c, | |
122 | .status_reg = 0x334, | |
123 | .status_bit = 16, | |
124 | .clkr.hw.init = &(struct clk_init_data){ | |
125 | .name = "pll2", | |
126 | .parent_names = (const char *[]){ "pxo" }, | |
127 | .num_parents = 1, | |
128 | .ops = &clk_pll_ops, | |
129 | }, | |
130 | }; | |
131 | ||
e216ce60 SB |
132 | static struct clk_pll pll15 = { |
133 | .l_reg = 0x33c, | |
134 | .m_reg = 0x340, | |
135 | .n_reg = 0x344, | |
136 | .config_reg = 0x348, | |
137 | .mode_reg = 0x338, | |
138 | .status_reg = 0x350, | |
139 | .status_bit = 16, | |
140 | .clkr.hw.init = &(struct clk_init_data){ | |
141 | .name = "pll15", | |
142 | .parent_names = (const char *[]){ "pxo" }, | |
143 | .num_parents = 1, | |
144 | .ops = &clk_pll_ops, | |
145 | }, | |
146 | }; | |
147 | ||
148 | static const struct pll_config pll15_config = { | |
149 | .l = 33, | |
150 | .m = 1, | |
151 | .n = 3, | |
152 | .vco_val = 0x2 << 16, | |
153 | .vco_mask = 0x3 << 16, | |
154 | .pre_div_val = 0x0, | |
155 | .pre_div_mask = BIT(19), | |
156 | .post_div_val = 0x0, | |
157 | .post_div_mask = 0x3 << 20, | |
158 | .mn_ena_mask = BIT(22), | |
159 | .main_output_mask = BIT(23), | |
160 | }; | |
161 | ||
6d00b56f SB |
162 | static struct freq_tbl clk_tbl_cam[] = { |
163 | { 6000000, P_PLL8, 4, 1, 16 }, | |
164 | { 8000000, P_PLL8, 4, 1, 12 }, | |
165 | { 12000000, P_PLL8, 4, 1, 8 }, | |
166 | { 16000000, P_PLL8, 4, 1, 6 }, | |
167 | { 19200000, P_PLL8, 4, 1, 5 }, | |
168 | { 24000000, P_PLL8, 4, 1, 4 }, | |
169 | { 32000000, P_PLL8, 4, 1, 3 }, | |
170 | { 48000000, P_PLL8, 4, 1, 2 }, | |
171 | { 64000000, P_PLL8, 3, 1, 2 }, | |
172 | { 96000000, P_PLL8, 4, 0, 0 }, | |
173 | { 128000000, P_PLL8, 3, 0, 0 }, | |
174 | { } | |
175 | }; | |
176 | ||
177 | static struct clk_rcg camclk0_src = { | |
178 | .ns_reg = 0x0148, | |
179 | .md_reg = 0x0144, | |
180 | .mn = { | |
181 | .mnctr_en_bit = 5, | |
182 | .mnctr_reset_bit = 8, | |
183 | .reset_in_cc = true, | |
184 | .mnctr_mode_shift = 6, | |
185 | .n_val_shift = 24, | |
186 | .m_val_shift = 8, | |
187 | .width = 8, | |
188 | }, | |
189 | .p = { | |
190 | .pre_div_shift = 14, | |
191 | .pre_div_width = 2, | |
192 | }, | |
193 | .s = { | |
194 | .src_sel_shift = 0, | |
195 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
196 | }, | |
197 | .freq_tbl = clk_tbl_cam, | |
198 | .clkr = { | |
199 | .enable_reg = 0x0140, | |
200 | .enable_mask = BIT(2), | |
201 | .hw.init = &(struct clk_init_data){ | |
202 | .name = "camclk0_src", | |
203 | .parent_names = mmcc_pxo_pll8_pll2, | |
204 | .num_parents = 3, | |
205 | .ops = &clk_rcg_ops, | |
206 | }, | |
207 | }, | |
208 | }; | |
209 | ||
210 | static struct clk_branch camclk0_clk = { | |
211 | .halt_reg = 0x01e8, | |
212 | .halt_bit = 15, | |
213 | .clkr = { | |
214 | .enable_reg = 0x0140, | |
215 | .enable_mask = BIT(0), | |
216 | .hw.init = &(struct clk_init_data){ | |
217 | .name = "camclk0_clk", | |
218 | .parent_names = (const char *[]){ "camclk0_src" }, | |
219 | .num_parents = 1, | |
220 | .ops = &clk_branch_ops, | |
221 | }, | |
222 | }, | |
223 | ||
224 | }; | |
225 | ||
226 | static struct clk_rcg camclk1_src = { | |
227 | .ns_reg = 0x015c, | |
228 | .md_reg = 0x0158, | |
229 | .mn = { | |
230 | .mnctr_en_bit = 5, | |
231 | .mnctr_reset_bit = 8, | |
232 | .reset_in_cc = true, | |
233 | .mnctr_mode_shift = 6, | |
234 | .n_val_shift = 24, | |
235 | .m_val_shift = 8, | |
236 | .width = 8, | |
237 | }, | |
238 | .p = { | |
239 | .pre_div_shift = 14, | |
240 | .pre_div_width = 2, | |
241 | }, | |
242 | .s = { | |
243 | .src_sel_shift = 0, | |
244 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
245 | }, | |
246 | .freq_tbl = clk_tbl_cam, | |
247 | .clkr = { | |
248 | .enable_reg = 0x0154, | |
249 | .enable_mask = BIT(2), | |
250 | .hw.init = &(struct clk_init_data){ | |
251 | .name = "camclk1_src", | |
252 | .parent_names = mmcc_pxo_pll8_pll2, | |
253 | .num_parents = 3, | |
254 | .ops = &clk_rcg_ops, | |
255 | }, | |
256 | }, | |
257 | }; | |
258 | ||
259 | static struct clk_branch camclk1_clk = { | |
260 | .halt_reg = 0x01e8, | |
261 | .halt_bit = 16, | |
262 | .clkr = { | |
263 | .enable_reg = 0x0154, | |
264 | .enable_mask = BIT(0), | |
265 | .hw.init = &(struct clk_init_data){ | |
266 | .name = "camclk1_clk", | |
267 | .parent_names = (const char *[]){ "camclk1_src" }, | |
268 | .num_parents = 1, | |
269 | .ops = &clk_branch_ops, | |
270 | }, | |
271 | }, | |
272 | ||
273 | }; | |
274 | ||
275 | static struct clk_rcg camclk2_src = { | |
276 | .ns_reg = 0x0228, | |
277 | .md_reg = 0x0224, | |
278 | .mn = { | |
279 | .mnctr_en_bit = 5, | |
280 | .mnctr_reset_bit = 8, | |
281 | .reset_in_cc = true, | |
282 | .mnctr_mode_shift = 6, | |
283 | .n_val_shift = 24, | |
284 | .m_val_shift = 8, | |
285 | .width = 8, | |
286 | }, | |
287 | .p = { | |
288 | .pre_div_shift = 14, | |
289 | .pre_div_width = 2, | |
290 | }, | |
291 | .s = { | |
292 | .src_sel_shift = 0, | |
293 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
294 | }, | |
295 | .freq_tbl = clk_tbl_cam, | |
296 | .clkr = { | |
297 | .enable_reg = 0x0220, | |
298 | .enable_mask = BIT(2), | |
299 | .hw.init = &(struct clk_init_data){ | |
300 | .name = "camclk2_src", | |
301 | .parent_names = mmcc_pxo_pll8_pll2, | |
302 | .num_parents = 3, | |
303 | .ops = &clk_rcg_ops, | |
304 | }, | |
305 | }, | |
306 | }; | |
307 | ||
308 | static struct clk_branch camclk2_clk = { | |
309 | .halt_reg = 0x01e8, | |
310 | .halt_bit = 16, | |
311 | .clkr = { | |
312 | .enable_reg = 0x0220, | |
313 | .enable_mask = BIT(0), | |
314 | .hw.init = &(struct clk_init_data){ | |
315 | .name = "camclk2_clk", | |
316 | .parent_names = (const char *[]){ "camclk2_src" }, | |
317 | .num_parents = 1, | |
318 | .ops = &clk_branch_ops, | |
319 | }, | |
320 | }, | |
321 | ||
322 | }; | |
323 | ||
324 | static struct freq_tbl clk_tbl_csi[] = { | |
325 | { 27000000, P_PXO, 1, 0, 0 }, | |
326 | { 85330000, P_PLL8, 1, 2, 9 }, | |
327 | { 177780000, P_PLL2, 1, 2, 9 }, | |
328 | { } | |
329 | }; | |
330 | ||
331 | static struct clk_rcg csi0_src = { | |
332 | .ns_reg = 0x0048, | |
333 | .md_reg = 0x0044, | |
334 | .mn = { | |
335 | .mnctr_en_bit = 5, | |
336 | .mnctr_reset_bit = 7, | |
337 | .mnctr_mode_shift = 6, | |
338 | .n_val_shift = 24, | |
339 | .m_val_shift = 8, | |
340 | .width = 8, | |
341 | }, | |
342 | .p = { | |
343 | .pre_div_shift = 14, | |
344 | .pre_div_width = 2, | |
345 | }, | |
346 | .s = { | |
347 | .src_sel_shift = 0, | |
348 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
349 | }, | |
350 | .freq_tbl = clk_tbl_csi, | |
351 | .clkr = { | |
352 | .enable_reg = 0x0040, | |
353 | .enable_mask = BIT(2), | |
354 | .hw.init = &(struct clk_init_data){ | |
355 | .name = "csi0_src", | |
356 | .parent_names = mmcc_pxo_pll8_pll2, | |
357 | .num_parents = 3, | |
358 | .ops = &clk_rcg_ops, | |
359 | }, | |
360 | }, | |
361 | }; | |
362 | ||
363 | static struct clk_branch csi0_clk = { | |
364 | .halt_reg = 0x01cc, | |
365 | .halt_bit = 13, | |
366 | .clkr = { | |
367 | .enable_reg = 0x0040, | |
368 | .enable_mask = BIT(0), | |
369 | .hw.init = &(struct clk_init_data){ | |
370 | .parent_names = (const char *[]){ "csi0_src" }, | |
371 | .num_parents = 1, | |
372 | .name = "csi0_clk", | |
373 | .ops = &clk_branch_ops, | |
374 | .flags = CLK_SET_RATE_PARENT, | |
375 | }, | |
376 | }, | |
377 | }; | |
378 | ||
379 | static struct clk_branch csi0_phy_clk = { | |
380 | .halt_reg = 0x01e8, | |
381 | .halt_bit = 9, | |
382 | .clkr = { | |
383 | .enable_reg = 0x0040, | |
384 | .enable_mask = BIT(8), | |
385 | .hw.init = &(struct clk_init_data){ | |
386 | .parent_names = (const char *[]){ "csi0_src" }, | |
387 | .num_parents = 1, | |
388 | .name = "csi0_phy_clk", | |
389 | .ops = &clk_branch_ops, | |
390 | .flags = CLK_SET_RATE_PARENT, | |
391 | }, | |
392 | }, | |
393 | }; | |
394 | ||
395 | static struct clk_rcg csi1_src = { | |
396 | .ns_reg = 0x0010, | |
397 | .md_reg = 0x0028, | |
398 | .mn = { | |
399 | .mnctr_en_bit = 5, | |
400 | .mnctr_reset_bit = 7, | |
401 | .mnctr_mode_shift = 6, | |
402 | .n_val_shift = 24, | |
403 | .m_val_shift = 8, | |
404 | .width = 8, | |
405 | }, | |
406 | .p = { | |
407 | .pre_div_shift = 14, | |
408 | .pre_div_width = 2, | |
409 | }, | |
410 | .s = { | |
411 | .src_sel_shift = 0, | |
412 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
413 | }, | |
414 | .freq_tbl = clk_tbl_csi, | |
415 | .clkr = { | |
416 | .enable_reg = 0x0024, | |
417 | .enable_mask = BIT(2), | |
418 | .hw.init = &(struct clk_init_data){ | |
419 | .name = "csi1_src", | |
420 | .parent_names = mmcc_pxo_pll8_pll2, | |
421 | .num_parents = 3, | |
422 | .ops = &clk_rcg_ops, | |
423 | }, | |
424 | }, | |
425 | }; | |
426 | ||
427 | static struct clk_branch csi1_clk = { | |
428 | .halt_reg = 0x01cc, | |
429 | .halt_bit = 14, | |
430 | .clkr = { | |
431 | .enable_reg = 0x0024, | |
432 | .enable_mask = BIT(0), | |
433 | .hw.init = &(struct clk_init_data){ | |
434 | .parent_names = (const char *[]){ "csi1_src" }, | |
435 | .num_parents = 1, | |
436 | .name = "csi1_clk", | |
437 | .ops = &clk_branch_ops, | |
438 | .flags = CLK_SET_RATE_PARENT, | |
439 | }, | |
440 | }, | |
441 | }; | |
442 | ||
443 | static struct clk_branch csi1_phy_clk = { | |
444 | .halt_reg = 0x01e8, | |
445 | .halt_bit = 10, | |
446 | .clkr = { | |
447 | .enable_reg = 0x0024, | |
448 | .enable_mask = BIT(8), | |
449 | .hw.init = &(struct clk_init_data){ | |
450 | .parent_names = (const char *[]){ "csi1_src" }, | |
451 | .num_parents = 1, | |
452 | .name = "csi1_phy_clk", | |
453 | .ops = &clk_branch_ops, | |
454 | .flags = CLK_SET_RATE_PARENT, | |
455 | }, | |
456 | }, | |
457 | }; | |
458 | ||
459 | static struct clk_rcg csi2_src = { | |
460 | .ns_reg = 0x0234, | |
461 | .md_reg = 0x022c, | |
462 | .mn = { | |
463 | .mnctr_en_bit = 5, | |
464 | .mnctr_reset_bit = 7, | |
465 | .mnctr_mode_shift = 6, | |
466 | .n_val_shift = 24, | |
467 | .m_val_shift = 8, | |
468 | .width = 8, | |
469 | }, | |
470 | .p = { | |
471 | .pre_div_shift = 14, | |
472 | .pre_div_width = 2, | |
473 | }, | |
474 | .s = { | |
475 | .src_sel_shift = 0, | |
476 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
477 | }, | |
478 | .freq_tbl = clk_tbl_csi, | |
479 | .clkr = { | |
480 | .enable_reg = 0x022c, | |
481 | .enable_mask = BIT(2), | |
482 | .hw.init = &(struct clk_init_data){ | |
483 | .name = "csi2_src", | |
484 | .parent_names = mmcc_pxo_pll8_pll2, | |
485 | .num_parents = 3, | |
486 | .ops = &clk_rcg_ops, | |
487 | }, | |
488 | }, | |
489 | }; | |
490 | ||
491 | static struct clk_branch csi2_clk = { | |
492 | .halt_reg = 0x01cc, | |
493 | .halt_bit = 29, | |
494 | .clkr = { | |
495 | .enable_reg = 0x022c, | |
496 | .enable_mask = BIT(0), | |
497 | .hw.init = &(struct clk_init_data){ | |
498 | .parent_names = (const char *[]){ "csi2_src" }, | |
499 | .num_parents = 1, | |
500 | .name = "csi2_clk", | |
501 | .ops = &clk_branch_ops, | |
502 | .flags = CLK_SET_RATE_PARENT, | |
503 | }, | |
504 | }, | |
505 | }; | |
506 | ||
507 | static struct clk_branch csi2_phy_clk = { | |
508 | .halt_reg = 0x01e8, | |
509 | .halt_bit = 29, | |
510 | .clkr = { | |
511 | .enable_reg = 0x022c, | |
512 | .enable_mask = BIT(8), | |
513 | .hw.init = &(struct clk_init_data){ | |
514 | .parent_names = (const char *[]){ "csi2_src" }, | |
515 | .num_parents = 1, | |
516 | .name = "csi2_phy_clk", | |
517 | .ops = &clk_branch_ops, | |
518 | .flags = CLK_SET_RATE_PARENT, | |
519 | }, | |
520 | }, | |
521 | }; | |
522 | ||
523 | struct clk_pix_rdi { | |
524 | u32 s_reg; | |
525 | u32 s_mask; | |
526 | u32 s2_reg; | |
527 | u32 s2_mask; | |
528 | struct clk_regmap clkr; | |
529 | }; | |
530 | ||
531 | #define to_clk_pix_rdi(_hw) \ | |
532 | container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr) | |
533 | ||
534 | static int pix_rdi_set_parent(struct clk_hw *hw, u8 index) | |
535 | { | |
536 | int i; | |
537 | int ret = 0; | |
538 | u32 val; | |
539 | struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw); | |
497295af | 540 | int num_parents = clk_hw_get_num_parents(hw); |
6d00b56f SB |
541 | |
542 | /* | |
543 | * These clocks select three inputs via two muxes. One mux selects | |
544 | * between csi0 and csi1 and the second mux selects between that mux's | |
545 | * output and csi2. The source and destination selections for each | |
546 | * mux must be clocking for the switch to succeed so just turn on | |
547 | * all three sources because it's easier than figuring out what source | |
548 | * needs to be on at what time. | |
549 | */ | |
550 | for (i = 0; i < num_parents; i++) { | |
ac269395 SB |
551 | struct clk_hw *p = clk_hw_get_parent_by_index(hw, i); |
552 | ret = clk_prepare_enable(p->clk); | |
6d00b56f SB |
553 | if (ret) |
554 | goto err; | |
555 | } | |
556 | ||
557 | if (index == 2) | |
558 | val = rdi->s2_mask; | |
559 | else | |
560 | val = 0; | |
561 | regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val); | |
562 | /* | |
563 | * Wait at least 6 cycles of slowest clock | |
564 | * for the glitch-free MUX to fully switch sources. | |
565 | */ | |
566 | udelay(1); | |
567 | ||
568 | if (index == 1) | |
569 | val = rdi->s_mask; | |
570 | else | |
571 | val = 0; | |
572 | regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val); | |
573 | /* | |
574 | * Wait at least 6 cycles of slowest clock | |
575 | * for the glitch-free MUX to fully switch sources. | |
576 | */ | |
577 | udelay(1); | |
578 | ||
579 | err: | |
ac269395 SB |
580 | for (i--; i >= 0; i--) { |
581 | struct clk_hw *p = clk_hw_get_parent_by_index(hw, i); | |
582 | clk_disable_unprepare(p->clk); | |
583 | } | |
6d00b56f SB |
584 | |
585 | return ret; | |
586 | } | |
587 | ||
588 | static u8 pix_rdi_get_parent(struct clk_hw *hw) | |
589 | { | |
590 | u32 val; | |
591 | struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw); | |
592 | ||
593 | ||
594 | regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val); | |
595 | if (val & rdi->s2_mask) | |
596 | return 2; | |
597 | ||
598 | regmap_read(rdi->clkr.regmap, rdi->s_reg, &val); | |
599 | if (val & rdi->s_mask) | |
600 | return 1; | |
601 | ||
602 | return 0; | |
603 | } | |
604 | ||
605 | static const struct clk_ops clk_ops_pix_rdi = { | |
606 | .enable = clk_enable_regmap, | |
607 | .disable = clk_disable_regmap, | |
608 | .set_parent = pix_rdi_set_parent, | |
609 | .get_parent = pix_rdi_get_parent, | |
610 | .determine_rate = __clk_mux_determine_rate, | |
611 | }; | |
612 | ||
adb11a40 | 613 | static const char * const pix_rdi_parents[] = { |
6d00b56f SB |
614 | "csi0_clk", |
615 | "csi1_clk", | |
616 | "csi2_clk", | |
617 | }; | |
618 | ||
619 | static struct clk_pix_rdi csi_pix_clk = { | |
620 | .s_reg = 0x0058, | |
621 | .s_mask = BIT(25), | |
622 | .s2_reg = 0x0238, | |
623 | .s2_mask = BIT(13), | |
624 | .clkr = { | |
625 | .enable_reg = 0x0058, | |
626 | .enable_mask = BIT(26), | |
627 | .hw.init = &(struct clk_init_data){ | |
628 | .name = "csi_pix_clk", | |
629 | .parent_names = pix_rdi_parents, | |
630 | .num_parents = 3, | |
631 | .ops = &clk_ops_pix_rdi, | |
632 | }, | |
633 | }, | |
634 | }; | |
635 | ||
636 | static struct clk_pix_rdi csi_pix1_clk = { | |
637 | .s_reg = 0x0238, | |
638 | .s_mask = BIT(8), | |
639 | .s2_reg = 0x0238, | |
640 | .s2_mask = BIT(9), | |
641 | .clkr = { | |
642 | .enable_reg = 0x0238, | |
643 | .enable_mask = BIT(10), | |
644 | .hw.init = &(struct clk_init_data){ | |
645 | .name = "csi_pix1_clk", | |
646 | .parent_names = pix_rdi_parents, | |
647 | .num_parents = 3, | |
648 | .ops = &clk_ops_pix_rdi, | |
649 | }, | |
650 | }, | |
651 | }; | |
652 | ||
653 | static struct clk_pix_rdi csi_rdi_clk = { | |
654 | .s_reg = 0x0058, | |
655 | .s_mask = BIT(12), | |
656 | .s2_reg = 0x0238, | |
657 | .s2_mask = BIT(12), | |
658 | .clkr = { | |
659 | .enable_reg = 0x0058, | |
660 | .enable_mask = BIT(13), | |
661 | .hw.init = &(struct clk_init_data){ | |
662 | .name = "csi_rdi_clk", | |
663 | .parent_names = pix_rdi_parents, | |
664 | .num_parents = 3, | |
665 | .ops = &clk_ops_pix_rdi, | |
666 | }, | |
667 | }, | |
668 | }; | |
669 | ||
670 | static struct clk_pix_rdi csi_rdi1_clk = { | |
671 | .s_reg = 0x0238, | |
672 | .s_mask = BIT(0), | |
673 | .s2_reg = 0x0238, | |
674 | .s2_mask = BIT(1), | |
675 | .clkr = { | |
676 | .enable_reg = 0x0238, | |
677 | .enable_mask = BIT(2), | |
678 | .hw.init = &(struct clk_init_data){ | |
679 | .name = "csi_rdi1_clk", | |
680 | .parent_names = pix_rdi_parents, | |
681 | .num_parents = 3, | |
682 | .ops = &clk_ops_pix_rdi, | |
683 | }, | |
684 | }, | |
685 | }; | |
686 | ||
687 | static struct clk_pix_rdi csi_rdi2_clk = { | |
688 | .s_reg = 0x0238, | |
689 | .s_mask = BIT(4), | |
690 | .s2_reg = 0x0238, | |
691 | .s2_mask = BIT(5), | |
692 | .clkr = { | |
693 | .enable_reg = 0x0238, | |
694 | .enable_mask = BIT(6), | |
695 | .hw.init = &(struct clk_init_data){ | |
696 | .name = "csi_rdi2_clk", | |
697 | .parent_names = pix_rdi_parents, | |
698 | .num_parents = 3, | |
699 | .ops = &clk_ops_pix_rdi, | |
700 | }, | |
701 | }, | |
702 | }; | |
703 | ||
704 | static struct freq_tbl clk_tbl_csiphytimer[] = { | |
705 | { 85330000, P_PLL8, 1, 2, 9 }, | |
706 | { 177780000, P_PLL2, 1, 2, 9 }, | |
707 | { } | |
708 | }; | |
709 | ||
710 | static struct clk_rcg csiphytimer_src = { | |
711 | .ns_reg = 0x0168, | |
712 | .md_reg = 0x0164, | |
713 | .mn = { | |
714 | .mnctr_en_bit = 5, | |
715 | .mnctr_reset_bit = 8, | |
716 | .reset_in_cc = true, | |
717 | .mnctr_mode_shift = 6, | |
718 | .n_val_shift = 24, | |
719 | .m_val_shift = 8, | |
720 | .width = 8, | |
721 | }, | |
722 | .p = { | |
723 | .pre_div_shift = 14, | |
724 | .pre_div_width = 2, | |
725 | }, | |
726 | .s = { | |
727 | .src_sel_shift = 0, | |
728 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
729 | }, | |
730 | .freq_tbl = clk_tbl_csiphytimer, | |
731 | .clkr = { | |
732 | .enable_reg = 0x0160, | |
733 | .enable_mask = BIT(2), | |
734 | .hw.init = &(struct clk_init_data){ | |
735 | .name = "csiphytimer_src", | |
736 | .parent_names = mmcc_pxo_pll8_pll2, | |
737 | .num_parents = 3, | |
738 | .ops = &clk_rcg_ops, | |
739 | }, | |
740 | }, | |
741 | }; | |
742 | ||
adb11a40 | 743 | static const char * const csixphy_timer_src[] = { "csiphytimer_src" }; |
6d00b56f SB |
744 | |
745 | static struct clk_branch csiphy0_timer_clk = { | |
746 | .halt_reg = 0x01e8, | |
747 | .halt_bit = 17, | |
748 | .clkr = { | |
749 | .enable_reg = 0x0160, | |
750 | .enable_mask = BIT(0), | |
751 | .hw.init = &(struct clk_init_data){ | |
752 | .parent_names = csixphy_timer_src, | |
753 | .num_parents = 1, | |
754 | .name = "csiphy0_timer_clk", | |
755 | .ops = &clk_branch_ops, | |
756 | .flags = CLK_SET_RATE_PARENT, | |
757 | }, | |
758 | }, | |
759 | }; | |
760 | ||
761 | static struct clk_branch csiphy1_timer_clk = { | |
762 | .halt_reg = 0x01e8, | |
763 | .halt_bit = 18, | |
764 | .clkr = { | |
765 | .enable_reg = 0x0160, | |
766 | .enable_mask = BIT(9), | |
767 | .hw.init = &(struct clk_init_data){ | |
768 | .parent_names = csixphy_timer_src, | |
769 | .num_parents = 1, | |
770 | .name = "csiphy1_timer_clk", | |
771 | .ops = &clk_branch_ops, | |
772 | .flags = CLK_SET_RATE_PARENT, | |
773 | }, | |
774 | }, | |
775 | }; | |
776 | ||
777 | static struct clk_branch csiphy2_timer_clk = { | |
778 | .halt_reg = 0x01e8, | |
779 | .halt_bit = 30, | |
780 | .clkr = { | |
781 | .enable_reg = 0x0160, | |
782 | .enable_mask = BIT(11), | |
783 | .hw.init = &(struct clk_init_data){ | |
784 | .parent_names = csixphy_timer_src, | |
785 | .num_parents = 1, | |
786 | .name = "csiphy2_timer_clk", | |
787 | .ops = &clk_branch_ops, | |
788 | .flags = CLK_SET_RATE_PARENT, | |
789 | }, | |
790 | }, | |
791 | }; | |
792 | ||
793 | static struct freq_tbl clk_tbl_gfx2d[] = { | |
ff20783f SB |
794 | F_MN( 27000000, P_PXO, 1, 0), |
795 | F_MN( 48000000, P_PLL8, 1, 8), | |
796 | F_MN( 54857000, P_PLL8, 1, 7), | |
797 | F_MN( 64000000, P_PLL8, 1, 6), | |
798 | F_MN( 76800000, P_PLL8, 1, 5), | |
799 | F_MN( 96000000, P_PLL8, 1, 4), | |
800 | F_MN(128000000, P_PLL8, 1, 3), | |
801 | F_MN(145455000, P_PLL2, 2, 11), | |
802 | F_MN(160000000, P_PLL2, 1, 5), | |
803 | F_MN(177778000, P_PLL2, 2, 9), | |
804 | F_MN(200000000, P_PLL2, 1, 4), | |
805 | F_MN(228571000, P_PLL2, 2, 7), | |
6d00b56f SB |
806 | { } |
807 | }; | |
808 | ||
809 | static struct clk_dyn_rcg gfx2d0_src = { | |
229fd4a5 SB |
810 | .ns_reg[0] = 0x0070, |
811 | .ns_reg[1] = 0x0070, | |
6d00b56f SB |
812 | .md_reg[0] = 0x0064, |
813 | .md_reg[1] = 0x0068, | |
229fd4a5 | 814 | .bank_reg = 0x0060, |
6d00b56f SB |
815 | .mn[0] = { |
816 | .mnctr_en_bit = 8, | |
817 | .mnctr_reset_bit = 25, | |
818 | .mnctr_mode_shift = 9, | |
819 | .n_val_shift = 20, | |
820 | .m_val_shift = 4, | |
821 | .width = 4, | |
822 | }, | |
823 | .mn[1] = { | |
824 | .mnctr_en_bit = 5, | |
825 | .mnctr_reset_bit = 24, | |
826 | .mnctr_mode_shift = 6, | |
827 | .n_val_shift = 16, | |
828 | .m_val_shift = 4, | |
829 | .width = 4, | |
830 | }, | |
831 | .s[0] = { | |
832 | .src_sel_shift = 3, | |
833 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
834 | }, | |
835 | .s[1] = { | |
836 | .src_sel_shift = 0, | |
837 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
838 | }, | |
839 | .mux_sel_bit = 11, | |
840 | .freq_tbl = clk_tbl_gfx2d, | |
841 | .clkr = { | |
842 | .enable_reg = 0x0060, | |
843 | .enable_mask = BIT(2), | |
844 | .hw.init = &(struct clk_init_data){ | |
845 | .name = "gfx2d0_src", | |
846 | .parent_names = mmcc_pxo_pll8_pll2, | |
847 | .num_parents = 3, | |
848 | .ops = &clk_dyn_rcg_ops, | |
849 | }, | |
850 | }, | |
851 | }; | |
852 | ||
853 | static struct clk_branch gfx2d0_clk = { | |
854 | .halt_reg = 0x01c8, | |
855 | .halt_bit = 9, | |
856 | .clkr = { | |
857 | .enable_reg = 0x0060, | |
858 | .enable_mask = BIT(0), | |
859 | .hw.init = &(struct clk_init_data){ | |
860 | .name = "gfx2d0_clk", | |
861 | .parent_names = (const char *[]){ "gfx2d0_src" }, | |
862 | .num_parents = 1, | |
863 | .ops = &clk_branch_ops, | |
864 | .flags = CLK_SET_RATE_PARENT, | |
865 | }, | |
866 | }, | |
867 | }; | |
868 | ||
869 | static struct clk_dyn_rcg gfx2d1_src = { | |
229fd4a5 SB |
870 | .ns_reg[0] = 0x007c, |
871 | .ns_reg[1] = 0x007c, | |
6d00b56f SB |
872 | .md_reg[0] = 0x0078, |
873 | .md_reg[1] = 0x006c, | |
229fd4a5 | 874 | .bank_reg = 0x0074, |
6d00b56f SB |
875 | .mn[0] = { |
876 | .mnctr_en_bit = 8, | |
877 | .mnctr_reset_bit = 25, | |
878 | .mnctr_mode_shift = 9, | |
879 | .n_val_shift = 20, | |
880 | .m_val_shift = 4, | |
881 | .width = 4, | |
882 | }, | |
883 | .mn[1] = { | |
884 | .mnctr_en_bit = 5, | |
885 | .mnctr_reset_bit = 24, | |
886 | .mnctr_mode_shift = 6, | |
887 | .n_val_shift = 16, | |
888 | .m_val_shift = 4, | |
889 | .width = 4, | |
890 | }, | |
891 | .s[0] = { | |
892 | .src_sel_shift = 3, | |
893 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
894 | }, | |
895 | .s[1] = { | |
896 | .src_sel_shift = 0, | |
897 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
898 | }, | |
899 | .mux_sel_bit = 11, | |
900 | .freq_tbl = clk_tbl_gfx2d, | |
901 | .clkr = { | |
902 | .enable_reg = 0x0074, | |
903 | .enable_mask = BIT(2), | |
904 | .hw.init = &(struct clk_init_data){ | |
905 | .name = "gfx2d1_src", | |
906 | .parent_names = mmcc_pxo_pll8_pll2, | |
907 | .num_parents = 3, | |
908 | .ops = &clk_dyn_rcg_ops, | |
909 | }, | |
910 | }, | |
911 | }; | |
912 | ||
913 | static struct clk_branch gfx2d1_clk = { | |
914 | .halt_reg = 0x01c8, | |
915 | .halt_bit = 14, | |
916 | .clkr = { | |
917 | .enable_reg = 0x0074, | |
918 | .enable_mask = BIT(0), | |
919 | .hw.init = &(struct clk_init_data){ | |
920 | .name = "gfx2d1_clk", | |
921 | .parent_names = (const char *[]){ "gfx2d1_src" }, | |
922 | .num_parents = 1, | |
923 | .ops = &clk_branch_ops, | |
924 | .flags = CLK_SET_RATE_PARENT, | |
925 | }, | |
926 | }, | |
927 | }; | |
928 | ||
929 | static struct freq_tbl clk_tbl_gfx3d[] = { | |
ff20783f SB |
930 | F_MN( 27000000, P_PXO, 1, 0), |
931 | F_MN( 48000000, P_PLL8, 1, 8), | |
932 | F_MN( 54857000, P_PLL8, 1, 7), | |
933 | F_MN( 64000000, P_PLL8, 1, 6), | |
934 | F_MN( 76800000, P_PLL8, 1, 5), | |
935 | F_MN( 96000000, P_PLL8, 1, 4), | |
936 | F_MN(128000000, P_PLL8, 1, 3), | |
937 | F_MN(145455000, P_PLL2, 2, 11), | |
938 | F_MN(160000000, P_PLL2, 1, 5), | |
939 | F_MN(177778000, P_PLL2, 2, 9), | |
940 | F_MN(200000000, P_PLL2, 1, 4), | |
941 | F_MN(228571000, P_PLL2, 2, 7), | |
942 | F_MN(266667000, P_PLL2, 1, 3), | |
943 | F_MN(300000000, P_PLL3, 1, 4), | |
944 | F_MN(320000000, P_PLL2, 2, 5), | |
945 | F_MN(400000000, P_PLL2, 1, 2), | |
6d00b56f SB |
946 | { } |
947 | }; | |
948 | ||
e216ce60 SB |
949 | static struct freq_tbl clk_tbl_gfx3d_8064[] = { |
950 | F_MN( 27000000, P_PXO, 0, 0), | |
951 | F_MN( 48000000, P_PLL8, 1, 8), | |
952 | F_MN( 54857000, P_PLL8, 1, 7), | |
953 | F_MN( 64000000, P_PLL8, 1, 6), | |
954 | F_MN( 76800000, P_PLL8, 1, 5), | |
955 | F_MN( 96000000, P_PLL8, 1, 4), | |
956 | F_MN(128000000, P_PLL8, 1, 3), | |
957 | F_MN(145455000, P_PLL2, 2, 11), | |
958 | F_MN(160000000, P_PLL2, 1, 5), | |
959 | F_MN(177778000, P_PLL2, 2, 9), | |
960 | F_MN(192000000, P_PLL8, 1, 2), | |
961 | F_MN(200000000, P_PLL2, 1, 4), | |
962 | F_MN(228571000, P_PLL2, 2, 7), | |
963 | F_MN(266667000, P_PLL2, 1, 3), | |
964 | F_MN(320000000, P_PLL2, 2, 5), | |
965 | F_MN(400000000, P_PLL2, 1, 2), | |
966 | F_MN(450000000, P_PLL15, 1, 2), | |
6d00b56f SB |
967 | { } |
968 | }; | |
969 | ||
970 | static struct clk_dyn_rcg gfx3d_src = { | |
229fd4a5 SB |
971 | .ns_reg[0] = 0x008c, |
972 | .ns_reg[1] = 0x008c, | |
6d00b56f SB |
973 | .md_reg[0] = 0x0084, |
974 | .md_reg[1] = 0x0088, | |
229fd4a5 | 975 | .bank_reg = 0x0080, |
6d00b56f SB |
976 | .mn[0] = { |
977 | .mnctr_en_bit = 8, | |
978 | .mnctr_reset_bit = 25, | |
979 | .mnctr_mode_shift = 9, | |
980 | .n_val_shift = 18, | |
981 | .m_val_shift = 4, | |
982 | .width = 4, | |
983 | }, | |
984 | .mn[1] = { | |
985 | .mnctr_en_bit = 5, | |
986 | .mnctr_reset_bit = 24, | |
987 | .mnctr_mode_shift = 6, | |
988 | .n_val_shift = 14, | |
989 | .m_val_shift = 4, | |
990 | .width = 4, | |
991 | }, | |
992 | .s[0] = { | |
993 | .src_sel_shift = 3, | |
994 | .parent_map = mmcc_pxo_pll8_pll2_pll3_map, | |
995 | }, | |
996 | .s[1] = { | |
997 | .src_sel_shift = 0, | |
998 | .parent_map = mmcc_pxo_pll8_pll2_pll3_map, | |
999 | }, | |
1000 | .mux_sel_bit = 11, | |
1001 | .freq_tbl = clk_tbl_gfx3d, | |
1002 | .clkr = { | |
1003 | .enable_reg = 0x0080, | |
1004 | .enable_mask = BIT(2), | |
1005 | .hw.init = &(struct clk_init_data){ | |
1006 | .name = "gfx3d_src", | |
1007 | .parent_names = mmcc_pxo_pll8_pll2_pll3, | |
ff20783f | 1008 | .num_parents = 4, |
6d00b56f SB |
1009 | .ops = &clk_dyn_rcg_ops, |
1010 | }, | |
1011 | }, | |
1012 | }; | |
1013 | ||
e216ce60 SB |
1014 | static const struct clk_init_data gfx3d_8064_init = { |
1015 | .name = "gfx3d_src", | |
1016 | .parent_names = mmcc_pxo_pll8_pll2_pll15, | |
1017 | .num_parents = 4, | |
1018 | .ops = &clk_dyn_rcg_ops, | |
1019 | }; | |
1020 | ||
6d00b56f SB |
1021 | static struct clk_branch gfx3d_clk = { |
1022 | .halt_reg = 0x01c8, | |
1023 | .halt_bit = 4, | |
1024 | .clkr = { | |
1025 | .enable_reg = 0x0080, | |
1026 | .enable_mask = BIT(0), | |
1027 | .hw.init = &(struct clk_init_data){ | |
1028 | .name = "gfx3d_clk", | |
1029 | .parent_names = (const char *[]){ "gfx3d_src" }, | |
1030 | .num_parents = 1, | |
1031 | .ops = &clk_branch_ops, | |
1032 | .flags = CLK_SET_RATE_PARENT, | |
1033 | }, | |
1034 | }, | |
1035 | }; | |
1036 | ||
e216ce60 SB |
1037 | static struct freq_tbl clk_tbl_vcap[] = { |
1038 | F_MN( 27000000, P_PXO, 0, 0), | |
1039 | F_MN( 54860000, P_PLL8, 1, 7), | |
1040 | F_MN( 64000000, P_PLL8, 1, 6), | |
1041 | F_MN( 76800000, P_PLL8, 1, 5), | |
1042 | F_MN(128000000, P_PLL8, 1, 3), | |
1043 | F_MN(160000000, P_PLL2, 1, 5), | |
1044 | F_MN(200000000, P_PLL2, 1, 4), | |
1045 | { } | |
1046 | }; | |
1047 | ||
1048 | static struct clk_dyn_rcg vcap_src = { | |
229fd4a5 SB |
1049 | .ns_reg[0] = 0x021c, |
1050 | .ns_reg[1] = 0x021c, | |
e216ce60 SB |
1051 | .md_reg[0] = 0x01ec, |
1052 | .md_reg[1] = 0x0218, | |
229fd4a5 | 1053 | .bank_reg = 0x0178, |
e216ce60 SB |
1054 | .mn[0] = { |
1055 | .mnctr_en_bit = 8, | |
1056 | .mnctr_reset_bit = 23, | |
1057 | .mnctr_mode_shift = 9, | |
1058 | .n_val_shift = 18, | |
1059 | .m_val_shift = 4, | |
1060 | .width = 4, | |
1061 | }, | |
1062 | .mn[1] = { | |
1063 | .mnctr_en_bit = 5, | |
1064 | .mnctr_reset_bit = 22, | |
1065 | .mnctr_mode_shift = 6, | |
1066 | .n_val_shift = 14, | |
1067 | .m_val_shift = 4, | |
1068 | .width = 4, | |
1069 | }, | |
1070 | .s[0] = { | |
1071 | .src_sel_shift = 3, | |
1072 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
1073 | }, | |
1074 | .s[1] = { | |
1075 | .src_sel_shift = 0, | |
1076 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
1077 | }, | |
1078 | .mux_sel_bit = 11, | |
1079 | .freq_tbl = clk_tbl_vcap, | |
1080 | .clkr = { | |
1081 | .enable_reg = 0x0178, | |
1082 | .enable_mask = BIT(2), | |
1083 | .hw.init = &(struct clk_init_data){ | |
1084 | .name = "vcap_src", | |
1085 | .parent_names = mmcc_pxo_pll8_pll2, | |
1086 | .num_parents = 3, | |
1087 | .ops = &clk_dyn_rcg_ops, | |
1088 | }, | |
1089 | }, | |
1090 | }; | |
1091 | ||
1092 | static struct clk_branch vcap_clk = { | |
1093 | .halt_reg = 0x0240, | |
1094 | .halt_bit = 15, | |
1095 | .clkr = { | |
1096 | .enable_reg = 0x0178, | |
1097 | .enable_mask = BIT(0), | |
1098 | .hw.init = &(struct clk_init_data){ | |
1099 | .name = "vcap_clk", | |
1100 | .parent_names = (const char *[]){ "vcap_src" }, | |
1101 | .num_parents = 1, | |
1102 | .ops = &clk_branch_ops, | |
1103 | .flags = CLK_SET_RATE_PARENT, | |
1104 | }, | |
1105 | }, | |
1106 | }; | |
1107 | ||
1108 | static struct clk_branch vcap_npl_clk = { | |
1109 | .halt_reg = 0x0240, | |
1110 | .halt_bit = 25, | |
1111 | .clkr = { | |
1112 | .enable_reg = 0x0178, | |
1113 | .enable_mask = BIT(13), | |
1114 | .hw.init = &(struct clk_init_data){ | |
1115 | .name = "vcap_npl_clk", | |
1116 | .parent_names = (const char *[]){ "vcap_src" }, | |
1117 | .num_parents = 1, | |
1118 | .ops = &clk_branch_ops, | |
1119 | .flags = CLK_SET_RATE_PARENT, | |
1120 | }, | |
1121 | }, | |
1122 | }; | |
1123 | ||
6d00b56f SB |
1124 | static struct freq_tbl clk_tbl_ijpeg[] = { |
1125 | { 27000000, P_PXO, 1, 0, 0 }, | |
1126 | { 36570000, P_PLL8, 1, 2, 21 }, | |
1127 | { 54860000, P_PLL8, 7, 0, 0 }, | |
1128 | { 96000000, P_PLL8, 4, 0, 0 }, | |
1129 | { 109710000, P_PLL8, 1, 2, 7 }, | |
1130 | { 128000000, P_PLL8, 3, 0, 0 }, | |
1131 | { 153600000, P_PLL8, 1, 2, 5 }, | |
1132 | { 200000000, P_PLL2, 4, 0, 0 }, | |
1133 | { 228571000, P_PLL2, 1, 2, 7 }, | |
1134 | { 266667000, P_PLL2, 1, 1, 3 }, | |
1135 | { 320000000, P_PLL2, 1, 2, 5 }, | |
1136 | { } | |
1137 | }; | |
1138 | ||
1139 | static struct clk_rcg ijpeg_src = { | |
1140 | .ns_reg = 0x00a0, | |
1141 | .md_reg = 0x009c, | |
1142 | .mn = { | |
1143 | .mnctr_en_bit = 5, | |
1144 | .mnctr_reset_bit = 7, | |
1145 | .mnctr_mode_shift = 6, | |
1146 | .n_val_shift = 16, | |
1147 | .m_val_shift = 8, | |
1148 | .width = 8, | |
1149 | }, | |
1150 | .p = { | |
1151 | .pre_div_shift = 12, | |
1152 | .pre_div_width = 2, | |
1153 | }, | |
1154 | .s = { | |
1155 | .src_sel_shift = 0, | |
1156 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
1157 | }, | |
1158 | .freq_tbl = clk_tbl_ijpeg, | |
1159 | .clkr = { | |
1160 | .enable_reg = 0x0098, | |
1161 | .enable_mask = BIT(2), | |
1162 | .hw.init = &(struct clk_init_data){ | |
1163 | .name = "ijpeg_src", | |
1164 | .parent_names = mmcc_pxo_pll8_pll2, | |
1165 | .num_parents = 3, | |
1166 | .ops = &clk_rcg_ops, | |
1167 | }, | |
1168 | }, | |
1169 | }; | |
1170 | ||
1171 | static struct clk_branch ijpeg_clk = { | |
1172 | .halt_reg = 0x01c8, | |
1173 | .halt_bit = 24, | |
1174 | .clkr = { | |
1175 | .enable_reg = 0x0098, | |
1176 | .enable_mask = BIT(0), | |
1177 | .hw.init = &(struct clk_init_data){ | |
1178 | .name = "ijpeg_clk", | |
1179 | .parent_names = (const char *[]){ "ijpeg_src" }, | |
1180 | .num_parents = 1, | |
1181 | .ops = &clk_branch_ops, | |
1182 | .flags = CLK_SET_RATE_PARENT, | |
1183 | }, | |
1184 | }, | |
1185 | }; | |
1186 | ||
1187 | static struct freq_tbl clk_tbl_jpegd[] = { | |
1188 | { 64000000, P_PLL8, 6 }, | |
1189 | { 76800000, P_PLL8, 5 }, | |
1190 | { 96000000, P_PLL8, 4 }, | |
1191 | { 160000000, P_PLL2, 5 }, | |
1192 | { 200000000, P_PLL2, 4 }, | |
1193 | { } | |
1194 | }; | |
1195 | ||
1196 | static struct clk_rcg jpegd_src = { | |
1197 | .ns_reg = 0x00ac, | |
1198 | .p = { | |
1199 | .pre_div_shift = 12, | |
ff20783f | 1200 | .pre_div_width = 4, |
6d00b56f SB |
1201 | }, |
1202 | .s = { | |
1203 | .src_sel_shift = 0, | |
1204 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
1205 | }, | |
1206 | .freq_tbl = clk_tbl_jpegd, | |
1207 | .clkr = { | |
1208 | .enable_reg = 0x00a4, | |
1209 | .enable_mask = BIT(2), | |
1210 | .hw.init = &(struct clk_init_data){ | |
1211 | .name = "jpegd_src", | |
1212 | .parent_names = mmcc_pxo_pll8_pll2, | |
1213 | .num_parents = 3, | |
1214 | .ops = &clk_rcg_ops, | |
1215 | }, | |
1216 | }, | |
1217 | }; | |
1218 | ||
1219 | static struct clk_branch jpegd_clk = { | |
1220 | .halt_reg = 0x01c8, | |
1221 | .halt_bit = 19, | |
1222 | .clkr = { | |
1223 | .enable_reg = 0x00a4, | |
1224 | .enable_mask = BIT(0), | |
1225 | .hw.init = &(struct clk_init_data){ | |
1226 | .name = "jpegd_clk", | |
1227 | .parent_names = (const char *[]){ "jpegd_src" }, | |
1228 | .num_parents = 1, | |
1229 | .ops = &clk_branch_ops, | |
1230 | .flags = CLK_SET_RATE_PARENT, | |
1231 | }, | |
1232 | }, | |
1233 | }; | |
1234 | ||
1235 | static struct freq_tbl clk_tbl_mdp[] = { | |
1236 | { 9600000, P_PLL8, 1, 1, 40 }, | |
1237 | { 13710000, P_PLL8, 1, 1, 28 }, | |
1238 | { 27000000, P_PXO, 1, 0, 0 }, | |
1239 | { 29540000, P_PLL8, 1, 1, 13 }, | |
1240 | { 34910000, P_PLL8, 1, 1, 11 }, | |
1241 | { 38400000, P_PLL8, 1, 1, 10 }, | |
1242 | { 59080000, P_PLL8, 1, 2, 13 }, | |
1243 | { 76800000, P_PLL8, 1, 1, 5 }, | |
1244 | { 85330000, P_PLL8, 1, 2, 9 }, | |
1245 | { 96000000, P_PLL8, 1, 1, 4 }, | |
1246 | { 128000000, P_PLL8, 1, 1, 3 }, | |
1247 | { 160000000, P_PLL2, 1, 1, 5 }, | |
1248 | { 177780000, P_PLL2, 1, 2, 9 }, | |
1249 | { 200000000, P_PLL2, 1, 1, 4 }, | |
1250 | { 228571000, P_PLL2, 1, 2, 7 }, | |
1251 | { 266667000, P_PLL2, 1, 1, 3 }, | |
1252 | { } | |
1253 | }; | |
1254 | ||
1255 | static struct clk_dyn_rcg mdp_src = { | |
229fd4a5 SB |
1256 | .ns_reg[0] = 0x00d0, |
1257 | .ns_reg[1] = 0x00d0, | |
6d00b56f SB |
1258 | .md_reg[0] = 0x00c4, |
1259 | .md_reg[1] = 0x00c8, | |
229fd4a5 | 1260 | .bank_reg = 0x00c0, |
6d00b56f SB |
1261 | .mn[0] = { |
1262 | .mnctr_en_bit = 8, | |
1263 | .mnctr_reset_bit = 31, | |
1264 | .mnctr_mode_shift = 9, | |
1265 | .n_val_shift = 22, | |
1266 | .m_val_shift = 8, | |
1267 | .width = 8, | |
1268 | }, | |
1269 | .mn[1] = { | |
1270 | .mnctr_en_bit = 5, | |
1271 | .mnctr_reset_bit = 30, | |
1272 | .mnctr_mode_shift = 6, | |
1273 | .n_val_shift = 14, | |
1274 | .m_val_shift = 8, | |
1275 | .width = 8, | |
1276 | }, | |
1277 | .s[0] = { | |
1278 | .src_sel_shift = 3, | |
1279 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
1280 | }, | |
1281 | .s[1] = { | |
1282 | .src_sel_shift = 0, | |
1283 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
1284 | }, | |
1285 | .mux_sel_bit = 11, | |
1286 | .freq_tbl = clk_tbl_mdp, | |
1287 | .clkr = { | |
1288 | .enable_reg = 0x00c0, | |
1289 | .enable_mask = BIT(2), | |
1290 | .hw.init = &(struct clk_init_data){ | |
1291 | .name = "mdp_src", | |
1292 | .parent_names = mmcc_pxo_pll8_pll2, | |
1293 | .num_parents = 3, | |
1294 | .ops = &clk_dyn_rcg_ops, | |
1295 | }, | |
1296 | }, | |
1297 | }; | |
1298 | ||
1299 | static struct clk_branch mdp_clk = { | |
1300 | .halt_reg = 0x01d0, | |
1301 | .halt_bit = 10, | |
1302 | .clkr = { | |
1303 | .enable_reg = 0x00c0, | |
1304 | .enable_mask = BIT(0), | |
1305 | .hw.init = &(struct clk_init_data){ | |
1306 | .name = "mdp_clk", | |
1307 | .parent_names = (const char *[]){ "mdp_src" }, | |
1308 | .num_parents = 1, | |
1309 | .ops = &clk_branch_ops, | |
1310 | .flags = CLK_SET_RATE_PARENT, | |
1311 | }, | |
1312 | }, | |
1313 | }; | |
1314 | ||
1315 | static struct clk_branch mdp_lut_clk = { | |
1316 | .halt_reg = 0x01e8, | |
1317 | .halt_bit = 13, | |
1318 | .clkr = { | |
1319 | .enable_reg = 0x016c, | |
1320 | .enable_mask = BIT(0), | |
1321 | .hw.init = &(struct clk_init_data){ | |
f87dfcab | 1322 | .parent_names = (const char *[]){ "mdp_src" }, |
6d00b56f SB |
1323 | .num_parents = 1, |
1324 | .name = "mdp_lut_clk", | |
1325 | .ops = &clk_branch_ops, | |
1326 | .flags = CLK_SET_RATE_PARENT, | |
1327 | }, | |
1328 | }, | |
1329 | }; | |
1330 | ||
1331 | static struct clk_branch mdp_vsync_clk = { | |
1332 | .halt_reg = 0x01cc, | |
1333 | .halt_bit = 22, | |
1334 | .clkr = { | |
1335 | .enable_reg = 0x0058, | |
1336 | .enable_mask = BIT(6), | |
1337 | .hw.init = &(struct clk_init_data){ | |
1338 | .name = "mdp_vsync_clk", | |
1339 | .parent_names = (const char *[]){ "pxo" }, | |
1340 | .num_parents = 1, | |
1341 | .ops = &clk_branch_ops | |
1342 | }, | |
1343 | }, | |
1344 | }; | |
1345 | ||
1346 | static struct freq_tbl clk_tbl_rot[] = { | |
1347 | { 27000000, P_PXO, 1 }, | |
1348 | { 29540000, P_PLL8, 13 }, | |
1349 | { 32000000, P_PLL8, 12 }, | |
1350 | { 38400000, P_PLL8, 10 }, | |
1351 | { 48000000, P_PLL8, 8 }, | |
1352 | { 54860000, P_PLL8, 7 }, | |
1353 | { 64000000, P_PLL8, 6 }, | |
1354 | { 76800000, P_PLL8, 5 }, | |
1355 | { 96000000, P_PLL8, 4 }, | |
1356 | { 100000000, P_PLL2, 8 }, | |
1357 | { 114290000, P_PLL2, 7 }, | |
1358 | { 133330000, P_PLL2, 6 }, | |
1359 | { 160000000, P_PLL2, 5 }, | |
1360 | { 200000000, P_PLL2, 4 }, | |
1361 | { } | |
1362 | }; | |
1363 | ||
1364 | static struct clk_dyn_rcg rot_src = { | |
229fd4a5 SB |
1365 | .ns_reg[0] = 0x00e8, |
1366 | .ns_reg[1] = 0x00e8, | |
1367 | .bank_reg = 0x00e8, | |
6d00b56f SB |
1368 | .p[0] = { |
1369 | .pre_div_shift = 22, | |
1370 | .pre_div_width = 4, | |
1371 | }, | |
1372 | .p[1] = { | |
1373 | .pre_div_shift = 26, | |
1374 | .pre_div_width = 4, | |
1375 | }, | |
1376 | .s[0] = { | |
1377 | .src_sel_shift = 16, | |
1378 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
1379 | }, | |
1380 | .s[1] = { | |
1381 | .src_sel_shift = 19, | |
1382 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
1383 | }, | |
1384 | .mux_sel_bit = 30, | |
1385 | .freq_tbl = clk_tbl_rot, | |
1386 | .clkr = { | |
1387 | .enable_reg = 0x00e0, | |
1388 | .enable_mask = BIT(2), | |
1389 | .hw.init = &(struct clk_init_data){ | |
1390 | .name = "rot_src", | |
1391 | .parent_names = mmcc_pxo_pll8_pll2, | |
1392 | .num_parents = 3, | |
1393 | .ops = &clk_dyn_rcg_ops, | |
1394 | }, | |
1395 | }, | |
1396 | }; | |
1397 | ||
1398 | static struct clk_branch rot_clk = { | |
1399 | .halt_reg = 0x01d0, | |
1400 | .halt_bit = 15, | |
1401 | .clkr = { | |
1402 | .enable_reg = 0x00e0, | |
1403 | .enable_mask = BIT(0), | |
1404 | .hw.init = &(struct clk_init_data){ | |
1405 | .name = "rot_clk", | |
1406 | .parent_names = (const char *[]){ "rot_src" }, | |
1407 | .num_parents = 1, | |
1408 | .ops = &clk_branch_ops, | |
1409 | .flags = CLK_SET_RATE_PARENT, | |
1410 | }, | |
1411 | }, | |
1412 | }; | |
1413 | ||
293d2e97 GD |
1414 | static const struct parent_map mmcc_pxo_hdmi_map[] = { |
1415 | { P_PXO, 0 }, | |
1416 | { P_HDMI_PLL, 3 } | |
6d00b56f SB |
1417 | }; |
1418 | ||
adb11a40 | 1419 | static const char * const mmcc_pxo_hdmi[] = { |
6d00b56f SB |
1420 | "pxo", |
1421 | "hdmi_pll", | |
1422 | }; | |
1423 | ||
1424 | static struct freq_tbl clk_tbl_tv[] = { | |
404c1ff6 | 1425 | { .src = P_HDMI_PLL, .pre_div = 1 }, |
6d00b56f SB |
1426 | { } |
1427 | }; | |
1428 | ||
1429 | static struct clk_rcg tv_src = { | |
1430 | .ns_reg = 0x00f4, | |
1431 | .md_reg = 0x00f0, | |
1432 | .mn = { | |
1433 | .mnctr_en_bit = 5, | |
1434 | .mnctr_reset_bit = 7, | |
1435 | .mnctr_mode_shift = 6, | |
1436 | .n_val_shift = 16, | |
1437 | .m_val_shift = 8, | |
1438 | .width = 8, | |
1439 | }, | |
1440 | .p = { | |
1441 | .pre_div_shift = 14, | |
1442 | .pre_div_width = 2, | |
1443 | }, | |
1444 | .s = { | |
1445 | .src_sel_shift = 0, | |
1446 | .parent_map = mmcc_pxo_hdmi_map, | |
1447 | }, | |
1448 | .freq_tbl = clk_tbl_tv, | |
1449 | .clkr = { | |
1450 | .enable_reg = 0x00ec, | |
1451 | .enable_mask = BIT(2), | |
1452 | .hw.init = &(struct clk_init_data){ | |
1453 | .name = "tv_src", | |
1454 | .parent_names = mmcc_pxo_hdmi, | |
1455 | .num_parents = 2, | |
404c1ff6 | 1456 | .ops = &clk_rcg_bypass_ops, |
6d00b56f SB |
1457 | .flags = CLK_SET_RATE_PARENT, |
1458 | }, | |
1459 | }, | |
1460 | }; | |
1461 | ||
adb11a40 | 1462 | static const char * const tv_src_name[] = { "tv_src" }; |
6d00b56f SB |
1463 | |
1464 | static struct clk_branch tv_enc_clk = { | |
1465 | .halt_reg = 0x01d4, | |
1466 | .halt_bit = 9, | |
1467 | .clkr = { | |
1468 | .enable_reg = 0x00ec, | |
1469 | .enable_mask = BIT(8), | |
1470 | .hw.init = &(struct clk_init_data){ | |
1471 | .parent_names = tv_src_name, | |
1472 | .num_parents = 1, | |
1473 | .name = "tv_enc_clk", | |
1474 | .ops = &clk_branch_ops, | |
1475 | .flags = CLK_SET_RATE_PARENT, | |
1476 | }, | |
1477 | }, | |
1478 | }; | |
1479 | ||
1480 | static struct clk_branch tv_dac_clk = { | |
1481 | .halt_reg = 0x01d4, | |
1482 | .halt_bit = 10, | |
1483 | .clkr = { | |
1484 | .enable_reg = 0x00ec, | |
1485 | .enable_mask = BIT(10), | |
1486 | .hw.init = &(struct clk_init_data){ | |
1487 | .parent_names = tv_src_name, | |
1488 | .num_parents = 1, | |
1489 | .name = "tv_dac_clk", | |
1490 | .ops = &clk_branch_ops, | |
1491 | .flags = CLK_SET_RATE_PARENT, | |
1492 | }, | |
1493 | }, | |
1494 | }; | |
1495 | ||
1496 | static struct clk_branch mdp_tv_clk = { | |
1497 | .halt_reg = 0x01d4, | |
1498 | .halt_bit = 12, | |
1499 | .clkr = { | |
1500 | .enable_reg = 0x00ec, | |
1501 | .enable_mask = BIT(0), | |
1502 | .hw.init = &(struct clk_init_data){ | |
1503 | .parent_names = tv_src_name, | |
1504 | .num_parents = 1, | |
1505 | .name = "mdp_tv_clk", | |
1506 | .ops = &clk_branch_ops, | |
1507 | .flags = CLK_SET_RATE_PARENT, | |
1508 | }, | |
1509 | }, | |
1510 | }; | |
1511 | ||
1512 | static struct clk_branch hdmi_tv_clk = { | |
1513 | .halt_reg = 0x01d4, | |
1514 | .halt_bit = 11, | |
1515 | .clkr = { | |
1516 | .enable_reg = 0x00ec, | |
1517 | .enable_mask = BIT(12), | |
1518 | .hw.init = &(struct clk_init_data){ | |
1519 | .parent_names = tv_src_name, | |
1520 | .num_parents = 1, | |
1521 | .name = "hdmi_tv_clk", | |
1522 | .ops = &clk_branch_ops, | |
1523 | .flags = CLK_SET_RATE_PARENT, | |
1524 | }, | |
1525 | }, | |
1526 | }; | |
1527 | ||
e216ce60 SB |
1528 | static struct clk_branch rgb_tv_clk = { |
1529 | .halt_reg = 0x0240, | |
1530 | .halt_bit = 27, | |
1531 | .clkr = { | |
1532 | .enable_reg = 0x0124, | |
1533 | .enable_mask = BIT(14), | |
1534 | .hw.init = &(struct clk_init_data){ | |
1535 | .parent_names = tv_src_name, | |
1536 | .num_parents = 1, | |
1537 | .name = "rgb_tv_clk", | |
1538 | .ops = &clk_branch_ops, | |
1539 | .flags = CLK_SET_RATE_PARENT, | |
1540 | }, | |
1541 | }, | |
1542 | }; | |
1543 | ||
1544 | static struct clk_branch npl_tv_clk = { | |
1545 | .halt_reg = 0x0240, | |
1546 | .halt_bit = 26, | |
1547 | .clkr = { | |
1548 | .enable_reg = 0x0124, | |
1549 | .enable_mask = BIT(16), | |
1550 | .hw.init = &(struct clk_init_data){ | |
1551 | .parent_names = tv_src_name, | |
1552 | .num_parents = 1, | |
1553 | .name = "npl_tv_clk", | |
1554 | .ops = &clk_branch_ops, | |
1555 | .flags = CLK_SET_RATE_PARENT, | |
1556 | }, | |
1557 | }, | |
1558 | }; | |
1559 | ||
6d00b56f SB |
1560 | static struct clk_branch hdmi_app_clk = { |
1561 | .halt_reg = 0x01cc, | |
1562 | .halt_bit = 25, | |
1563 | .clkr = { | |
1564 | .enable_reg = 0x005c, | |
1565 | .enable_mask = BIT(11), | |
1566 | .hw.init = &(struct clk_init_data){ | |
1567 | .parent_names = (const char *[]){ "pxo" }, | |
1568 | .num_parents = 1, | |
1569 | .name = "hdmi_app_clk", | |
1570 | .ops = &clk_branch_ops, | |
1571 | }, | |
1572 | }, | |
1573 | }; | |
1574 | ||
1575 | static struct freq_tbl clk_tbl_vcodec[] = { | |
ff20783f SB |
1576 | F_MN( 27000000, P_PXO, 1, 0), |
1577 | F_MN( 32000000, P_PLL8, 1, 12), | |
1578 | F_MN( 48000000, P_PLL8, 1, 8), | |
1579 | F_MN( 54860000, P_PLL8, 1, 7), | |
1580 | F_MN( 96000000, P_PLL8, 1, 4), | |
1581 | F_MN(133330000, P_PLL2, 1, 6), | |
1582 | F_MN(200000000, P_PLL2, 1, 4), | |
1583 | F_MN(228570000, P_PLL2, 2, 7), | |
1584 | F_MN(266670000, P_PLL2, 1, 3), | |
6d00b56f SB |
1585 | { } |
1586 | }; | |
1587 | ||
1588 | static struct clk_dyn_rcg vcodec_src = { | |
229fd4a5 SB |
1589 | .ns_reg[0] = 0x0100, |
1590 | .ns_reg[1] = 0x0100, | |
6d00b56f SB |
1591 | .md_reg[0] = 0x00fc, |
1592 | .md_reg[1] = 0x0128, | |
229fd4a5 | 1593 | .bank_reg = 0x00f8, |
6d00b56f SB |
1594 | .mn[0] = { |
1595 | .mnctr_en_bit = 5, | |
1596 | .mnctr_reset_bit = 31, | |
1597 | .mnctr_mode_shift = 6, | |
1598 | .n_val_shift = 11, | |
1599 | .m_val_shift = 8, | |
1600 | .width = 8, | |
1601 | }, | |
1602 | .mn[1] = { | |
1603 | .mnctr_en_bit = 10, | |
1604 | .mnctr_reset_bit = 30, | |
1605 | .mnctr_mode_shift = 11, | |
1606 | .n_val_shift = 19, | |
1607 | .m_val_shift = 8, | |
1608 | .width = 8, | |
1609 | }, | |
1610 | .s[0] = { | |
1611 | .src_sel_shift = 27, | |
1612 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
1613 | }, | |
1614 | .s[1] = { | |
1615 | .src_sel_shift = 0, | |
1616 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
1617 | }, | |
1618 | .mux_sel_bit = 13, | |
1619 | .freq_tbl = clk_tbl_vcodec, | |
1620 | .clkr = { | |
1621 | .enable_reg = 0x00f8, | |
1622 | .enable_mask = BIT(2), | |
1623 | .hw.init = &(struct clk_init_data){ | |
1624 | .name = "vcodec_src", | |
1625 | .parent_names = mmcc_pxo_pll8_pll2, | |
1626 | .num_parents = 3, | |
1627 | .ops = &clk_dyn_rcg_ops, | |
1628 | }, | |
1629 | }, | |
1630 | }; | |
1631 | ||
1632 | static struct clk_branch vcodec_clk = { | |
1633 | .halt_reg = 0x01d0, | |
1634 | .halt_bit = 29, | |
1635 | .clkr = { | |
1636 | .enable_reg = 0x00f8, | |
1637 | .enable_mask = BIT(0), | |
1638 | .hw.init = &(struct clk_init_data){ | |
1639 | .name = "vcodec_clk", | |
1640 | .parent_names = (const char *[]){ "vcodec_src" }, | |
1641 | .num_parents = 1, | |
1642 | .ops = &clk_branch_ops, | |
1643 | .flags = CLK_SET_RATE_PARENT, | |
1644 | }, | |
1645 | }, | |
1646 | }; | |
1647 | ||
1648 | static struct freq_tbl clk_tbl_vpe[] = { | |
1649 | { 27000000, P_PXO, 1 }, | |
1650 | { 34909000, P_PLL8, 11 }, | |
1651 | { 38400000, P_PLL8, 10 }, | |
1652 | { 64000000, P_PLL8, 6 }, | |
1653 | { 76800000, P_PLL8, 5 }, | |
1654 | { 96000000, P_PLL8, 4 }, | |
1655 | { 100000000, P_PLL2, 8 }, | |
1656 | { 160000000, P_PLL2, 5 }, | |
1657 | { } | |
1658 | }; | |
1659 | ||
1660 | static struct clk_rcg vpe_src = { | |
1661 | .ns_reg = 0x0118, | |
1662 | .p = { | |
1663 | .pre_div_shift = 12, | |
1664 | .pre_div_width = 4, | |
1665 | }, | |
1666 | .s = { | |
1667 | .src_sel_shift = 0, | |
1668 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
1669 | }, | |
1670 | .freq_tbl = clk_tbl_vpe, | |
1671 | .clkr = { | |
1672 | .enable_reg = 0x0110, | |
1673 | .enable_mask = BIT(2), | |
1674 | .hw.init = &(struct clk_init_data){ | |
1675 | .name = "vpe_src", | |
1676 | .parent_names = mmcc_pxo_pll8_pll2, | |
1677 | .num_parents = 3, | |
1678 | .ops = &clk_rcg_ops, | |
1679 | }, | |
1680 | }, | |
1681 | }; | |
1682 | ||
1683 | static struct clk_branch vpe_clk = { | |
1684 | .halt_reg = 0x01c8, | |
1685 | .halt_bit = 28, | |
1686 | .clkr = { | |
1687 | .enable_reg = 0x0110, | |
1688 | .enable_mask = BIT(0), | |
1689 | .hw.init = &(struct clk_init_data){ | |
1690 | .name = "vpe_clk", | |
1691 | .parent_names = (const char *[]){ "vpe_src" }, | |
1692 | .num_parents = 1, | |
1693 | .ops = &clk_branch_ops, | |
1694 | .flags = CLK_SET_RATE_PARENT, | |
1695 | }, | |
1696 | }, | |
1697 | }; | |
1698 | ||
1699 | static struct freq_tbl clk_tbl_vfe[] = { | |
1700 | { 13960000, P_PLL8, 1, 2, 55 }, | |
1701 | { 27000000, P_PXO, 1, 0, 0 }, | |
1702 | { 36570000, P_PLL8, 1, 2, 21 }, | |
1703 | { 38400000, P_PLL8, 2, 1, 5 }, | |
1704 | { 45180000, P_PLL8, 1, 2, 17 }, | |
1705 | { 48000000, P_PLL8, 2, 1, 4 }, | |
1706 | { 54860000, P_PLL8, 1, 1, 7 }, | |
1707 | { 64000000, P_PLL8, 2, 1, 3 }, | |
1708 | { 76800000, P_PLL8, 1, 1, 5 }, | |
1709 | { 96000000, P_PLL8, 2, 1, 2 }, | |
1710 | { 109710000, P_PLL8, 1, 2, 7 }, | |
1711 | { 128000000, P_PLL8, 1, 1, 3 }, | |
1712 | { 153600000, P_PLL8, 1, 2, 5 }, | |
1713 | { 200000000, P_PLL2, 2, 1, 2 }, | |
1714 | { 228570000, P_PLL2, 1, 2, 7 }, | |
1715 | { 266667000, P_PLL2, 1, 1, 3 }, | |
1716 | { 320000000, P_PLL2, 1, 2, 5 }, | |
1717 | { } | |
1718 | }; | |
1719 | ||
1720 | static struct clk_rcg vfe_src = { | |
1721 | .ns_reg = 0x0108, | |
1722 | .mn = { | |
1723 | .mnctr_en_bit = 5, | |
1724 | .mnctr_reset_bit = 7, | |
1725 | .mnctr_mode_shift = 6, | |
1726 | .n_val_shift = 16, | |
1727 | .m_val_shift = 8, | |
1728 | .width = 8, | |
1729 | }, | |
1730 | .p = { | |
1731 | .pre_div_shift = 10, | |
1732 | .pre_div_width = 1, | |
1733 | }, | |
1734 | .s = { | |
1735 | .src_sel_shift = 0, | |
1736 | .parent_map = mmcc_pxo_pll8_pll2_map, | |
1737 | }, | |
1738 | .freq_tbl = clk_tbl_vfe, | |
1739 | .clkr = { | |
1740 | .enable_reg = 0x0104, | |
1741 | .enable_mask = BIT(2), | |
1742 | .hw.init = &(struct clk_init_data){ | |
1743 | .name = "vfe_src", | |
1744 | .parent_names = mmcc_pxo_pll8_pll2, | |
1745 | .num_parents = 3, | |
1746 | .ops = &clk_rcg_ops, | |
1747 | }, | |
1748 | }, | |
1749 | }; | |
1750 | ||
1751 | static struct clk_branch vfe_clk = { | |
1752 | .halt_reg = 0x01cc, | |
1753 | .halt_bit = 6, | |
1754 | .clkr = { | |
1755 | .enable_reg = 0x0104, | |
1756 | .enable_mask = BIT(0), | |
1757 | .hw.init = &(struct clk_init_data){ | |
1758 | .name = "vfe_clk", | |
1759 | .parent_names = (const char *[]){ "vfe_src" }, | |
1760 | .num_parents = 1, | |
1761 | .ops = &clk_branch_ops, | |
1762 | .flags = CLK_SET_RATE_PARENT, | |
1763 | }, | |
1764 | }, | |
1765 | }; | |
1766 | ||
1767 | static struct clk_branch vfe_csi_clk = { | |
1768 | .halt_reg = 0x01cc, | |
1769 | .halt_bit = 8, | |
1770 | .clkr = { | |
1771 | .enable_reg = 0x0104, | |
1772 | .enable_mask = BIT(12), | |
1773 | .hw.init = &(struct clk_init_data){ | |
1774 | .parent_names = (const char *[]){ "vfe_src" }, | |
1775 | .num_parents = 1, | |
1776 | .name = "vfe_csi_clk", | |
1777 | .ops = &clk_branch_ops, | |
1778 | .flags = CLK_SET_RATE_PARENT, | |
1779 | }, | |
1780 | }, | |
1781 | }; | |
1782 | ||
1783 | static struct clk_branch gmem_axi_clk = { | |
1784 | .halt_reg = 0x01d8, | |
1785 | .halt_bit = 6, | |
1786 | .clkr = { | |
1787 | .enable_reg = 0x0018, | |
1788 | .enable_mask = BIT(24), | |
1789 | .hw.init = &(struct clk_init_data){ | |
1790 | .name = "gmem_axi_clk", | |
1791 | .ops = &clk_branch_ops, | |
6d00b56f SB |
1792 | }, |
1793 | }, | |
1794 | }; | |
1795 | ||
1796 | static struct clk_branch ijpeg_axi_clk = { | |
1797 | .hwcg_reg = 0x0018, | |
1798 | .hwcg_bit = 11, | |
1799 | .halt_reg = 0x01d8, | |
1800 | .halt_bit = 4, | |
1801 | .clkr = { | |
1802 | .enable_reg = 0x0018, | |
1803 | .enable_mask = BIT(21), | |
1804 | .hw.init = &(struct clk_init_data){ | |
1805 | .name = "ijpeg_axi_clk", | |
1806 | .ops = &clk_branch_ops, | |
6d00b56f SB |
1807 | }, |
1808 | }, | |
1809 | }; | |
1810 | ||
1811 | static struct clk_branch mmss_imem_axi_clk = { | |
1812 | .hwcg_reg = 0x0018, | |
1813 | .hwcg_bit = 15, | |
1814 | .halt_reg = 0x01d8, | |
1815 | .halt_bit = 7, | |
1816 | .clkr = { | |
1817 | .enable_reg = 0x0018, | |
1818 | .enable_mask = BIT(22), | |
1819 | .hw.init = &(struct clk_init_data){ | |
1820 | .name = "mmss_imem_axi_clk", | |
1821 | .ops = &clk_branch_ops, | |
6d00b56f SB |
1822 | }, |
1823 | }, | |
1824 | }; | |
1825 | ||
1826 | static struct clk_branch jpegd_axi_clk = { | |
1827 | .halt_reg = 0x01d8, | |
1828 | .halt_bit = 5, | |
1829 | .clkr = { | |
1830 | .enable_reg = 0x0018, | |
1831 | .enable_mask = BIT(25), | |
1832 | .hw.init = &(struct clk_init_data){ | |
1833 | .name = "jpegd_axi_clk", | |
1834 | .ops = &clk_branch_ops, | |
6d00b56f SB |
1835 | }, |
1836 | }, | |
1837 | }; | |
1838 | ||
1839 | static struct clk_branch vcodec_axi_b_clk = { | |
1840 | .hwcg_reg = 0x0114, | |
1841 | .hwcg_bit = 22, | |
1842 | .halt_reg = 0x01e8, | |
1843 | .halt_bit = 25, | |
1844 | .clkr = { | |
1845 | .enable_reg = 0x0114, | |
1846 | .enable_mask = BIT(23), | |
1847 | .hw.init = &(struct clk_init_data){ | |
1848 | .name = "vcodec_axi_b_clk", | |
1849 | .ops = &clk_branch_ops, | |
6d00b56f SB |
1850 | }, |
1851 | }, | |
1852 | }; | |
1853 | ||
1854 | static struct clk_branch vcodec_axi_a_clk = { | |
1855 | .hwcg_reg = 0x0114, | |
1856 | .hwcg_bit = 24, | |
1857 | .halt_reg = 0x01e8, | |
1858 | .halt_bit = 26, | |
1859 | .clkr = { | |
1860 | .enable_reg = 0x0114, | |
1861 | .enable_mask = BIT(25), | |
1862 | .hw.init = &(struct clk_init_data){ | |
1863 | .name = "vcodec_axi_a_clk", | |
1864 | .ops = &clk_branch_ops, | |
6d00b56f SB |
1865 | }, |
1866 | }, | |
1867 | }; | |
1868 | ||
1869 | static struct clk_branch vcodec_axi_clk = { | |
1870 | .hwcg_reg = 0x0018, | |
1871 | .hwcg_bit = 13, | |
1872 | .halt_reg = 0x01d8, | |
1873 | .halt_bit = 3, | |
1874 | .clkr = { | |
1875 | .enable_reg = 0x0018, | |
1876 | .enable_mask = BIT(19), | |
1877 | .hw.init = &(struct clk_init_data){ | |
1878 | .name = "vcodec_axi_clk", | |
1879 | .ops = &clk_branch_ops, | |
6d00b56f SB |
1880 | }, |
1881 | }, | |
1882 | }; | |
1883 | ||
1884 | static struct clk_branch vfe_axi_clk = { | |
1885 | .halt_reg = 0x01d8, | |
1886 | .halt_bit = 0, | |
1887 | .clkr = { | |
1888 | .enable_reg = 0x0018, | |
1889 | .enable_mask = BIT(18), | |
1890 | .hw.init = &(struct clk_init_data){ | |
1891 | .name = "vfe_axi_clk", | |
1892 | .ops = &clk_branch_ops, | |
6d00b56f SB |
1893 | }, |
1894 | }, | |
1895 | }; | |
1896 | ||
1897 | static struct clk_branch mdp_axi_clk = { | |
1898 | .hwcg_reg = 0x0018, | |
1899 | .hwcg_bit = 16, | |
1900 | .halt_reg = 0x01d8, | |
1901 | .halt_bit = 8, | |
1902 | .clkr = { | |
1903 | .enable_reg = 0x0018, | |
1904 | .enable_mask = BIT(23), | |
1905 | .hw.init = &(struct clk_init_data){ | |
1906 | .name = "mdp_axi_clk", | |
1907 | .ops = &clk_branch_ops, | |
6d00b56f SB |
1908 | }, |
1909 | }, | |
1910 | }; | |
1911 | ||
1912 | static struct clk_branch rot_axi_clk = { | |
1913 | .hwcg_reg = 0x0020, | |
1914 | .hwcg_bit = 25, | |
1915 | .halt_reg = 0x01d8, | |
1916 | .halt_bit = 2, | |
1917 | .clkr = { | |
1918 | .enable_reg = 0x0020, | |
1919 | .enable_mask = BIT(24), | |
1920 | .hw.init = &(struct clk_init_data){ | |
1921 | .name = "rot_axi_clk", | |
1922 | .ops = &clk_branch_ops, | |
6d00b56f SB |
1923 | }, |
1924 | }, | |
1925 | }; | |
1926 | ||
e216ce60 SB |
1927 | static struct clk_branch vcap_axi_clk = { |
1928 | .halt_reg = 0x0240, | |
1929 | .halt_bit = 20, | |
1930 | .hwcg_reg = 0x0244, | |
1931 | .hwcg_bit = 11, | |
1932 | .clkr = { | |
1933 | .enable_reg = 0x0244, | |
1934 | .enable_mask = BIT(12), | |
1935 | .hw.init = &(struct clk_init_data){ | |
1936 | .name = "vcap_axi_clk", | |
1937 | .ops = &clk_branch_ops, | |
e216ce60 SB |
1938 | }, |
1939 | }, | |
1940 | }; | |
1941 | ||
6d00b56f SB |
1942 | static struct clk_branch vpe_axi_clk = { |
1943 | .hwcg_reg = 0x0020, | |
1944 | .hwcg_bit = 27, | |
1945 | .halt_reg = 0x01d8, | |
1946 | .halt_bit = 1, | |
1947 | .clkr = { | |
1948 | .enable_reg = 0x0020, | |
1949 | .enable_mask = BIT(26), | |
1950 | .hw.init = &(struct clk_init_data){ | |
1951 | .name = "vpe_axi_clk", | |
1952 | .ops = &clk_branch_ops, | |
6d00b56f SB |
1953 | }, |
1954 | }, | |
1955 | }; | |
1956 | ||
1957 | static struct clk_branch gfx3d_axi_clk = { | |
1958 | .hwcg_reg = 0x0244, | |
1959 | .hwcg_bit = 24, | |
1960 | .halt_reg = 0x0240, | |
1961 | .halt_bit = 30, | |
1962 | .clkr = { | |
1963 | .enable_reg = 0x0244, | |
1964 | .enable_mask = BIT(25), | |
1965 | .hw.init = &(struct clk_init_data){ | |
1966 | .name = "gfx3d_axi_clk", | |
1967 | .ops = &clk_branch_ops, | |
6d00b56f SB |
1968 | }, |
1969 | }, | |
1970 | }; | |
1971 | ||
1972 | static struct clk_branch amp_ahb_clk = { | |
1973 | .halt_reg = 0x01dc, | |
1974 | .halt_bit = 18, | |
1975 | .clkr = { | |
1976 | .enable_reg = 0x0008, | |
1977 | .enable_mask = BIT(24), | |
1978 | .hw.init = &(struct clk_init_data){ | |
1979 | .name = "amp_ahb_clk", | |
1980 | .ops = &clk_branch_ops, | |
6d00b56f SB |
1981 | }, |
1982 | }, | |
1983 | }; | |
1984 | ||
1985 | static struct clk_branch csi_ahb_clk = { | |
1986 | .halt_reg = 0x01dc, | |
1987 | .halt_bit = 16, | |
1988 | .clkr = { | |
1989 | .enable_reg = 0x0008, | |
1990 | .enable_mask = BIT(7), | |
1991 | .hw.init = &(struct clk_init_data){ | |
1992 | .name = "csi_ahb_clk", | |
1993 | .ops = &clk_branch_ops, | |
6d00b56f SB |
1994 | }, |
1995 | }, | |
1996 | }; | |
1997 | ||
1998 | static struct clk_branch dsi_m_ahb_clk = { | |
1999 | .halt_reg = 0x01dc, | |
2000 | .halt_bit = 19, | |
2001 | .clkr = { | |
2002 | .enable_reg = 0x0008, | |
2003 | .enable_mask = BIT(9), | |
2004 | .hw.init = &(struct clk_init_data){ | |
2005 | .name = "dsi_m_ahb_clk", | |
2006 | .ops = &clk_branch_ops, | |
6d00b56f SB |
2007 | }, |
2008 | }, | |
2009 | }; | |
2010 | ||
2011 | static struct clk_branch dsi_s_ahb_clk = { | |
2012 | .hwcg_reg = 0x0038, | |
2013 | .hwcg_bit = 20, | |
2014 | .halt_reg = 0x01dc, | |
2015 | .halt_bit = 21, | |
2016 | .clkr = { | |
2017 | .enable_reg = 0x0008, | |
2018 | .enable_mask = BIT(18), | |
2019 | .hw.init = &(struct clk_init_data){ | |
2020 | .name = "dsi_s_ahb_clk", | |
2021 | .ops = &clk_branch_ops, | |
6d00b56f SB |
2022 | }, |
2023 | }, | |
2024 | }; | |
2025 | ||
2026 | static struct clk_branch dsi2_m_ahb_clk = { | |
2027 | .halt_reg = 0x01d8, | |
2028 | .halt_bit = 18, | |
2029 | .clkr = { | |
2030 | .enable_reg = 0x0008, | |
2031 | .enable_mask = BIT(17), | |
2032 | .hw.init = &(struct clk_init_data){ | |
2033 | .name = "dsi2_m_ahb_clk", | |
2034 | .ops = &clk_branch_ops, | |
6d00b56f SB |
2035 | }, |
2036 | }, | |
2037 | }; | |
2038 | ||
2039 | static struct clk_branch dsi2_s_ahb_clk = { | |
2040 | .hwcg_reg = 0x0038, | |
2041 | .hwcg_bit = 15, | |
2042 | .halt_reg = 0x01dc, | |
2043 | .halt_bit = 20, | |
2044 | .clkr = { | |
2045 | .enable_reg = 0x0008, | |
2046 | .enable_mask = BIT(22), | |
2047 | .hw.init = &(struct clk_init_data){ | |
2048 | .name = "dsi2_s_ahb_clk", | |
2049 | .ops = &clk_branch_ops, | |
6d00b56f SB |
2050 | }, |
2051 | }, | |
2052 | }; | |
2053 | ||
5532cfb5 AT |
2054 | static struct clk_rcg dsi1_src = { |
2055 | .ns_reg = 0x0054, | |
2056 | .md_reg = 0x0050, | |
2057 | .mn = { | |
2058 | .mnctr_en_bit = 5, | |
2059 | .mnctr_reset_bit = 7, | |
2060 | .mnctr_mode_shift = 6, | |
2061 | .n_val_shift = 24, | |
2062 | .m_val_shift = 8, | |
2063 | .width = 8, | |
2064 | }, | |
2065 | .p = { | |
2066 | .pre_div_shift = 14, | |
2067 | .pre_div_width = 2, | |
2068 | }, | |
2069 | .s = { | |
2070 | .src_sel_shift = 0, | |
2071 | .parent_map = mmcc_pxo_dsi2_dsi1_map, | |
2072 | }, | |
2073 | .clkr = { | |
2074 | .enable_reg = 0x004c, | |
2075 | .enable_mask = BIT(2), | |
2076 | .hw.init = &(struct clk_init_data){ | |
2077 | .name = "dsi1_src", | |
2078 | .parent_names = mmcc_pxo_dsi2_dsi1, | |
2079 | .num_parents = 3, | |
2080 | .ops = &clk_rcg_bypass2_ops, | |
2081 | .flags = CLK_SET_RATE_PARENT, | |
2082 | }, | |
2083 | }, | |
2084 | }; | |
2085 | ||
2086 | static struct clk_branch dsi1_clk = { | |
2087 | .halt_reg = 0x01d0, | |
e5bf1991 | 2088 | .halt_bit = 2, |
5532cfb5 AT |
2089 | .clkr = { |
2090 | .enable_reg = 0x004c, | |
2091 | .enable_mask = BIT(0), | |
2092 | .hw.init = &(struct clk_init_data){ | |
2093 | .name = "dsi1_clk", | |
2094 | .parent_names = (const char *[]){ "dsi1_src" }, | |
2095 | .num_parents = 1, | |
2096 | .ops = &clk_branch_ops, | |
2097 | .flags = CLK_SET_RATE_PARENT, | |
2098 | }, | |
2099 | }, | |
2100 | }; | |
2101 | ||
2102 | static struct clk_rcg dsi2_src = { | |
2103 | .ns_reg = 0x012c, | |
2104 | .md_reg = 0x00a8, | |
2105 | .mn = { | |
2106 | .mnctr_en_bit = 5, | |
2107 | .mnctr_reset_bit = 7, | |
2108 | .mnctr_mode_shift = 6, | |
2109 | .n_val_shift = 24, | |
2110 | .m_val_shift = 8, | |
2111 | .width = 8, | |
2112 | }, | |
2113 | .p = { | |
2114 | .pre_div_shift = 14, | |
2115 | .pre_div_width = 2, | |
2116 | }, | |
2117 | .s = { | |
2118 | .src_sel_shift = 0, | |
2119 | .parent_map = mmcc_pxo_dsi2_dsi1_map, | |
2120 | }, | |
2121 | .clkr = { | |
2122 | .enable_reg = 0x003c, | |
2123 | .enable_mask = BIT(2), | |
2124 | .hw.init = &(struct clk_init_data){ | |
2125 | .name = "dsi2_src", | |
2126 | .parent_names = mmcc_pxo_dsi2_dsi1, | |
2127 | .num_parents = 3, | |
2128 | .ops = &clk_rcg_bypass2_ops, | |
2129 | .flags = CLK_SET_RATE_PARENT, | |
2130 | }, | |
2131 | }, | |
2132 | }; | |
2133 | ||
2134 | static struct clk_branch dsi2_clk = { | |
2135 | .halt_reg = 0x01d0, | |
e5bf1991 | 2136 | .halt_bit = 20, |
5532cfb5 AT |
2137 | .clkr = { |
2138 | .enable_reg = 0x003c, | |
2139 | .enable_mask = BIT(0), | |
2140 | .hw.init = &(struct clk_init_data){ | |
2141 | .name = "dsi2_clk", | |
2142 | .parent_names = (const char *[]){ "dsi2_src" }, | |
2143 | .num_parents = 1, | |
2144 | .ops = &clk_branch_ops, | |
2145 | .flags = CLK_SET_RATE_PARENT, | |
2146 | }, | |
2147 | }, | |
2148 | }; | |
2149 | ||
2150 | static struct clk_rcg dsi1_byte_src = { | |
2151 | .ns_reg = 0x00b0, | |
2152 | .p = { | |
2153 | .pre_div_shift = 12, | |
2154 | .pre_div_width = 4, | |
2155 | }, | |
2156 | .s = { | |
2157 | .src_sel_shift = 0, | |
2158 | .parent_map = mmcc_pxo_dsi1_dsi2_byte_map, | |
2159 | }, | |
2160 | .clkr = { | |
2161 | .enable_reg = 0x0090, | |
2162 | .enable_mask = BIT(2), | |
2163 | .hw.init = &(struct clk_init_data){ | |
2164 | .name = "dsi1_byte_src", | |
2165 | .parent_names = mmcc_pxo_dsi1_dsi2_byte, | |
2166 | .num_parents = 3, | |
2167 | .ops = &clk_rcg_bypass2_ops, | |
2168 | .flags = CLK_SET_RATE_PARENT, | |
2169 | }, | |
2170 | }, | |
2171 | }; | |
2172 | ||
2173 | static struct clk_branch dsi1_byte_clk = { | |
2174 | .halt_reg = 0x01cc, | |
2175 | .halt_bit = 21, | |
2176 | .clkr = { | |
2177 | .enable_reg = 0x0090, | |
2178 | .enable_mask = BIT(0), | |
2179 | .hw.init = &(struct clk_init_data){ | |
2180 | .name = "dsi1_byte_clk", | |
2181 | .parent_names = (const char *[]){ "dsi1_byte_src" }, | |
2182 | .num_parents = 1, | |
2183 | .ops = &clk_branch_ops, | |
2184 | .flags = CLK_SET_RATE_PARENT, | |
2185 | }, | |
2186 | }, | |
2187 | }; | |
2188 | ||
2189 | static struct clk_rcg dsi2_byte_src = { | |
2190 | .ns_reg = 0x012c, | |
2191 | .p = { | |
2192 | .pre_div_shift = 12, | |
2193 | .pre_div_width = 4, | |
2194 | }, | |
2195 | .s = { | |
2196 | .src_sel_shift = 0, | |
2197 | .parent_map = mmcc_pxo_dsi1_dsi2_byte_map, | |
2198 | }, | |
2199 | .clkr = { | |
2200 | .enable_reg = 0x0130, | |
2201 | .enable_mask = BIT(2), | |
2202 | .hw.init = &(struct clk_init_data){ | |
2203 | .name = "dsi2_byte_src", | |
2204 | .parent_names = mmcc_pxo_dsi1_dsi2_byte, | |
2205 | .num_parents = 3, | |
2206 | .ops = &clk_rcg_bypass2_ops, | |
2207 | .flags = CLK_SET_RATE_PARENT, | |
2208 | }, | |
2209 | }, | |
2210 | }; | |
2211 | ||
2212 | static struct clk_branch dsi2_byte_clk = { | |
2213 | .halt_reg = 0x01cc, | |
2214 | .halt_bit = 20, | |
2215 | .clkr = { | |
2216 | .enable_reg = 0x00b4, | |
2217 | .enable_mask = BIT(0), | |
2218 | .hw.init = &(struct clk_init_data){ | |
2219 | .name = "dsi2_byte_clk", | |
2220 | .parent_names = (const char *[]){ "dsi2_byte_src" }, | |
2221 | .num_parents = 1, | |
2222 | .ops = &clk_branch_ops, | |
2223 | .flags = CLK_SET_RATE_PARENT, | |
2224 | }, | |
2225 | }, | |
2226 | }; | |
2227 | ||
2228 | static struct clk_rcg dsi1_esc_src = { | |
2229 | .ns_reg = 0x0011c, | |
2230 | .p = { | |
2231 | .pre_div_shift = 12, | |
2232 | .pre_div_width = 4, | |
2233 | }, | |
2234 | .s = { | |
2235 | .src_sel_shift = 0, | |
2236 | .parent_map = mmcc_pxo_dsi1_dsi2_byte_map, | |
2237 | }, | |
2238 | .clkr = { | |
2239 | .enable_reg = 0x00cc, | |
2240 | .enable_mask = BIT(2), | |
2241 | .hw.init = &(struct clk_init_data){ | |
2242 | .name = "dsi1_esc_src", | |
2243 | .parent_names = mmcc_pxo_dsi1_dsi2_byte, | |
2244 | .num_parents = 3, | |
2245 | .ops = &clk_rcg_esc_ops, | |
2246 | }, | |
2247 | }, | |
2248 | }; | |
2249 | ||
2250 | static struct clk_branch dsi1_esc_clk = { | |
2251 | .halt_reg = 0x01e8, | |
2252 | .halt_bit = 1, | |
2253 | .clkr = { | |
2254 | .enable_reg = 0x00cc, | |
2255 | .enable_mask = BIT(0), | |
2256 | .hw.init = &(struct clk_init_data){ | |
2257 | .name = "dsi1_esc_clk", | |
2258 | .parent_names = (const char *[]){ "dsi1_esc_src" }, | |
2259 | .num_parents = 1, | |
2260 | .ops = &clk_branch_ops, | |
2261 | .flags = CLK_SET_RATE_PARENT, | |
2262 | }, | |
2263 | }, | |
2264 | }; | |
2265 | ||
2266 | static struct clk_rcg dsi2_esc_src = { | |
2267 | .ns_reg = 0x0150, | |
2268 | .p = { | |
2269 | .pre_div_shift = 12, | |
2270 | .pre_div_width = 4, | |
2271 | }, | |
2272 | .s = { | |
2273 | .src_sel_shift = 0, | |
2274 | .parent_map = mmcc_pxo_dsi1_dsi2_byte_map, | |
2275 | }, | |
2276 | .clkr = { | |
2277 | .enable_reg = 0x013c, | |
2278 | .enable_mask = BIT(2), | |
2279 | .hw.init = &(struct clk_init_data){ | |
2280 | .name = "dsi2_esc_src", | |
2281 | .parent_names = mmcc_pxo_dsi1_dsi2_byte, | |
2282 | .num_parents = 3, | |
2283 | .ops = &clk_rcg_esc_ops, | |
2284 | }, | |
2285 | }, | |
2286 | }; | |
2287 | ||
2288 | static struct clk_branch dsi2_esc_clk = { | |
2289 | .halt_reg = 0x01e8, | |
2290 | .halt_bit = 3, | |
2291 | .clkr = { | |
2292 | .enable_reg = 0x013c, | |
2293 | .enable_mask = BIT(0), | |
2294 | .hw.init = &(struct clk_init_data){ | |
2295 | .name = "dsi2_esc_clk", | |
2296 | .parent_names = (const char *[]){ "dsi2_esc_src" }, | |
2297 | .num_parents = 1, | |
2298 | .ops = &clk_branch_ops, | |
2299 | .flags = CLK_SET_RATE_PARENT, | |
2300 | }, | |
2301 | }, | |
2302 | }; | |
2303 | ||
2304 | static struct clk_rcg dsi1_pixel_src = { | |
2305 | .ns_reg = 0x0138, | |
2306 | .md_reg = 0x0134, | |
2307 | .mn = { | |
2308 | .mnctr_en_bit = 5, | |
2309 | .mnctr_reset_bit = 7, | |
2310 | .mnctr_mode_shift = 6, | |
2311 | .n_val_shift = 16, | |
2312 | .m_val_shift = 8, | |
2313 | .width = 8, | |
2314 | }, | |
2315 | .p = { | |
2316 | .pre_div_shift = 12, | |
2317 | .pre_div_width = 4, | |
2318 | }, | |
2319 | .s = { | |
2320 | .src_sel_shift = 0, | |
2321 | .parent_map = mmcc_pxo_dsi2_dsi1_map, | |
2322 | }, | |
2323 | .clkr = { | |
2324 | .enable_reg = 0x0130, | |
2325 | .enable_mask = BIT(2), | |
2326 | .hw.init = &(struct clk_init_data){ | |
2327 | .name = "dsi1_pixel_src", | |
2328 | .parent_names = mmcc_pxo_dsi2_dsi1, | |
2329 | .num_parents = 3, | |
2330 | .ops = &clk_rcg_pixel_ops, | |
2331 | }, | |
2332 | }, | |
2333 | }; | |
2334 | ||
2335 | static struct clk_branch dsi1_pixel_clk = { | |
2336 | .halt_reg = 0x01d0, | |
2337 | .halt_bit = 6, | |
2338 | .clkr = { | |
2339 | .enable_reg = 0x0130, | |
2340 | .enable_mask = BIT(0), | |
2341 | .hw.init = &(struct clk_init_data){ | |
2342 | .name = "mdp_pclk1_clk", | |
2343 | .parent_names = (const char *[]){ "dsi1_pixel_src" }, | |
2344 | .num_parents = 1, | |
2345 | .ops = &clk_branch_ops, | |
2346 | .flags = CLK_SET_RATE_PARENT, | |
2347 | }, | |
2348 | }, | |
2349 | }; | |
2350 | ||
2351 | static struct clk_rcg dsi2_pixel_src = { | |
2352 | .ns_reg = 0x00e4, | |
2353 | .md_reg = 0x00b8, | |
2354 | .mn = { | |
2355 | .mnctr_en_bit = 5, | |
2356 | .mnctr_reset_bit = 7, | |
2357 | .mnctr_mode_shift = 6, | |
2358 | .n_val_shift = 16, | |
2359 | .m_val_shift = 8, | |
2360 | .width = 8, | |
2361 | }, | |
2362 | .p = { | |
2363 | .pre_div_shift = 12, | |
2364 | .pre_div_width = 4, | |
2365 | }, | |
2366 | .s = { | |
2367 | .src_sel_shift = 0, | |
2368 | .parent_map = mmcc_pxo_dsi2_dsi1_map, | |
2369 | }, | |
2370 | .clkr = { | |
2371 | .enable_reg = 0x0094, | |
2372 | .enable_mask = BIT(2), | |
2373 | .hw.init = &(struct clk_init_data){ | |
2374 | .name = "dsi2_pixel_src", | |
2375 | .parent_names = mmcc_pxo_dsi2_dsi1, | |
2376 | .num_parents = 3, | |
2377 | .ops = &clk_rcg_pixel_ops, | |
2378 | }, | |
2379 | }, | |
2380 | }; | |
2381 | ||
2382 | static struct clk_branch dsi2_pixel_clk = { | |
2383 | .halt_reg = 0x01d0, | |
2384 | .halt_bit = 19, | |
2385 | .clkr = { | |
2386 | .enable_reg = 0x0094, | |
2387 | .enable_mask = BIT(0), | |
2388 | .hw.init = &(struct clk_init_data){ | |
2389 | .name = "mdp_pclk2_clk", | |
2390 | .parent_names = (const char *[]){ "dsi2_pixel_src" }, | |
2391 | .num_parents = 1, | |
2392 | .ops = &clk_branch_ops, | |
2393 | .flags = CLK_SET_RATE_PARENT, | |
2394 | }, | |
2395 | }, | |
2396 | }; | |
2397 | ||
6d00b56f SB |
2398 | static struct clk_branch gfx2d0_ahb_clk = { |
2399 | .hwcg_reg = 0x0038, | |
2400 | .hwcg_bit = 28, | |
2401 | .halt_reg = 0x01dc, | |
2402 | .halt_bit = 2, | |
2403 | .clkr = { | |
2404 | .enable_reg = 0x0008, | |
2405 | .enable_mask = BIT(19), | |
2406 | .hw.init = &(struct clk_init_data){ | |
2407 | .name = "gfx2d0_ahb_clk", | |
2408 | .ops = &clk_branch_ops, | |
6d00b56f SB |
2409 | }, |
2410 | }, | |
2411 | }; | |
2412 | ||
2413 | static struct clk_branch gfx2d1_ahb_clk = { | |
2414 | .hwcg_reg = 0x0038, | |
2415 | .hwcg_bit = 29, | |
2416 | .halt_reg = 0x01dc, | |
2417 | .halt_bit = 3, | |
2418 | .clkr = { | |
2419 | .enable_reg = 0x0008, | |
2420 | .enable_mask = BIT(2), | |
2421 | .hw.init = &(struct clk_init_data){ | |
2422 | .name = "gfx2d1_ahb_clk", | |
2423 | .ops = &clk_branch_ops, | |
6d00b56f SB |
2424 | }, |
2425 | }, | |
2426 | }; | |
2427 | ||
2428 | static struct clk_branch gfx3d_ahb_clk = { | |
2429 | .hwcg_reg = 0x0038, | |
2430 | .hwcg_bit = 27, | |
2431 | .halt_reg = 0x01dc, | |
2432 | .halt_bit = 4, | |
2433 | .clkr = { | |
2434 | .enable_reg = 0x0008, | |
2435 | .enable_mask = BIT(3), | |
2436 | .hw.init = &(struct clk_init_data){ | |
2437 | .name = "gfx3d_ahb_clk", | |
2438 | .ops = &clk_branch_ops, | |
6d00b56f SB |
2439 | }, |
2440 | }, | |
2441 | }; | |
2442 | ||
2443 | static struct clk_branch hdmi_m_ahb_clk = { | |
2444 | .hwcg_reg = 0x0038, | |
2445 | .hwcg_bit = 21, | |
2446 | .halt_reg = 0x01dc, | |
2447 | .halt_bit = 5, | |
2448 | .clkr = { | |
2449 | .enable_reg = 0x0008, | |
2450 | .enable_mask = BIT(14), | |
2451 | .hw.init = &(struct clk_init_data){ | |
2452 | .name = "hdmi_m_ahb_clk", | |
2453 | .ops = &clk_branch_ops, | |
6d00b56f SB |
2454 | }, |
2455 | }, | |
2456 | }; | |
2457 | ||
2458 | static struct clk_branch hdmi_s_ahb_clk = { | |
2459 | .hwcg_reg = 0x0038, | |
2460 | .hwcg_bit = 22, | |
2461 | .halt_reg = 0x01dc, | |
2462 | .halt_bit = 6, | |
2463 | .clkr = { | |
2464 | .enable_reg = 0x0008, | |
2465 | .enable_mask = BIT(4), | |
2466 | .hw.init = &(struct clk_init_data){ | |
2467 | .name = "hdmi_s_ahb_clk", | |
2468 | .ops = &clk_branch_ops, | |
6d00b56f SB |
2469 | }, |
2470 | }, | |
2471 | }; | |
2472 | ||
2473 | static struct clk_branch ijpeg_ahb_clk = { | |
2474 | .halt_reg = 0x01dc, | |
2475 | .halt_bit = 9, | |
2476 | .clkr = { | |
2477 | .enable_reg = 0x0008, | |
2478 | .enable_mask = BIT(5), | |
2479 | .hw.init = &(struct clk_init_data){ | |
2480 | .name = "ijpeg_ahb_clk", | |
2481 | .ops = &clk_branch_ops, | |
6d00b56f SB |
2482 | }, |
2483 | }, | |
2484 | }; | |
2485 | ||
2486 | static struct clk_branch mmss_imem_ahb_clk = { | |
2487 | .hwcg_reg = 0x0038, | |
2488 | .hwcg_bit = 12, | |
2489 | .halt_reg = 0x01dc, | |
2490 | .halt_bit = 10, | |
2491 | .clkr = { | |
2492 | .enable_reg = 0x0008, | |
2493 | .enable_mask = BIT(6), | |
2494 | .hw.init = &(struct clk_init_data){ | |
2495 | .name = "mmss_imem_ahb_clk", | |
2496 | .ops = &clk_branch_ops, | |
6d00b56f SB |
2497 | }, |
2498 | }, | |
2499 | }; | |
2500 | ||
2501 | static struct clk_branch jpegd_ahb_clk = { | |
2502 | .halt_reg = 0x01dc, | |
2503 | .halt_bit = 7, | |
2504 | .clkr = { | |
2505 | .enable_reg = 0x0008, | |
2506 | .enable_mask = BIT(21), | |
2507 | .hw.init = &(struct clk_init_data){ | |
2508 | .name = "jpegd_ahb_clk", | |
2509 | .ops = &clk_branch_ops, | |
6d00b56f SB |
2510 | }, |
2511 | }, | |
2512 | }; | |
2513 | ||
2514 | static struct clk_branch mdp_ahb_clk = { | |
2515 | .halt_reg = 0x01dc, | |
2516 | .halt_bit = 11, | |
2517 | .clkr = { | |
2518 | .enable_reg = 0x0008, | |
2519 | .enable_mask = BIT(10), | |
2520 | .hw.init = &(struct clk_init_data){ | |
2521 | .name = "mdp_ahb_clk", | |
2522 | .ops = &clk_branch_ops, | |
6d00b56f SB |
2523 | }, |
2524 | }, | |
2525 | }; | |
2526 | ||
2527 | static struct clk_branch rot_ahb_clk = { | |
2528 | .halt_reg = 0x01dc, | |
2529 | .halt_bit = 13, | |
2530 | .clkr = { | |
2531 | .enable_reg = 0x0008, | |
2532 | .enable_mask = BIT(12), | |
2533 | .hw.init = &(struct clk_init_data){ | |
2534 | .name = "rot_ahb_clk", | |
2535 | .ops = &clk_branch_ops, | |
6d00b56f SB |
2536 | }, |
2537 | }, | |
2538 | }; | |
2539 | ||
2540 | static struct clk_branch smmu_ahb_clk = { | |
2541 | .hwcg_reg = 0x0008, | |
2542 | .hwcg_bit = 26, | |
2543 | .halt_reg = 0x01dc, | |
2544 | .halt_bit = 22, | |
2545 | .clkr = { | |
2546 | .enable_reg = 0x0008, | |
2547 | .enable_mask = BIT(15), | |
2548 | .hw.init = &(struct clk_init_data){ | |
2549 | .name = "smmu_ahb_clk", | |
2550 | .ops = &clk_branch_ops, | |
6d00b56f SB |
2551 | }, |
2552 | }, | |
2553 | }; | |
2554 | ||
2555 | static struct clk_branch tv_enc_ahb_clk = { | |
2556 | .halt_reg = 0x01dc, | |
2557 | .halt_bit = 23, | |
2558 | .clkr = { | |
2559 | .enable_reg = 0x0008, | |
2560 | .enable_mask = BIT(25), | |
2561 | .hw.init = &(struct clk_init_data){ | |
2562 | .name = "tv_enc_ahb_clk", | |
2563 | .ops = &clk_branch_ops, | |
6d00b56f SB |
2564 | }, |
2565 | }, | |
2566 | }; | |
2567 | ||
e216ce60 SB |
2568 | static struct clk_branch vcap_ahb_clk = { |
2569 | .halt_reg = 0x0240, | |
2570 | .halt_bit = 23, | |
2571 | .clkr = { | |
2572 | .enable_reg = 0x0248, | |
2573 | .enable_mask = BIT(1), | |
2574 | .hw.init = &(struct clk_init_data){ | |
2575 | .name = "vcap_ahb_clk", | |
2576 | .ops = &clk_branch_ops, | |
e216ce60 SB |
2577 | }, |
2578 | }, | |
2579 | }; | |
2580 | ||
6d00b56f SB |
2581 | static struct clk_branch vcodec_ahb_clk = { |
2582 | .hwcg_reg = 0x0038, | |
2583 | .hwcg_bit = 26, | |
2584 | .halt_reg = 0x01dc, | |
2585 | .halt_bit = 12, | |
2586 | .clkr = { | |
2587 | .enable_reg = 0x0008, | |
2588 | .enable_mask = BIT(11), | |
2589 | .hw.init = &(struct clk_init_data){ | |
2590 | .name = "vcodec_ahb_clk", | |
2591 | .ops = &clk_branch_ops, | |
6d00b56f SB |
2592 | }, |
2593 | }, | |
2594 | }; | |
2595 | ||
2596 | static struct clk_branch vfe_ahb_clk = { | |
2597 | .halt_reg = 0x01dc, | |
2598 | .halt_bit = 14, | |
2599 | .clkr = { | |
2600 | .enable_reg = 0x0008, | |
2601 | .enable_mask = BIT(13), | |
2602 | .hw.init = &(struct clk_init_data){ | |
2603 | .name = "vfe_ahb_clk", | |
2604 | .ops = &clk_branch_ops, | |
6d00b56f SB |
2605 | }, |
2606 | }, | |
2607 | }; | |
2608 | ||
2609 | static struct clk_branch vpe_ahb_clk = { | |
2610 | .halt_reg = 0x01dc, | |
2611 | .halt_bit = 15, | |
2612 | .clkr = { | |
2613 | .enable_reg = 0x0008, | |
2614 | .enable_mask = BIT(16), | |
2615 | .hw.init = &(struct clk_init_data){ | |
2616 | .name = "vpe_ahb_clk", | |
2617 | .ops = &clk_branch_ops, | |
6d00b56f SB |
2618 | }, |
2619 | }, | |
2620 | }; | |
2621 | ||
2622 | static struct clk_regmap *mmcc_msm8960_clks[] = { | |
2623 | [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr, | |
2624 | [AMP_AHB_CLK] = &_ahb_clk.clkr, | |
2625 | [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr, | |
2626 | [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr, | |
2627 | [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr, | |
2628 | [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr, | |
2629 | [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr, | |
2630 | [VPE_AHB_CLK] = &vpe_ahb_clk.clkr, | |
2631 | [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr, | |
2632 | [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr, | |
2633 | [VFE_AHB_CLK] = &vfe_ahb_clk.clkr, | |
2634 | [ROT_AHB_CLK] = &rot_ahb_clk.clkr, | |
2635 | [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr, | |
2636 | [MDP_AHB_CLK] = &mdp_ahb_clk.clkr, | |
2637 | [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr, | |
2638 | [CSI_AHB_CLK] = &csi_ahb_clk.clkr, | |
2639 | [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr, | |
2640 | [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr, | |
2641 | [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr, | |
2642 | [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr, | |
2643 | [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr, | |
2644 | [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr, | |
2645 | [GMEM_AXI_CLK] = &gmem_axi_clk.clkr, | |
2646 | [MDP_AXI_CLK] = &mdp_axi_clk.clkr, | |
2647 | [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr, | |
2648 | [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr, | |
2649 | [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr, | |
2650 | [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr, | |
2651 | [VFE_AXI_CLK] = &vfe_axi_clk.clkr, | |
2652 | [VPE_AXI_CLK] = &vpe_axi_clk.clkr, | |
2653 | [ROT_AXI_CLK] = &rot_axi_clk.clkr, | |
2654 | [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr, | |
2655 | [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr, | |
2656 | [CSI0_SRC] = &csi0_src.clkr, | |
2657 | [CSI0_CLK] = &csi0_clk.clkr, | |
2658 | [CSI0_PHY_CLK] = &csi0_phy_clk.clkr, | |
2659 | [CSI1_SRC] = &csi1_src.clkr, | |
2660 | [CSI1_CLK] = &csi1_clk.clkr, | |
2661 | [CSI1_PHY_CLK] = &csi1_phy_clk.clkr, | |
2662 | [CSI2_SRC] = &csi2_src.clkr, | |
2663 | [CSI2_CLK] = &csi2_clk.clkr, | |
2664 | [CSI2_PHY_CLK] = &csi2_phy_clk.clkr, | |
5532cfb5 AT |
2665 | [DSI_SRC] = &dsi1_src.clkr, |
2666 | [DSI_CLK] = &dsi1_clk.clkr, | |
6d00b56f SB |
2667 | [CSI_PIX_CLK] = &csi_pix_clk.clkr, |
2668 | [CSI_RDI_CLK] = &csi_rdi_clk.clkr, | |
2669 | [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr, | |
2670 | [HDMI_APP_CLK] = &hdmi_app_clk.clkr, | |
2671 | [CSI_PIX1_CLK] = &csi_pix1_clk.clkr, | |
2672 | [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr, | |
2673 | [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr, | |
2674 | [GFX2D0_SRC] = &gfx2d0_src.clkr, | |
2675 | [GFX2D0_CLK] = &gfx2d0_clk.clkr, | |
2676 | [GFX2D1_SRC] = &gfx2d1_src.clkr, | |
2677 | [GFX2D1_CLK] = &gfx2d1_clk.clkr, | |
2678 | [GFX3D_SRC] = &gfx3d_src.clkr, | |
2679 | [GFX3D_CLK] = &gfx3d_clk.clkr, | |
2680 | [IJPEG_SRC] = &ijpeg_src.clkr, | |
2681 | [IJPEG_CLK] = &ijpeg_clk.clkr, | |
2682 | [JPEGD_SRC] = &jpegd_src.clkr, | |
2683 | [JPEGD_CLK] = &jpegd_clk.clkr, | |
2684 | [MDP_SRC] = &mdp_src.clkr, | |
2685 | [MDP_CLK] = &mdp_clk.clkr, | |
2686 | [MDP_LUT_CLK] = &mdp_lut_clk.clkr, | |
5532cfb5 AT |
2687 | [DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr, |
2688 | [DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr, | |
2689 | [DSI2_SRC] = &dsi2_src.clkr, | |
2690 | [DSI2_CLK] = &dsi2_clk.clkr, | |
2691 | [DSI1_BYTE_SRC] = &dsi1_byte_src.clkr, | |
2692 | [DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr, | |
2693 | [DSI2_BYTE_SRC] = &dsi2_byte_src.clkr, | |
2694 | [DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr, | |
2695 | [DSI1_ESC_SRC] = &dsi1_esc_src.clkr, | |
2696 | [DSI1_ESC_CLK] = &dsi1_esc_clk.clkr, | |
2697 | [DSI2_ESC_SRC] = &dsi2_esc_src.clkr, | |
2698 | [DSI2_ESC_CLK] = &dsi2_esc_clk.clkr, | |
6d00b56f SB |
2699 | [ROT_SRC] = &rot_src.clkr, |
2700 | [ROT_CLK] = &rot_clk.clkr, | |
2701 | [TV_ENC_CLK] = &tv_enc_clk.clkr, | |
2702 | [TV_DAC_CLK] = &tv_dac_clk.clkr, | |
2703 | [HDMI_TV_CLK] = &hdmi_tv_clk.clkr, | |
2704 | [MDP_TV_CLK] = &mdp_tv_clk.clkr, | |
2705 | [TV_SRC] = &tv_src.clkr, | |
2706 | [VCODEC_SRC] = &vcodec_src.clkr, | |
2707 | [VCODEC_CLK] = &vcodec_clk.clkr, | |
2708 | [VFE_SRC] = &vfe_src.clkr, | |
2709 | [VFE_CLK] = &vfe_clk.clkr, | |
2710 | [VFE_CSI_CLK] = &vfe_csi_clk.clkr, | |
2711 | [VPE_SRC] = &vpe_src.clkr, | |
2712 | [VPE_CLK] = &vpe_clk.clkr, | |
5532cfb5 AT |
2713 | [DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr, |
2714 | [DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr, | |
6d00b56f SB |
2715 | [CAMCLK0_SRC] = &camclk0_src.clkr, |
2716 | [CAMCLK0_CLK] = &camclk0_clk.clkr, | |
2717 | [CAMCLK1_SRC] = &camclk1_src.clkr, | |
2718 | [CAMCLK1_CLK] = &camclk1_clk.clkr, | |
2719 | [CAMCLK2_SRC] = &camclk2_src.clkr, | |
2720 | [CAMCLK2_CLK] = &camclk2_clk.clkr, | |
2721 | [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr, | |
2722 | [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr, | |
2723 | [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr, | |
2724 | [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr, | |
2725 | [PLL2] = &pll2.clkr, | |
2726 | }; | |
2727 | ||
2728 | static const struct qcom_reset_map mmcc_msm8960_resets[] = { | |
2729 | [VPE_AXI_RESET] = { 0x0208, 15 }, | |
2730 | [IJPEG_AXI_RESET] = { 0x0208, 14 }, | |
2731 | [MPD_AXI_RESET] = { 0x0208, 13 }, | |
2732 | [VFE_AXI_RESET] = { 0x0208, 9 }, | |
2733 | [SP_AXI_RESET] = { 0x0208, 8 }, | |
2734 | [VCODEC_AXI_RESET] = { 0x0208, 7 }, | |
2735 | [ROT_AXI_RESET] = { 0x0208, 6 }, | |
2736 | [VCODEC_AXI_A_RESET] = { 0x0208, 5 }, | |
2737 | [VCODEC_AXI_B_RESET] = { 0x0208, 4 }, | |
2738 | [FAB_S3_AXI_RESET] = { 0x0208, 3 }, | |
2739 | [FAB_S2_AXI_RESET] = { 0x0208, 2 }, | |
2740 | [FAB_S1_AXI_RESET] = { 0x0208, 1 }, | |
2741 | [FAB_S0_AXI_RESET] = { 0x0208 }, | |
2742 | [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 }, | |
2743 | [SMMU_VPE_AHB_RESET] = { 0x020c, 30 }, | |
2744 | [SMMU_VFE_AHB_RESET] = { 0x020c, 29 }, | |
2745 | [SMMU_ROT_AHB_RESET] = { 0x020c, 28 }, | |
2746 | [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 }, | |
2747 | [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 }, | |
2748 | [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 }, | |
2749 | [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 }, | |
2750 | [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 }, | |
2751 | [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 }, | |
2752 | [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 }, | |
2753 | [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 }, | |
2754 | [APU_AHB_RESET] = { 0x020c, 18 }, | |
2755 | [CSI_AHB_RESET] = { 0x020c, 17 }, | |
2756 | [TV_ENC_AHB_RESET] = { 0x020c, 15 }, | |
2757 | [VPE_AHB_RESET] = { 0x020c, 14 }, | |
2758 | [FABRIC_AHB_RESET] = { 0x020c, 13 }, | |
2759 | [GFX2D0_AHB_RESET] = { 0x020c, 12 }, | |
2760 | [GFX2D1_AHB_RESET] = { 0x020c, 11 }, | |
2761 | [GFX3D_AHB_RESET] = { 0x020c, 10 }, | |
2762 | [HDMI_AHB_RESET] = { 0x020c, 9 }, | |
2763 | [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 }, | |
2764 | [IJPEG_AHB_RESET] = { 0x020c, 7 }, | |
2765 | [DSI_M_AHB_RESET] = { 0x020c, 6 }, | |
2766 | [DSI_S_AHB_RESET] = { 0x020c, 5 }, | |
2767 | [JPEGD_AHB_RESET] = { 0x020c, 4 }, | |
2768 | [MDP_AHB_RESET] = { 0x020c, 3 }, | |
2769 | [ROT_AHB_RESET] = { 0x020c, 2 }, | |
2770 | [VCODEC_AHB_RESET] = { 0x020c, 1 }, | |
2771 | [VFE_AHB_RESET] = { 0x020c, 0 }, | |
2772 | [DSI2_M_AHB_RESET] = { 0x0210, 31 }, | |
2773 | [DSI2_S_AHB_RESET] = { 0x0210, 30 }, | |
2774 | [CSIPHY2_RESET] = { 0x0210, 29 }, | |
2775 | [CSI_PIX1_RESET] = { 0x0210, 28 }, | |
2776 | [CSIPHY0_RESET] = { 0x0210, 27 }, | |
2777 | [CSIPHY1_RESET] = { 0x0210, 26 }, | |
2778 | [DSI2_RESET] = { 0x0210, 25 }, | |
2779 | [VFE_CSI_RESET] = { 0x0210, 24 }, | |
2780 | [MDP_RESET] = { 0x0210, 21 }, | |
2781 | [AMP_RESET] = { 0x0210, 20 }, | |
2782 | [JPEGD_RESET] = { 0x0210, 19 }, | |
2783 | [CSI1_RESET] = { 0x0210, 18 }, | |
2784 | [VPE_RESET] = { 0x0210, 17 }, | |
2785 | [MMSS_FABRIC_RESET] = { 0x0210, 16 }, | |
2786 | [VFE_RESET] = { 0x0210, 15 }, | |
2787 | [GFX2D0_RESET] = { 0x0210, 14 }, | |
2788 | [GFX2D1_RESET] = { 0x0210, 13 }, | |
2789 | [GFX3D_RESET] = { 0x0210, 12 }, | |
2790 | [HDMI_RESET] = { 0x0210, 11 }, | |
2791 | [MMSS_IMEM_RESET] = { 0x0210, 10 }, | |
2792 | [IJPEG_RESET] = { 0x0210, 9 }, | |
2793 | [CSI0_RESET] = { 0x0210, 8 }, | |
2794 | [DSI_RESET] = { 0x0210, 7 }, | |
2795 | [VCODEC_RESET] = { 0x0210, 6 }, | |
2796 | [MDP_TV_RESET] = { 0x0210, 4 }, | |
2797 | [MDP_VSYNC_RESET] = { 0x0210, 3 }, | |
2798 | [ROT_RESET] = { 0x0210, 2 }, | |
2799 | [TV_HDMI_RESET] = { 0x0210, 1 }, | |
2800 | [TV_ENC_RESET] = { 0x0210 }, | |
2801 | [CSI2_RESET] = { 0x0214, 2 }, | |
2802 | [CSI_RDI1_RESET] = { 0x0214, 1 }, | |
2803 | [CSI_RDI2_RESET] = { 0x0214 }, | |
2804 | }; | |
2805 | ||
e216ce60 SB |
2806 | static struct clk_regmap *mmcc_apq8064_clks[] = { |
2807 | [AMP_AHB_CLK] = &_ahb_clk.clkr, | |
2808 | [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr, | |
2809 | [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr, | |
2810 | [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr, | |
2811 | [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr, | |
2812 | [VPE_AHB_CLK] = &vpe_ahb_clk.clkr, | |
2813 | [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr, | |
2814 | [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr, | |
2815 | [VFE_AHB_CLK] = &vfe_ahb_clk.clkr, | |
2816 | [ROT_AHB_CLK] = &rot_ahb_clk.clkr, | |
2817 | [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr, | |
2818 | [MDP_AHB_CLK] = &mdp_ahb_clk.clkr, | |
2819 | [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr, | |
2820 | [CSI_AHB_CLK] = &csi_ahb_clk.clkr, | |
2821 | [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr, | |
2822 | [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr, | |
2823 | [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr, | |
2824 | [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr, | |
2825 | [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr, | |
2826 | [GMEM_AXI_CLK] = &gmem_axi_clk.clkr, | |
2827 | [MDP_AXI_CLK] = &mdp_axi_clk.clkr, | |
2828 | [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr, | |
2829 | [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr, | |
2830 | [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr, | |
2831 | [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr, | |
2832 | [VFE_AXI_CLK] = &vfe_axi_clk.clkr, | |
2833 | [VPE_AXI_CLK] = &vpe_axi_clk.clkr, | |
2834 | [ROT_AXI_CLK] = &rot_axi_clk.clkr, | |
2835 | [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr, | |
2836 | [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr, | |
2837 | [CSI0_SRC] = &csi0_src.clkr, | |
2838 | [CSI0_CLK] = &csi0_clk.clkr, | |
2839 | [CSI0_PHY_CLK] = &csi0_phy_clk.clkr, | |
2840 | [CSI1_SRC] = &csi1_src.clkr, | |
2841 | [CSI1_CLK] = &csi1_clk.clkr, | |
2842 | [CSI1_PHY_CLK] = &csi1_phy_clk.clkr, | |
2843 | [CSI2_SRC] = &csi2_src.clkr, | |
2844 | [CSI2_CLK] = &csi2_clk.clkr, | |
2845 | [CSI2_PHY_CLK] = &csi2_phy_clk.clkr, | |
5532cfb5 AT |
2846 | [DSI_SRC] = &dsi1_src.clkr, |
2847 | [DSI_CLK] = &dsi1_clk.clkr, | |
e216ce60 SB |
2848 | [CSI_PIX_CLK] = &csi_pix_clk.clkr, |
2849 | [CSI_RDI_CLK] = &csi_rdi_clk.clkr, | |
2850 | [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr, | |
2851 | [HDMI_APP_CLK] = &hdmi_app_clk.clkr, | |
2852 | [CSI_PIX1_CLK] = &csi_pix1_clk.clkr, | |
2853 | [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr, | |
2854 | [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr, | |
2855 | [GFX3D_SRC] = &gfx3d_src.clkr, | |
2856 | [GFX3D_CLK] = &gfx3d_clk.clkr, | |
2857 | [IJPEG_SRC] = &ijpeg_src.clkr, | |
2858 | [IJPEG_CLK] = &ijpeg_clk.clkr, | |
2859 | [JPEGD_SRC] = &jpegd_src.clkr, | |
2860 | [JPEGD_CLK] = &jpegd_clk.clkr, | |
2861 | [MDP_SRC] = &mdp_src.clkr, | |
2862 | [MDP_CLK] = &mdp_clk.clkr, | |
2863 | [MDP_LUT_CLK] = &mdp_lut_clk.clkr, | |
5532cfb5 AT |
2864 | [DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr, |
2865 | [DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr, | |
2866 | [DSI2_SRC] = &dsi2_src.clkr, | |
2867 | [DSI2_CLK] = &dsi2_clk.clkr, | |
2868 | [DSI1_BYTE_SRC] = &dsi1_byte_src.clkr, | |
2869 | [DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr, | |
2870 | [DSI2_BYTE_SRC] = &dsi2_byte_src.clkr, | |
2871 | [DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr, | |
2872 | [DSI1_ESC_SRC] = &dsi1_esc_src.clkr, | |
2873 | [DSI1_ESC_CLK] = &dsi1_esc_clk.clkr, | |
2874 | [DSI2_ESC_SRC] = &dsi2_esc_src.clkr, | |
2875 | [DSI2_ESC_CLK] = &dsi2_esc_clk.clkr, | |
e216ce60 SB |
2876 | [ROT_SRC] = &rot_src.clkr, |
2877 | [ROT_CLK] = &rot_clk.clkr, | |
2878 | [TV_DAC_CLK] = &tv_dac_clk.clkr, | |
2879 | [HDMI_TV_CLK] = &hdmi_tv_clk.clkr, | |
2880 | [MDP_TV_CLK] = &mdp_tv_clk.clkr, | |
2881 | [TV_SRC] = &tv_src.clkr, | |
2882 | [VCODEC_SRC] = &vcodec_src.clkr, | |
2883 | [VCODEC_CLK] = &vcodec_clk.clkr, | |
2884 | [VFE_SRC] = &vfe_src.clkr, | |
2885 | [VFE_CLK] = &vfe_clk.clkr, | |
2886 | [VFE_CSI_CLK] = &vfe_csi_clk.clkr, | |
2887 | [VPE_SRC] = &vpe_src.clkr, | |
2888 | [VPE_CLK] = &vpe_clk.clkr, | |
5532cfb5 AT |
2889 | [DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr, |
2890 | [DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr, | |
e216ce60 SB |
2891 | [CAMCLK0_SRC] = &camclk0_src.clkr, |
2892 | [CAMCLK0_CLK] = &camclk0_clk.clkr, | |
2893 | [CAMCLK1_SRC] = &camclk1_src.clkr, | |
2894 | [CAMCLK1_CLK] = &camclk1_clk.clkr, | |
2895 | [CAMCLK2_SRC] = &camclk2_src.clkr, | |
2896 | [CAMCLK2_CLK] = &camclk2_clk.clkr, | |
2897 | [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr, | |
2898 | [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr, | |
2899 | [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr, | |
2900 | [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr, | |
2901 | [PLL2] = &pll2.clkr, | |
2902 | [RGB_TV_CLK] = &rgb_tv_clk.clkr, | |
2903 | [NPL_TV_CLK] = &npl_tv_clk.clkr, | |
2904 | [VCAP_AHB_CLK] = &vcap_ahb_clk.clkr, | |
2905 | [VCAP_AXI_CLK] = &vcap_axi_clk.clkr, | |
2906 | [VCAP_SRC] = &vcap_src.clkr, | |
2907 | [VCAP_CLK] = &vcap_clk.clkr, | |
2908 | [VCAP_NPL_CLK] = &vcap_npl_clk.clkr, | |
2909 | [PLL15] = &pll15.clkr, | |
2910 | }; | |
2911 | ||
2912 | static const struct qcom_reset_map mmcc_apq8064_resets[] = { | |
2913 | [GFX3D_AXI_RESET] = { 0x0208, 17 }, | |
2914 | [VCAP_AXI_RESET] = { 0x0208, 16 }, | |
2915 | [VPE_AXI_RESET] = { 0x0208, 15 }, | |
2916 | [IJPEG_AXI_RESET] = { 0x0208, 14 }, | |
2917 | [MPD_AXI_RESET] = { 0x0208, 13 }, | |
2918 | [VFE_AXI_RESET] = { 0x0208, 9 }, | |
2919 | [SP_AXI_RESET] = { 0x0208, 8 }, | |
2920 | [VCODEC_AXI_RESET] = { 0x0208, 7 }, | |
2921 | [ROT_AXI_RESET] = { 0x0208, 6 }, | |
2922 | [VCODEC_AXI_A_RESET] = { 0x0208, 5 }, | |
2923 | [VCODEC_AXI_B_RESET] = { 0x0208, 4 }, | |
2924 | [FAB_S3_AXI_RESET] = { 0x0208, 3 }, | |
2925 | [FAB_S2_AXI_RESET] = { 0x0208, 2 }, | |
2926 | [FAB_S1_AXI_RESET] = { 0x0208, 1 }, | |
2927 | [FAB_S0_AXI_RESET] = { 0x0208 }, | |
2928 | [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 }, | |
2929 | [SMMU_VPE_AHB_RESET] = { 0x020c, 30 }, | |
2930 | [SMMU_VFE_AHB_RESET] = { 0x020c, 29 }, | |
2931 | [SMMU_ROT_AHB_RESET] = { 0x020c, 28 }, | |
2932 | [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 }, | |
2933 | [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 }, | |
2934 | [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 }, | |
2935 | [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 }, | |
2936 | [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 }, | |
2937 | [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 }, | |
2938 | [APU_AHB_RESET] = { 0x020c, 18 }, | |
2939 | [CSI_AHB_RESET] = { 0x020c, 17 }, | |
2940 | [TV_ENC_AHB_RESET] = { 0x020c, 15 }, | |
2941 | [VPE_AHB_RESET] = { 0x020c, 14 }, | |
2942 | [FABRIC_AHB_RESET] = { 0x020c, 13 }, | |
2943 | [GFX3D_AHB_RESET] = { 0x020c, 10 }, | |
2944 | [HDMI_AHB_RESET] = { 0x020c, 9 }, | |
2945 | [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 }, | |
2946 | [IJPEG_AHB_RESET] = { 0x020c, 7 }, | |
2947 | [DSI_M_AHB_RESET] = { 0x020c, 6 }, | |
2948 | [DSI_S_AHB_RESET] = { 0x020c, 5 }, | |
2949 | [JPEGD_AHB_RESET] = { 0x020c, 4 }, | |
2950 | [MDP_AHB_RESET] = { 0x020c, 3 }, | |
2951 | [ROT_AHB_RESET] = { 0x020c, 2 }, | |
2952 | [VCODEC_AHB_RESET] = { 0x020c, 1 }, | |
2953 | [VFE_AHB_RESET] = { 0x020c, 0 }, | |
2954 | [SMMU_VCAP_AHB_RESET] = { 0x0200, 3 }, | |
2955 | [VCAP_AHB_RESET] = { 0x0200, 2 }, | |
2956 | [DSI2_M_AHB_RESET] = { 0x0200, 1 }, | |
2957 | [DSI2_S_AHB_RESET] = { 0x0200, 0 }, | |
2958 | [CSIPHY2_RESET] = { 0x0210, 31 }, | |
2959 | [CSI_PIX1_RESET] = { 0x0210, 30 }, | |
2960 | [CSIPHY0_RESET] = { 0x0210, 29 }, | |
2961 | [CSIPHY1_RESET] = { 0x0210, 28 }, | |
2962 | [CSI_RDI_RESET] = { 0x0210, 27 }, | |
2963 | [CSI_PIX_RESET] = { 0x0210, 26 }, | |
2964 | [DSI2_RESET] = { 0x0210, 25 }, | |
2965 | [VFE_CSI_RESET] = { 0x0210, 24 }, | |
2966 | [MDP_RESET] = { 0x0210, 21 }, | |
2967 | [AMP_RESET] = { 0x0210, 20 }, | |
2968 | [JPEGD_RESET] = { 0x0210, 19 }, | |
2969 | [CSI1_RESET] = { 0x0210, 18 }, | |
2970 | [VPE_RESET] = { 0x0210, 17 }, | |
2971 | [MMSS_FABRIC_RESET] = { 0x0210, 16 }, | |
2972 | [VFE_RESET] = { 0x0210, 15 }, | |
2973 | [GFX3D_RESET] = { 0x0210, 12 }, | |
2974 | [HDMI_RESET] = { 0x0210, 11 }, | |
2975 | [MMSS_IMEM_RESET] = { 0x0210, 10 }, | |
2976 | [IJPEG_RESET] = { 0x0210, 9 }, | |
2977 | [CSI0_RESET] = { 0x0210, 8 }, | |
2978 | [DSI_RESET] = { 0x0210, 7 }, | |
2979 | [VCODEC_RESET] = { 0x0210, 6 }, | |
2980 | [MDP_TV_RESET] = { 0x0210, 4 }, | |
2981 | [MDP_VSYNC_RESET] = { 0x0210, 3 }, | |
2982 | [ROT_RESET] = { 0x0210, 2 }, | |
2983 | [TV_HDMI_RESET] = { 0x0210, 1 }, | |
2984 | [VCAP_NPL_RESET] = { 0x0214, 4 }, | |
2985 | [VCAP_RESET] = { 0x0214, 3 }, | |
2986 | [CSI2_RESET] = { 0x0214, 2 }, | |
2987 | [CSI_RDI1_RESET] = { 0x0214, 1 }, | |
2988 | [CSI_RDI2_RESET] = { 0x0214 }, | |
2989 | }; | |
2990 | ||
6d00b56f SB |
2991 | static const struct regmap_config mmcc_msm8960_regmap_config = { |
2992 | .reg_bits = 32, | |
2993 | .reg_stride = 4, | |
2994 | .val_bits = 32, | |
2995 | .max_register = 0x334, | |
2996 | .fast_io = true, | |
2997 | }; | |
2998 | ||
e216ce60 SB |
2999 | static const struct regmap_config mmcc_apq8064_regmap_config = { |
3000 | .reg_bits = 32, | |
3001 | .reg_stride = 4, | |
3002 | .val_bits = 32, | |
3003 | .max_register = 0x350, | |
3004 | .fast_io = true, | |
3005 | }; | |
3006 | ||
49fc825f SB |
3007 | static const struct qcom_cc_desc mmcc_msm8960_desc = { |
3008 | .config = &mmcc_msm8960_regmap_config, | |
3009 | .clks = mmcc_msm8960_clks, | |
3010 | .num_clks = ARRAY_SIZE(mmcc_msm8960_clks), | |
3011 | .resets = mmcc_msm8960_resets, | |
3012 | .num_resets = ARRAY_SIZE(mmcc_msm8960_resets), | |
3013 | }; | |
3014 | ||
e216ce60 SB |
3015 | static const struct qcom_cc_desc mmcc_apq8064_desc = { |
3016 | .config = &mmcc_apq8064_regmap_config, | |
3017 | .clks = mmcc_apq8064_clks, | |
3018 | .num_clks = ARRAY_SIZE(mmcc_apq8064_clks), | |
3019 | .resets = mmcc_apq8064_resets, | |
3020 | .num_resets = ARRAY_SIZE(mmcc_apq8064_resets), | |
3021 | }; | |
3022 | ||
6d00b56f | 3023 | static const struct of_device_id mmcc_msm8960_match_table[] = { |
e216ce60 SB |
3024 | { .compatible = "qcom,mmcc-msm8960", .data = &mmcc_msm8960_desc }, |
3025 | { .compatible = "qcom,mmcc-apq8064", .data = &mmcc_apq8064_desc }, | |
6d00b56f SB |
3026 | { } |
3027 | }; | |
3028 | MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table); | |
3029 | ||
6d00b56f SB |
3030 | static int mmcc_msm8960_probe(struct platform_device *pdev) |
3031 | { | |
e216ce60 SB |
3032 | const struct of_device_id *match; |
3033 | struct regmap *regmap; | |
3034 | bool is_8064; | |
3035 | struct device *dev = &pdev->dev; | |
3036 | ||
3037 | match = of_match_device(mmcc_msm8960_match_table, dev); | |
3038 | if (!match) | |
3039 | return -EINVAL; | |
3040 | ||
3041 | is_8064 = of_device_is_compatible(dev->of_node, "qcom,mmcc-apq8064"); | |
3042 | if (is_8064) { | |
3043 | gfx3d_src.freq_tbl = clk_tbl_gfx3d_8064; | |
3044 | gfx3d_src.clkr.hw.init = &gfx3d_8064_init; | |
3045 | gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map; | |
3046 | gfx3d_src.s[1].parent_map = mmcc_pxo_pll8_pll2_pll15_map; | |
3047 | } | |
3048 | ||
3049 | regmap = qcom_cc_map(pdev, match->data); | |
3050 | if (IS_ERR(regmap)) | |
3051 | return PTR_ERR(regmap); | |
3052 | ||
3053 | clk_pll_configure_sr(&pll15, regmap, &pll15_config, false); | |
3054 | ||
3055 | return qcom_cc_really_probe(pdev, match->data, regmap); | |
6d00b56f SB |
3056 | } |
3057 | ||
6d00b56f SB |
3058 | static struct platform_driver mmcc_msm8960_driver = { |
3059 | .probe = mmcc_msm8960_probe, | |
6d00b56f SB |
3060 | .driver = { |
3061 | .name = "mmcc-msm8960", | |
6d00b56f SB |
3062 | .of_match_table = mmcc_msm8960_match_table, |
3063 | }, | |
3064 | }; | |
3065 | ||
3066 | module_platform_driver(mmcc_msm8960_driver); | |
3067 | ||
3068 | MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver"); | |
3069 | MODULE_LICENSE("GPL v2"); | |
3070 | MODULE_ALIAS("platform:mmcc-msm8960"); |