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9c92ab61 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
2b46cd23 | 2 | /* |
cb2eb7de | 3 | * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. |
2b46cd23 GD |
4 | */ |
5 | ||
6 | #include <linux/kernel.h> | |
7 | #include <linux/platform_device.h> | |
8 | #include <linux/module.h> | |
9 | #include <linux/regmap.h> | |
10 | #include <linux/reset-controller.h> | |
11 | ||
12 | #include <dt-bindings/clock/qcom,mmcc-apq8084.h> | |
13 | #include <dt-bindings/reset/qcom,mmcc-apq8084.h> | |
14 | ||
15 | #include "common.h" | |
16 | #include "clk-regmap.h" | |
17 | #include "clk-pll.h" | |
18 | #include "clk-rcg.h" | |
19 | #include "clk-branch.h" | |
20 | #include "reset.h" | |
cb2eb7de | 21 | #include "gdsc.h" |
2b46cd23 | 22 | |
293d2e97 GD |
23 | enum { |
24 | P_XO, | |
25 | P_MMPLL0, | |
26 | P_EDPLINK, | |
27 | P_MMPLL1, | |
28 | P_HDMIPLL, | |
29 | P_GPLL0, | |
30 | P_EDPVCO, | |
31 | P_MMPLL4, | |
32 | P_DSI0PLL, | |
33 | P_DSI0PLL_BYTE, | |
34 | P_MMPLL2, | |
35 | P_MMPLL3, | |
36 | P_GPLL1, | |
37 | P_DSI1PLL, | |
38 | P_DSI1PLL_BYTE, | |
39 | P_MMSLEEP, | |
40 | }; | |
41 | ||
42 | static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = { | |
43 | { P_XO, 0 }, | |
44 | { P_MMPLL0, 1 }, | |
45 | { P_MMPLL1, 2 }, | |
46 | { P_GPLL0, 5 } | |
2b46cd23 GD |
47 | }; |
48 | ||
adb11a40 | 49 | static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = { |
2b46cd23 GD |
50 | "xo", |
51 | "mmpll0_vote", | |
52 | "mmpll1_vote", | |
53 | "mmss_gpll0_vote", | |
54 | }; | |
55 | ||
293d2e97 GD |
56 | static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = { |
57 | { P_XO, 0 }, | |
58 | { P_MMPLL0, 1 }, | |
59 | { P_HDMIPLL, 4 }, | |
60 | { P_GPLL0, 5 }, | |
61 | { P_DSI0PLL, 2 }, | |
62 | { P_DSI1PLL, 3 } | |
2b46cd23 GD |
63 | }; |
64 | ||
adb11a40 | 65 | static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { |
2b46cd23 GD |
66 | "xo", |
67 | "mmpll0_vote", | |
68 | "hdmipll", | |
69 | "mmss_gpll0_vote", | |
70 | "dsi0pll", | |
71 | "dsi1pll", | |
72 | }; | |
73 | ||
293d2e97 GD |
74 | static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = { |
75 | { P_XO, 0 }, | |
76 | { P_MMPLL0, 1 }, | |
77 | { P_MMPLL1, 2 }, | |
78 | { P_GPLL0, 5 }, | |
79 | { P_MMPLL2, 3 } | |
2b46cd23 GD |
80 | }; |
81 | ||
adb11a40 | 82 | static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = { |
2b46cd23 GD |
83 | "xo", |
84 | "mmpll0_vote", | |
85 | "mmpll1_vote", | |
86 | "mmss_gpll0_vote", | |
87 | "mmpll2", | |
88 | }; | |
89 | ||
293d2e97 GD |
90 | static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = { |
91 | { P_XO, 0 }, | |
92 | { P_MMPLL0, 1 }, | |
93 | { P_MMPLL1, 2 }, | |
94 | { P_GPLL0, 5 }, | |
95 | { P_MMPLL3, 3 } | |
2b46cd23 GD |
96 | }; |
97 | ||
adb11a40 | 98 | static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = { |
2b46cd23 GD |
99 | "xo", |
100 | "mmpll0_vote", | |
101 | "mmpll1_vote", | |
102 | "mmss_gpll0_vote", | |
103 | "mmpll3", | |
104 | }; | |
105 | ||
293d2e97 GD |
106 | static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = { |
107 | { P_XO, 0 }, | |
108 | { P_EDPLINK, 4 }, | |
109 | { P_HDMIPLL, 3 }, | |
110 | { P_EDPVCO, 5 }, | |
111 | { P_DSI0PLL, 1 }, | |
112 | { P_DSI1PLL, 2 } | |
2b46cd23 GD |
113 | }; |
114 | ||
adb11a40 | 115 | static const char * const mmcc_xo_dsi_hdmi_edp[] = { |
2b46cd23 GD |
116 | "xo", |
117 | "edp_link_clk", | |
118 | "hdmipll", | |
119 | "edp_vco_div", | |
120 | "dsi0pll", | |
121 | "dsi1pll", | |
122 | }; | |
123 | ||
293d2e97 GD |
124 | static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = { |
125 | { P_XO, 0 }, | |
126 | { P_EDPLINK, 4 }, | |
127 | { P_HDMIPLL, 3 }, | |
128 | { P_GPLL0, 5 }, | |
129 | { P_DSI0PLL, 1 }, | |
130 | { P_DSI1PLL, 2 } | |
2b46cd23 GD |
131 | }; |
132 | ||
adb11a40 | 133 | static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = { |
2b46cd23 GD |
134 | "xo", |
135 | "edp_link_clk", | |
136 | "hdmipll", | |
137 | "gpll0_vote", | |
138 | "dsi0pll", | |
139 | "dsi1pll", | |
140 | }; | |
141 | ||
293d2e97 GD |
142 | static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = { |
143 | { P_XO, 0 }, | |
144 | { P_EDPLINK, 4 }, | |
145 | { P_HDMIPLL, 3 }, | |
146 | { P_GPLL0, 5 }, | |
147 | { P_DSI0PLL_BYTE, 1 }, | |
148 | { P_DSI1PLL_BYTE, 2 } | |
2b46cd23 GD |
149 | }; |
150 | ||
adb11a40 | 151 | static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { |
2b46cd23 GD |
152 | "xo", |
153 | "edp_link_clk", | |
154 | "hdmipll", | |
155 | "gpll0_vote", | |
156 | "dsi0pllbyte", | |
157 | "dsi1pllbyte", | |
158 | }; | |
159 | ||
293d2e97 GD |
160 | static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = { |
161 | { P_XO, 0 }, | |
162 | { P_MMPLL0, 1 }, | |
163 | { P_MMPLL1, 2 }, | |
164 | { P_GPLL0, 5 }, | |
165 | { P_MMPLL4, 3 } | |
2b46cd23 GD |
166 | }; |
167 | ||
adb11a40 | 168 | static const char * const mmcc_xo_mmpll0_1_4_gpll0[] = { |
2b46cd23 GD |
169 | "xo", |
170 | "mmpll0", | |
171 | "mmpll1", | |
172 | "mmpll4", | |
173 | "gpll0", | |
174 | }; | |
175 | ||
293d2e97 GD |
176 | static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = { |
177 | { P_XO, 0 }, | |
178 | { P_MMPLL0, 1 }, | |
179 | { P_MMPLL1, 2 }, | |
180 | { P_MMPLL4, 3 }, | |
181 | { P_GPLL0, 5 }, | |
182 | { P_GPLL1, 4 } | |
2b46cd23 GD |
183 | }; |
184 | ||
adb11a40 | 185 | static const char * const mmcc_xo_mmpll0_1_4_gpll1_0[] = { |
2b46cd23 GD |
186 | "xo", |
187 | "mmpll0", | |
188 | "mmpll1", | |
189 | "mmpll4", | |
190 | "gpll1", | |
191 | "gpll0", | |
192 | }; | |
193 | ||
293d2e97 GD |
194 | static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = { |
195 | { P_XO, 0 }, | |
196 | { P_MMPLL0, 1 }, | |
197 | { P_MMPLL1, 2 }, | |
198 | { P_MMPLL4, 3 }, | |
199 | { P_GPLL0, 5 }, | |
200 | { P_GPLL1, 4 }, | |
201 | { P_MMSLEEP, 6 } | |
2b46cd23 GD |
202 | }; |
203 | ||
adb11a40 | 204 | static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = { |
2b46cd23 GD |
205 | "xo", |
206 | "mmpll0", | |
207 | "mmpll1", | |
208 | "mmpll4", | |
209 | "gpll1", | |
210 | "gpll0", | |
211 | "sleep_clk_src", | |
212 | }; | |
213 | ||
2b46cd23 GD |
214 | static struct clk_pll mmpll0 = { |
215 | .l_reg = 0x0004, | |
216 | .m_reg = 0x0008, | |
217 | .n_reg = 0x000c, | |
218 | .config_reg = 0x0014, | |
219 | .mode_reg = 0x0000, | |
220 | .status_reg = 0x001c, | |
221 | .status_bit = 17, | |
222 | .clkr.hw.init = &(struct clk_init_data){ | |
223 | .name = "mmpll0", | |
224 | .parent_names = (const char *[]){ "xo" }, | |
225 | .num_parents = 1, | |
226 | .ops = &clk_pll_ops, | |
227 | }, | |
228 | }; | |
229 | ||
230 | static struct clk_regmap mmpll0_vote = { | |
231 | .enable_reg = 0x0100, | |
232 | .enable_mask = BIT(0), | |
233 | .hw.init = &(struct clk_init_data){ | |
234 | .name = "mmpll0_vote", | |
235 | .parent_names = (const char *[]){ "mmpll0" }, | |
236 | .num_parents = 1, | |
237 | .ops = &clk_pll_vote_ops, | |
238 | }, | |
239 | }; | |
240 | ||
241 | static struct clk_pll mmpll1 = { | |
242 | .l_reg = 0x0044, | |
243 | .m_reg = 0x0048, | |
244 | .n_reg = 0x004c, | |
245 | .config_reg = 0x0050, | |
246 | .mode_reg = 0x0040, | |
247 | .status_reg = 0x005c, | |
248 | .status_bit = 17, | |
249 | .clkr.hw.init = &(struct clk_init_data){ | |
250 | .name = "mmpll1", | |
251 | .parent_names = (const char *[]){ "xo" }, | |
252 | .num_parents = 1, | |
253 | .ops = &clk_pll_ops, | |
254 | }, | |
255 | }; | |
256 | ||
257 | static struct clk_regmap mmpll1_vote = { | |
258 | .enable_reg = 0x0100, | |
259 | .enable_mask = BIT(1), | |
260 | .hw.init = &(struct clk_init_data){ | |
261 | .name = "mmpll1_vote", | |
262 | .parent_names = (const char *[]){ "mmpll1" }, | |
263 | .num_parents = 1, | |
264 | .ops = &clk_pll_vote_ops, | |
265 | }, | |
266 | }; | |
267 | ||
268 | static struct clk_pll mmpll2 = { | |
269 | .l_reg = 0x4104, | |
270 | .m_reg = 0x4108, | |
271 | .n_reg = 0x410c, | |
272 | .config_reg = 0x4110, | |
273 | .mode_reg = 0x4100, | |
274 | .status_reg = 0x411c, | |
275 | .clkr.hw.init = &(struct clk_init_data){ | |
276 | .name = "mmpll2", | |
277 | .parent_names = (const char *[]){ "xo" }, | |
278 | .num_parents = 1, | |
279 | .ops = &clk_pll_ops, | |
280 | }, | |
281 | }; | |
282 | ||
283 | static struct clk_pll mmpll3 = { | |
284 | .l_reg = 0x0084, | |
285 | .m_reg = 0x0088, | |
286 | .n_reg = 0x008c, | |
287 | .config_reg = 0x0090, | |
288 | .mode_reg = 0x0080, | |
289 | .status_reg = 0x009c, | |
290 | .status_bit = 17, | |
291 | .clkr.hw.init = &(struct clk_init_data){ | |
292 | .name = "mmpll3", | |
293 | .parent_names = (const char *[]){ "xo" }, | |
294 | .num_parents = 1, | |
295 | .ops = &clk_pll_ops, | |
296 | }, | |
297 | }; | |
298 | ||
299 | static struct clk_pll mmpll4 = { | |
300 | .l_reg = 0x00a4, | |
301 | .m_reg = 0x00a8, | |
302 | .n_reg = 0x00ac, | |
303 | .config_reg = 0x00b0, | |
304 | .mode_reg = 0x0080, | |
305 | .status_reg = 0x00bc, | |
306 | .clkr.hw.init = &(struct clk_init_data){ | |
307 | .name = "mmpll4", | |
308 | .parent_names = (const char *[]){ "xo" }, | |
309 | .num_parents = 1, | |
310 | .ops = &clk_pll_ops, | |
311 | }, | |
312 | }; | |
313 | ||
314 | static struct clk_rcg2 mmss_ahb_clk_src = { | |
315 | .cmd_rcgr = 0x5000, | |
316 | .hid_width = 5, | |
317 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
318 | .clkr.hw.init = &(struct clk_init_data){ | |
319 | .name = "mmss_ahb_clk_src", | |
320 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
321 | .num_parents = 4, | |
322 | .ops = &clk_rcg2_ops, | |
323 | }, | |
324 | }; | |
325 | ||
326 | static struct freq_tbl ftbl_mmss_axi_clk[] = { | |
327 | F(19200000, P_XO, 1, 0, 0), | |
328 | F(37500000, P_GPLL0, 16, 0, 0), | |
329 | F(50000000, P_GPLL0, 12, 0, 0), | |
330 | F(75000000, P_GPLL0, 8, 0, 0), | |
331 | F(100000000, P_GPLL0, 6, 0, 0), | |
332 | F(150000000, P_GPLL0, 4, 0, 0), | |
333 | F(333430000, P_MMPLL1, 3.5, 0, 0), | |
334 | F(400000000, P_MMPLL0, 2, 0, 0), | |
335 | F(466800000, P_MMPLL1, 2.5, 0, 0), | |
336 | }; | |
337 | ||
338 | static struct clk_rcg2 mmss_axi_clk_src = { | |
339 | .cmd_rcgr = 0x5040, | |
340 | .hid_width = 5, | |
341 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
342 | .freq_tbl = ftbl_mmss_axi_clk, | |
343 | .clkr.hw.init = &(struct clk_init_data){ | |
344 | .name = "mmss_axi_clk_src", | |
345 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
346 | .num_parents = 4, | |
347 | .ops = &clk_rcg2_ops, | |
348 | }, | |
349 | }; | |
350 | ||
351 | static struct freq_tbl ftbl_ocmemnoc_clk[] = { | |
352 | F(19200000, P_XO, 1, 0, 0), | |
353 | F(37500000, P_GPLL0, 16, 0, 0), | |
354 | F(50000000, P_GPLL0, 12, 0, 0), | |
355 | F(75000000, P_GPLL0, 8, 0, 0), | |
356 | F(109090000, P_GPLL0, 5.5, 0, 0), | |
357 | F(150000000, P_GPLL0, 4, 0, 0), | |
358 | F(228570000, P_MMPLL0, 3.5, 0, 0), | |
359 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
360 | }; | |
361 | ||
362 | static struct clk_rcg2 ocmemnoc_clk_src = { | |
363 | .cmd_rcgr = 0x5090, | |
364 | .hid_width = 5, | |
365 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
366 | .freq_tbl = ftbl_ocmemnoc_clk, | |
367 | .clkr.hw.init = &(struct clk_init_data){ | |
368 | .name = "ocmemnoc_clk_src", | |
369 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
370 | .num_parents = 4, | |
371 | .ops = &clk_rcg2_ops, | |
372 | }, | |
373 | }; | |
374 | ||
375 | static struct freq_tbl ftbl_camss_csi0_3_clk[] = { | |
376 | F(100000000, P_GPLL0, 6, 0, 0), | |
377 | F(200000000, P_MMPLL0, 4, 0, 0), | |
378 | { } | |
379 | }; | |
380 | ||
381 | static struct clk_rcg2 csi0_clk_src = { | |
382 | .cmd_rcgr = 0x3090, | |
383 | .hid_width = 5, | |
384 | .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, | |
385 | .freq_tbl = ftbl_camss_csi0_3_clk, | |
386 | .clkr.hw.init = &(struct clk_init_data){ | |
387 | .name = "csi0_clk_src", | |
388 | .parent_names = mmcc_xo_mmpll0_1_4_gpll0, | |
389 | .num_parents = 5, | |
390 | .ops = &clk_rcg2_ops, | |
391 | }, | |
392 | }; | |
393 | ||
394 | static struct clk_rcg2 csi1_clk_src = { | |
395 | .cmd_rcgr = 0x3100, | |
396 | .hid_width = 5, | |
397 | .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, | |
398 | .freq_tbl = ftbl_camss_csi0_3_clk, | |
399 | .clkr.hw.init = &(struct clk_init_data){ | |
400 | .name = "csi1_clk_src", | |
401 | .parent_names = mmcc_xo_mmpll0_1_4_gpll0, | |
402 | .num_parents = 5, | |
403 | .ops = &clk_rcg2_ops, | |
404 | }, | |
405 | }; | |
406 | ||
407 | static struct clk_rcg2 csi2_clk_src = { | |
408 | .cmd_rcgr = 0x3160, | |
409 | .hid_width = 5, | |
410 | .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, | |
411 | .freq_tbl = ftbl_camss_csi0_3_clk, | |
412 | .clkr.hw.init = &(struct clk_init_data){ | |
413 | .name = "csi2_clk_src", | |
414 | .parent_names = mmcc_xo_mmpll0_1_4_gpll0, | |
415 | .num_parents = 5, | |
416 | .ops = &clk_rcg2_ops, | |
417 | }, | |
418 | }; | |
419 | ||
420 | static struct clk_rcg2 csi3_clk_src = { | |
421 | .cmd_rcgr = 0x31c0, | |
422 | .hid_width = 5, | |
423 | .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, | |
424 | .freq_tbl = ftbl_camss_csi0_3_clk, | |
425 | .clkr.hw.init = &(struct clk_init_data){ | |
426 | .name = "csi3_clk_src", | |
427 | .parent_names = mmcc_xo_mmpll0_1_4_gpll0, | |
428 | .num_parents = 5, | |
429 | .ops = &clk_rcg2_ops, | |
430 | }, | |
431 | }; | |
432 | ||
433 | static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = { | |
434 | F(37500000, P_GPLL0, 16, 0, 0), | |
435 | F(50000000, P_GPLL0, 12, 0, 0), | |
436 | F(60000000, P_GPLL0, 10, 0, 0), | |
437 | F(80000000, P_GPLL0, 7.5, 0, 0), | |
438 | F(100000000, P_GPLL0, 6, 0, 0), | |
439 | F(109090000, P_GPLL0, 5.5, 0, 0), | |
440 | F(133330000, P_GPLL0, 4.5, 0, 0), | |
441 | F(200000000, P_GPLL0, 3, 0, 0), | |
442 | F(228570000, P_MMPLL0, 3.5, 0, 0), | |
443 | F(266670000, P_MMPLL0, 3, 0, 0), | |
444 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
445 | F(465000000, P_MMPLL4, 2, 0, 0), | |
446 | F(600000000, P_GPLL0, 1, 0, 0), | |
447 | { } | |
448 | }; | |
449 | ||
450 | static struct clk_rcg2 vfe0_clk_src = { | |
451 | .cmd_rcgr = 0x3600, | |
452 | .hid_width = 5, | |
453 | .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, | |
454 | .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, | |
455 | .clkr.hw.init = &(struct clk_init_data){ | |
456 | .name = "vfe0_clk_src", | |
457 | .parent_names = mmcc_xo_mmpll0_1_4_gpll0, | |
458 | .num_parents = 5, | |
459 | .ops = &clk_rcg2_ops, | |
460 | }, | |
461 | }; | |
462 | ||
463 | static struct clk_rcg2 vfe1_clk_src = { | |
464 | .cmd_rcgr = 0x3620, | |
465 | .hid_width = 5, | |
466 | .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, | |
467 | .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, | |
468 | .clkr.hw.init = &(struct clk_init_data){ | |
469 | .name = "vfe1_clk_src", | |
470 | .parent_names = mmcc_xo_mmpll0_1_4_gpll0, | |
471 | .num_parents = 5, | |
472 | .ops = &clk_rcg2_ops, | |
473 | }, | |
474 | }; | |
475 | ||
476 | static struct freq_tbl ftbl_mdss_mdp_clk[] = { | |
477 | F(37500000, P_GPLL0, 16, 0, 0), | |
478 | F(60000000, P_GPLL0, 10, 0, 0), | |
479 | F(75000000, P_GPLL0, 8, 0, 0), | |
480 | F(85710000, P_GPLL0, 7, 0, 0), | |
481 | F(100000000, P_GPLL0, 6, 0, 0), | |
482 | F(150000000, P_GPLL0, 4, 0, 0), | |
483 | F(160000000, P_MMPLL0, 5, 0, 0), | |
484 | F(200000000, P_MMPLL0, 4, 0, 0), | |
485 | F(228570000, P_MMPLL0, 3.5, 0, 0), | |
486 | F(300000000, P_GPLL0, 2, 0, 0), | |
487 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
488 | { } | |
489 | }; | |
490 | ||
491 | static struct clk_rcg2 mdp_clk_src = { | |
492 | .cmd_rcgr = 0x2040, | |
493 | .hid_width = 5, | |
494 | .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map, | |
495 | .freq_tbl = ftbl_mdss_mdp_clk, | |
496 | .clkr.hw.init = &(struct clk_init_data){ | |
497 | .name = "mdp_clk_src", | |
498 | .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0, | |
499 | .num_parents = 6, | |
500 | .ops = &clk_rcg2_ops, | |
501 | }, | |
502 | }; | |
503 | ||
504 | static struct clk_rcg2 gfx3d_clk_src = { | |
505 | .cmd_rcgr = 0x4000, | |
506 | .hid_width = 5, | |
507 | .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map, | |
508 | .clkr.hw.init = &(struct clk_init_data){ | |
509 | .name = "gfx3d_clk_src", | |
510 | .parent_names = mmcc_xo_mmpll0_1_2_gpll0, | |
511 | .num_parents = 5, | |
512 | .ops = &clk_rcg2_ops, | |
513 | }, | |
514 | }; | |
515 | ||
516 | static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = { | |
517 | F(75000000, P_GPLL0, 8, 0, 0), | |
518 | F(133330000, P_GPLL0, 4.5, 0, 0), | |
519 | F(200000000, P_GPLL0, 3, 0, 0), | |
520 | F(228570000, P_MMPLL0, 3.5, 0, 0), | |
521 | F(266670000, P_MMPLL0, 3, 0, 0), | |
522 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
523 | { } | |
524 | }; | |
525 | ||
526 | static struct clk_rcg2 jpeg0_clk_src = { | |
527 | .cmd_rcgr = 0x3500, | |
528 | .hid_width = 5, | |
529 | .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, | |
530 | .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, | |
531 | .clkr.hw.init = &(struct clk_init_data){ | |
532 | .name = "jpeg0_clk_src", | |
533 | .parent_names = mmcc_xo_mmpll0_1_4_gpll0, | |
534 | .num_parents = 5, | |
535 | .ops = &clk_rcg2_ops, | |
536 | }, | |
537 | }; | |
538 | ||
539 | static struct clk_rcg2 jpeg1_clk_src = { | |
540 | .cmd_rcgr = 0x3520, | |
541 | .hid_width = 5, | |
542 | .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, | |
543 | .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, | |
544 | .clkr.hw.init = &(struct clk_init_data){ | |
545 | .name = "jpeg1_clk_src", | |
546 | .parent_names = mmcc_xo_mmpll0_1_4_gpll0, | |
547 | .num_parents = 5, | |
548 | .ops = &clk_rcg2_ops, | |
549 | }, | |
550 | }; | |
551 | ||
552 | static struct clk_rcg2 jpeg2_clk_src = { | |
553 | .cmd_rcgr = 0x3540, | |
554 | .hid_width = 5, | |
555 | .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, | |
556 | .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, | |
557 | .clkr.hw.init = &(struct clk_init_data){ | |
558 | .name = "jpeg2_clk_src", | |
559 | .parent_names = mmcc_xo_mmpll0_1_4_gpll0, | |
560 | .num_parents = 5, | |
561 | .ops = &clk_rcg2_ops, | |
562 | }, | |
563 | }; | |
564 | ||
2b46cd23 GD |
565 | static struct clk_rcg2 pclk0_clk_src = { |
566 | .cmd_rcgr = 0x2000, | |
567 | .mnd_width = 8, | |
568 | .hid_width = 5, | |
569 | .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, | |
2b46cd23 GD |
570 | .clkr.hw.init = &(struct clk_init_data){ |
571 | .name = "pclk0_clk_src", | |
572 | .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, | |
573 | .num_parents = 6, | |
574 | .ops = &clk_pixel_ops, | |
575 | .flags = CLK_SET_RATE_PARENT, | |
576 | }, | |
577 | }; | |
578 | ||
579 | static struct clk_rcg2 pclk1_clk_src = { | |
580 | .cmd_rcgr = 0x2020, | |
581 | .mnd_width = 8, | |
582 | .hid_width = 5, | |
583 | .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, | |
2b46cd23 GD |
584 | .clkr.hw.init = &(struct clk_init_data){ |
585 | .name = "pclk1_clk_src", | |
586 | .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, | |
587 | .num_parents = 6, | |
588 | .ops = &clk_pixel_ops, | |
589 | .flags = CLK_SET_RATE_PARENT, | |
590 | }, | |
591 | }; | |
592 | ||
593 | static struct freq_tbl ftbl_venus0_vcodec0_clk[] = { | |
594 | F(50000000, P_GPLL0, 12, 0, 0), | |
595 | F(100000000, P_GPLL0, 6, 0, 0), | |
596 | F(133330000, P_GPLL0, 4.5, 0, 0), | |
597 | F(200000000, P_MMPLL0, 4, 0, 0), | |
598 | F(266670000, P_MMPLL0, 3, 0, 0), | |
599 | F(465000000, P_MMPLL3, 2, 0, 0), | |
600 | { } | |
601 | }; | |
602 | ||
603 | static struct clk_rcg2 vcodec0_clk_src = { | |
604 | .cmd_rcgr = 0x1000, | |
605 | .mnd_width = 8, | |
606 | .hid_width = 5, | |
607 | .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map, | |
608 | .freq_tbl = ftbl_venus0_vcodec0_clk, | |
609 | .clkr.hw.init = &(struct clk_init_data){ | |
610 | .name = "vcodec0_clk_src", | |
611 | .parent_names = mmcc_xo_mmpll0_1_3_gpll0, | |
612 | .num_parents = 5, | |
613 | .ops = &clk_rcg2_ops, | |
614 | }, | |
615 | }; | |
616 | ||
617 | static struct freq_tbl ftbl_avsync_vp_clk[] = { | |
618 | F(150000000, P_GPLL0, 4, 0, 0), | |
619 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
620 | { } | |
621 | }; | |
622 | ||
623 | static struct clk_rcg2 vp_clk_src = { | |
624 | .cmd_rcgr = 0x2430, | |
625 | .hid_width = 5, | |
626 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
627 | .freq_tbl = ftbl_avsync_vp_clk, | |
628 | .clkr.hw.init = &(struct clk_init_data){ | |
629 | .name = "vp_clk_src", | |
630 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
631 | .num_parents = 4, | |
632 | .ops = &clk_rcg2_ops, | |
633 | }, | |
634 | }; | |
635 | ||
636 | static struct freq_tbl ftbl_camss_cci_cci_clk[] = { | |
637 | F(19200000, P_XO, 1, 0, 0), | |
638 | { } | |
639 | }; | |
640 | ||
641 | static struct clk_rcg2 cci_clk_src = { | |
642 | .cmd_rcgr = 0x3300, | |
643 | .mnd_width = 8, | |
644 | .hid_width = 5, | |
645 | .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, | |
646 | .freq_tbl = ftbl_camss_cci_cci_clk, | |
647 | .clkr.hw.init = &(struct clk_init_data){ | |
648 | .name = "cci_clk_src", | |
649 | .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0, | |
650 | .num_parents = 6, | |
651 | .ops = &clk_rcg2_ops, | |
652 | }, | |
653 | }; | |
654 | ||
655 | static struct freq_tbl ftbl_camss_gp0_1_clk[] = { | |
656 | F(10000, P_XO, 16, 1, 120), | |
657 | F(24000, P_XO, 16, 1, 50), | |
658 | F(6000000, P_GPLL0, 10, 1, 10), | |
659 | F(12000000, P_GPLL0, 10, 1, 5), | |
660 | F(13000000, P_GPLL0, 4, 13, 150), | |
661 | F(24000000, P_GPLL0, 5, 1, 5), | |
662 | { } | |
663 | }; | |
664 | ||
665 | static struct clk_rcg2 camss_gp0_clk_src = { | |
666 | .cmd_rcgr = 0x3420, | |
667 | .mnd_width = 8, | |
668 | .hid_width = 5, | |
669 | .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map, | |
670 | .freq_tbl = ftbl_camss_gp0_1_clk, | |
671 | .clkr.hw.init = &(struct clk_init_data){ | |
672 | .name = "camss_gp0_clk_src", | |
673 | .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep, | |
674 | .num_parents = 7, | |
675 | .ops = &clk_rcg2_ops, | |
676 | }, | |
677 | }; | |
678 | ||
679 | static struct clk_rcg2 camss_gp1_clk_src = { | |
680 | .cmd_rcgr = 0x3450, | |
681 | .mnd_width = 8, | |
682 | .hid_width = 5, | |
683 | .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map, | |
684 | .freq_tbl = ftbl_camss_gp0_1_clk, | |
685 | .clkr.hw.init = &(struct clk_init_data){ | |
686 | .name = "camss_gp1_clk_src", | |
687 | .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep, | |
688 | .num_parents = 7, | |
689 | .ops = &clk_rcg2_ops, | |
690 | }, | |
691 | }; | |
692 | ||
693 | static struct freq_tbl ftbl_camss_mclk0_3_clk[] = { | |
694 | F(4800000, P_XO, 4, 0, 0), | |
695 | F(6000000, P_GPLL0, 10, 1, 10), | |
696 | F(8000000, P_GPLL0, 15, 1, 5), | |
697 | F(9600000, P_XO, 2, 0, 0), | |
698 | F(16000000, P_MMPLL0, 10, 1, 5), | |
699 | F(19200000, P_XO, 1, 0, 0), | |
700 | F(24000000, P_GPLL0, 5, 1, 5), | |
701 | F(32000000, P_MMPLL0, 5, 1, 5), | |
702 | F(48000000, P_GPLL0, 12.5, 0, 0), | |
703 | F(64000000, P_MMPLL0, 12.5, 0, 0), | |
704 | { } | |
705 | }; | |
706 | ||
707 | static struct clk_rcg2 mclk0_clk_src = { | |
708 | .cmd_rcgr = 0x3360, | |
709 | .mnd_width = 8, | |
710 | .hid_width = 5, | |
711 | .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, | |
712 | .freq_tbl = ftbl_camss_mclk0_3_clk, | |
713 | .clkr.hw.init = &(struct clk_init_data){ | |
714 | .name = "mclk0_clk_src", | |
715 | .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0, | |
716 | .num_parents = 6, | |
717 | .ops = &clk_rcg2_ops, | |
718 | }, | |
719 | }; | |
720 | ||
721 | static struct clk_rcg2 mclk1_clk_src = { | |
722 | .cmd_rcgr = 0x3390, | |
723 | .mnd_width = 8, | |
724 | .hid_width = 5, | |
725 | .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, | |
726 | .freq_tbl = ftbl_camss_mclk0_3_clk, | |
727 | .clkr.hw.init = &(struct clk_init_data){ | |
728 | .name = "mclk1_clk_src", | |
729 | .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0, | |
730 | .num_parents = 6, | |
731 | .ops = &clk_rcg2_ops, | |
732 | }, | |
733 | }; | |
734 | ||
735 | static struct clk_rcg2 mclk2_clk_src = { | |
736 | .cmd_rcgr = 0x33c0, | |
737 | .mnd_width = 8, | |
738 | .hid_width = 5, | |
739 | .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, | |
740 | .freq_tbl = ftbl_camss_mclk0_3_clk, | |
741 | .clkr.hw.init = &(struct clk_init_data){ | |
742 | .name = "mclk2_clk_src", | |
743 | .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0, | |
744 | .num_parents = 6, | |
745 | .ops = &clk_rcg2_ops, | |
746 | }, | |
747 | }; | |
748 | ||
749 | static struct clk_rcg2 mclk3_clk_src = { | |
750 | .cmd_rcgr = 0x33f0, | |
751 | .mnd_width = 8, | |
752 | .hid_width = 5, | |
753 | .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, | |
754 | .freq_tbl = ftbl_camss_mclk0_3_clk, | |
755 | .clkr.hw.init = &(struct clk_init_data){ | |
756 | .name = "mclk3_clk_src", | |
757 | .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0, | |
758 | .num_parents = 6, | |
759 | .ops = &clk_rcg2_ops, | |
760 | }, | |
761 | }; | |
762 | ||
763 | static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = { | |
764 | F(100000000, P_GPLL0, 6, 0, 0), | |
765 | F(200000000, P_MMPLL0, 4, 0, 0), | |
766 | { } | |
767 | }; | |
768 | ||
769 | static struct clk_rcg2 csi0phytimer_clk_src = { | |
770 | .cmd_rcgr = 0x3000, | |
771 | .hid_width = 5, | |
772 | .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, | |
773 | .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, | |
774 | .clkr.hw.init = &(struct clk_init_data){ | |
775 | .name = "csi0phytimer_clk_src", | |
776 | .parent_names = mmcc_xo_mmpll0_1_4_gpll0, | |
777 | .num_parents = 5, | |
778 | .ops = &clk_rcg2_ops, | |
779 | }, | |
780 | }; | |
781 | ||
782 | static struct clk_rcg2 csi1phytimer_clk_src = { | |
783 | .cmd_rcgr = 0x3030, | |
784 | .hid_width = 5, | |
785 | .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, | |
786 | .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, | |
787 | .clkr.hw.init = &(struct clk_init_data){ | |
788 | .name = "csi1phytimer_clk_src", | |
789 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
790 | .num_parents = 5, | |
791 | .ops = &clk_rcg2_ops, | |
792 | }, | |
793 | }; | |
794 | ||
795 | static struct clk_rcg2 csi2phytimer_clk_src = { | |
796 | .cmd_rcgr = 0x3060, | |
797 | .hid_width = 5, | |
798 | .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, | |
799 | .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, | |
800 | .clkr.hw.init = &(struct clk_init_data){ | |
801 | .name = "csi2phytimer_clk_src", | |
802 | .parent_names = mmcc_xo_mmpll0_1_4_gpll0, | |
803 | .num_parents = 5, | |
804 | .ops = &clk_rcg2_ops, | |
805 | }, | |
806 | }; | |
807 | ||
808 | static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = { | |
809 | F(133330000, P_GPLL0, 4.5, 0, 0), | |
810 | F(266670000, P_MMPLL0, 3, 0, 0), | |
811 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
812 | F(372000000, P_MMPLL4, 2.5, 0, 0), | |
813 | F(465000000, P_MMPLL4, 2, 0, 0), | |
814 | F(600000000, P_GPLL0, 1, 0, 0), | |
815 | { } | |
816 | }; | |
817 | ||
818 | static struct clk_rcg2 cpp_clk_src = { | |
819 | .cmd_rcgr = 0x3640, | |
820 | .hid_width = 5, | |
821 | .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, | |
822 | .freq_tbl = ftbl_camss_vfe_cpp_clk, | |
823 | .clkr.hw.init = &(struct clk_init_data){ | |
824 | .name = "cpp_clk_src", | |
825 | .parent_names = mmcc_xo_mmpll0_1_4_gpll0, | |
826 | .num_parents = 5, | |
827 | .ops = &clk_rcg2_ops, | |
828 | }, | |
829 | }; | |
830 | ||
2b46cd23 GD |
831 | static struct clk_rcg2 byte0_clk_src = { |
832 | .cmd_rcgr = 0x2120, | |
833 | .hid_width = 5, | |
834 | .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, | |
2b46cd23 GD |
835 | .clkr.hw.init = &(struct clk_init_data){ |
836 | .name = "byte0_clk_src", | |
837 | .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, | |
838 | .num_parents = 6, | |
8ee9c7de | 839 | .ops = &clk_byte2_ops, |
2b46cd23 GD |
840 | .flags = CLK_SET_RATE_PARENT, |
841 | }, | |
842 | }; | |
843 | ||
844 | static struct clk_rcg2 byte1_clk_src = { | |
845 | .cmd_rcgr = 0x2140, | |
846 | .hid_width = 5, | |
847 | .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, | |
2b46cd23 GD |
848 | .clkr.hw.init = &(struct clk_init_data){ |
849 | .name = "byte1_clk_src", | |
850 | .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, | |
851 | .num_parents = 6, | |
8ee9c7de | 852 | .ops = &clk_byte2_ops, |
2b46cd23 GD |
853 | .flags = CLK_SET_RATE_PARENT, |
854 | }, | |
855 | }; | |
856 | ||
857 | static struct freq_tbl ftbl_mdss_edpaux_clk[] = { | |
858 | F(19200000, P_XO, 1, 0, 0), | |
859 | { } | |
860 | }; | |
861 | ||
862 | static struct clk_rcg2 edpaux_clk_src = { | |
863 | .cmd_rcgr = 0x20e0, | |
864 | .hid_width = 5, | |
865 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
866 | .freq_tbl = ftbl_mdss_edpaux_clk, | |
867 | .clkr.hw.init = &(struct clk_init_data){ | |
868 | .name = "edpaux_clk_src", | |
869 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
870 | .num_parents = 4, | |
871 | .ops = &clk_rcg2_ops, | |
872 | }, | |
873 | }; | |
874 | ||
875 | static struct freq_tbl ftbl_mdss_edplink_clk[] = { | |
876 | F(135000000, P_EDPLINK, 2, 0, 0), | |
877 | F(270000000, P_EDPLINK, 11, 0, 0), | |
878 | { } | |
879 | }; | |
880 | ||
881 | static struct clk_rcg2 edplink_clk_src = { | |
882 | .cmd_rcgr = 0x20c0, | |
883 | .hid_width = 5, | |
884 | .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, | |
885 | .freq_tbl = ftbl_mdss_edplink_clk, | |
886 | .clkr.hw.init = &(struct clk_init_data){ | |
887 | .name = "edplink_clk_src", | |
888 | .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, | |
889 | .num_parents = 6, | |
890 | .ops = &clk_rcg2_ops, | |
891 | .flags = CLK_SET_RATE_PARENT, | |
892 | }, | |
893 | }; | |
894 | ||
895 | static struct freq_tbl edp_pixel_freq_tbl[] = { | |
896 | { .src = P_EDPVCO }, | |
897 | { } | |
898 | }; | |
899 | ||
900 | static struct clk_rcg2 edppixel_clk_src = { | |
901 | .cmd_rcgr = 0x20a0, | |
902 | .mnd_width = 8, | |
903 | .hid_width = 5, | |
904 | .parent_map = mmcc_xo_dsi_hdmi_edp_map, | |
905 | .freq_tbl = edp_pixel_freq_tbl, | |
906 | .clkr.hw.init = &(struct clk_init_data){ | |
907 | .name = "edppixel_clk_src", | |
908 | .parent_names = mmcc_xo_dsi_hdmi_edp, | |
909 | .num_parents = 6, | |
910 | .ops = &clk_edp_pixel_ops, | |
911 | }, | |
912 | }; | |
913 | ||
914 | static struct freq_tbl ftbl_mdss_esc0_1_clk[] = { | |
915 | F(19200000, P_XO, 1, 0, 0), | |
916 | { } | |
917 | }; | |
918 | ||
919 | static struct clk_rcg2 esc0_clk_src = { | |
920 | .cmd_rcgr = 0x2160, | |
921 | .hid_width = 5, | |
922 | .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, | |
923 | .freq_tbl = ftbl_mdss_esc0_1_clk, | |
924 | .clkr.hw.init = &(struct clk_init_data){ | |
925 | .name = "esc0_clk_src", | |
926 | .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, | |
927 | .num_parents = 6, | |
928 | .ops = &clk_rcg2_ops, | |
929 | }, | |
930 | }; | |
931 | ||
932 | static struct clk_rcg2 esc1_clk_src = { | |
933 | .cmd_rcgr = 0x2180, | |
934 | .hid_width = 5, | |
935 | .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, | |
936 | .freq_tbl = ftbl_mdss_esc0_1_clk, | |
937 | .clkr.hw.init = &(struct clk_init_data){ | |
938 | .name = "esc1_clk_src", | |
939 | .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, | |
940 | .num_parents = 6, | |
941 | .ops = &clk_rcg2_ops, | |
942 | }, | |
943 | }; | |
944 | ||
945 | static struct freq_tbl extpclk_freq_tbl[] = { | |
946 | { .src = P_HDMIPLL }, | |
947 | { } | |
948 | }; | |
949 | ||
950 | static struct clk_rcg2 extpclk_clk_src = { | |
951 | .cmd_rcgr = 0x2060, | |
952 | .hid_width = 5, | |
953 | .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, | |
954 | .freq_tbl = extpclk_freq_tbl, | |
955 | .clkr.hw.init = &(struct clk_init_data){ | |
956 | .name = "extpclk_clk_src", | |
957 | .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, | |
958 | .num_parents = 6, | |
959 | .ops = &clk_byte_ops, | |
960 | .flags = CLK_SET_RATE_PARENT, | |
961 | }, | |
962 | }; | |
963 | ||
964 | static struct freq_tbl ftbl_mdss_hdmi_clk[] = { | |
965 | F(19200000, P_XO, 1, 0, 0), | |
966 | { } | |
967 | }; | |
968 | ||
969 | static struct clk_rcg2 hdmi_clk_src = { | |
970 | .cmd_rcgr = 0x2100, | |
971 | .hid_width = 5, | |
972 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
973 | .freq_tbl = ftbl_mdss_hdmi_clk, | |
974 | .clkr.hw.init = &(struct clk_init_data){ | |
975 | .name = "hdmi_clk_src", | |
976 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
977 | .num_parents = 4, | |
978 | .ops = &clk_rcg2_ops, | |
979 | }, | |
980 | }; | |
981 | ||
982 | static struct freq_tbl ftbl_mdss_vsync_clk[] = { | |
983 | F(19200000, P_XO, 1, 0, 0), | |
984 | { } | |
985 | }; | |
986 | ||
987 | static struct clk_rcg2 vsync_clk_src = { | |
988 | .cmd_rcgr = 0x2080, | |
989 | .hid_width = 5, | |
990 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
991 | .freq_tbl = ftbl_mdss_vsync_clk, | |
992 | .clkr.hw.init = &(struct clk_init_data){ | |
993 | .name = "vsync_clk_src", | |
994 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
995 | .num_parents = 4, | |
996 | .ops = &clk_rcg2_ops, | |
997 | }, | |
998 | }; | |
999 | ||
1000 | static struct freq_tbl ftbl_mmss_rbcpr_clk[] = { | |
1001 | F(50000000, P_GPLL0, 12, 0, 0), | |
1002 | { } | |
1003 | }; | |
1004 | ||
1005 | static struct clk_rcg2 rbcpr_clk_src = { | |
1006 | .cmd_rcgr = 0x4060, | |
1007 | .hid_width = 5, | |
1008 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
1009 | .freq_tbl = ftbl_mmss_rbcpr_clk, | |
1010 | .clkr.hw.init = &(struct clk_init_data){ | |
1011 | .name = "rbcpr_clk_src", | |
1012 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
1013 | .num_parents = 4, | |
1014 | .ops = &clk_rcg2_ops, | |
1015 | }, | |
1016 | }; | |
1017 | ||
1018 | static struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = { | |
1019 | F(19200000, P_XO, 1, 0, 0), | |
1020 | { } | |
1021 | }; | |
1022 | ||
1023 | static struct clk_rcg2 rbbmtimer_clk_src = { | |
1024 | .cmd_rcgr = 0x4090, | |
1025 | .hid_width = 5, | |
1026 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
1027 | .freq_tbl = ftbl_oxili_rbbmtimer_clk, | |
1028 | .clkr.hw.init = &(struct clk_init_data){ | |
1029 | .name = "rbbmtimer_clk_src", | |
1030 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
1031 | .num_parents = 4, | |
1032 | .ops = &clk_rcg2_ops, | |
1033 | }, | |
1034 | }; | |
1035 | ||
1036 | static struct freq_tbl ftbl_vpu_maple_clk[] = { | |
1037 | F(50000000, P_GPLL0, 12, 0, 0), | |
1038 | F(100000000, P_GPLL0, 6, 0, 0), | |
1039 | F(133330000, P_GPLL0, 4.5, 0, 0), | |
1040 | F(200000000, P_MMPLL0, 4, 0, 0), | |
1041 | F(266670000, P_MMPLL0, 3, 0, 0), | |
1042 | F(465000000, P_MMPLL3, 2, 0, 0), | |
1043 | { } | |
1044 | }; | |
1045 | ||
1046 | static struct clk_rcg2 maple_clk_src = { | |
1047 | .cmd_rcgr = 0x1320, | |
1048 | .hid_width = 5, | |
1049 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
1050 | .freq_tbl = ftbl_vpu_maple_clk, | |
1051 | .clkr.hw.init = &(struct clk_init_data){ | |
1052 | .name = "maple_clk_src", | |
1053 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
1054 | .num_parents = 4, | |
1055 | .ops = &clk_rcg2_ops, | |
1056 | }, | |
1057 | }; | |
1058 | ||
1059 | static struct freq_tbl ftbl_vpu_vdp_clk[] = { | |
1060 | F(50000000, P_GPLL0, 12, 0, 0), | |
1061 | F(100000000, P_GPLL0, 6, 0, 0), | |
1062 | F(200000000, P_MMPLL0, 4, 0, 0), | |
1063 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
1064 | F(400000000, P_MMPLL0, 2, 0, 0), | |
1065 | { } | |
1066 | }; | |
1067 | ||
1068 | static struct clk_rcg2 vdp_clk_src = { | |
1069 | .cmd_rcgr = 0x1300, | |
1070 | .hid_width = 5, | |
1071 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
1072 | .freq_tbl = ftbl_vpu_vdp_clk, | |
1073 | .clkr.hw.init = &(struct clk_init_data){ | |
1074 | .name = "vdp_clk_src", | |
1075 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
1076 | .num_parents = 4, | |
1077 | .ops = &clk_rcg2_ops, | |
1078 | }, | |
1079 | }; | |
1080 | ||
1081 | static struct freq_tbl ftbl_vpu_bus_clk[] = { | |
1082 | F(40000000, P_GPLL0, 15, 0, 0), | |
1083 | F(80000000, P_MMPLL0, 10, 0, 0), | |
1084 | { } | |
1085 | }; | |
1086 | ||
1087 | static struct clk_rcg2 vpu_bus_clk_src = { | |
1088 | .cmd_rcgr = 0x1340, | |
1089 | .hid_width = 5, | |
1090 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
1091 | .freq_tbl = ftbl_vpu_bus_clk, | |
1092 | .clkr.hw.init = &(struct clk_init_data){ | |
1093 | .name = "vpu_bus_clk_src", | |
1094 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
1095 | .num_parents = 4, | |
1096 | .ops = &clk_rcg2_ops, | |
1097 | }, | |
1098 | }; | |
1099 | ||
1100 | static struct clk_branch mmss_cxo_clk = { | |
1101 | .halt_reg = 0x5104, | |
1102 | .clkr = { | |
1103 | .enable_reg = 0x5104, | |
1104 | .enable_mask = BIT(0), | |
1105 | .hw.init = &(struct clk_init_data){ | |
1106 | .name = "mmss_cxo_clk", | |
1107 | .parent_names = (const char *[]){ "xo" }, | |
1108 | .num_parents = 1, | |
1109 | .flags = CLK_SET_RATE_PARENT, | |
1110 | .ops = &clk_branch2_ops, | |
1111 | }, | |
1112 | }, | |
1113 | }; | |
1114 | ||
1115 | static struct clk_branch mmss_sleepclk_clk = { | |
1116 | .halt_reg = 0x5100, | |
1117 | .clkr = { | |
1118 | .enable_reg = 0x5100, | |
1119 | .enable_mask = BIT(0), | |
1120 | .hw.init = &(struct clk_init_data){ | |
1121 | .name = "mmss_sleepclk_clk", | |
1122 | .parent_names = (const char *[]){ | |
1123 | "sleep_clk_src", | |
1124 | }, | |
1125 | .num_parents = 1, | |
1126 | .flags = CLK_SET_RATE_PARENT, | |
1127 | .ops = &clk_branch2_ops, | |
1128 | }, | |
1129 | }, | |
1130 | }; | |
1131 | ||
1132 | static struct clk_branch avsync_ahb_clk = { | |
1133 | .halt_reg = 0x2414, | |
1134 | .clkr = { | |
1135 | .enable_reg = 0x2414, | |
1136 | .enable_mask = BIT(0), | |
1137 | .hw.init = &(struct clk_init_data){ | |
1138 | .name = "avsync_ahb_clk", | |
1139 | .parent_names = (const char *[]){ | |
1140 | "mmss_ahb_clk_src", | |
1141 | }, | |
1142 | .num_parents = 1, | |
1143 | .flags = CLK_SET_RATE_PARENT, | |
1144 | .ops = &clk_branch2_ops, | |
1145 | }, | |
1146 | }, | |
1147 | }; | |
1148 | ||
1149 | static struct clk_branch avsync_edppixel_clk = { | |
1150 | .halt_reg = 0x2418, | |
1151 | .clkr = { | |
1152 | .enable_reg = 0x2418, | |
1153 | .enable_mask = BIT(0), | |
1154 | .hw.init = &(struct clk_init_data){ | |
1155 | .name = "avsync_edppixel_clk", | |
1156 | .parent_names = (const char *[]){ | |
1157 | "edppixel_clk_src", | |
1158 | }, | |
1159 | .num_parents = 1, | |
1160 | .flags = CLK_SET_RATE_PARENT, | |
1161 | .ops = &clk_branch2_ops, | |
1162 | }, | |
1163 | }, | |
1164 | }; | |
1165 | ||
1166 | static struct clk_branch avsync_extpclk_clk = { | |
1167 | .halt_reg = 0x2410, | |
1168 | .clkr = { | |
1169 | .enable_reg = 0x2410, | |
1170 | .enable_mask = BIT(0), | |
1171 | .hw.init = &(struct clk_init_data){ | |
1172 | .name = "avsync_extpclk_clk", | |
1173 | .parent_names = (const char *[]){ | |
1174 | "extpclk_clk_src", | |
1175 | }, | |
1176 | .num_parents = 1, | |
1177 | .flags = CLK_SET_RATE_PARENT, | |
1178 | .ops = &clk_branch2_ops, | |
1179 | }, | |
1180 | }, | |
1181 | }; | |
1182 | ||
1183 | static struct clk_branch avsync_pclk0_clk = { | |
1184 | .halt_reg = 0x241c, | |
1185 | .clkr = { | |
1186 | .enable_reg = 0x241c, | |
1187 | .enable_mask = BIT(0), | |
1188 | .hw.init = &(struct clk_init_data){ | |
1189 | .name = "avsync_pclk0_clk", | |
1190 | .parent_names = (const char *[]){ | |
1191 | "pclk0_clk_src", | |
1192 | }, | |
1193 | .num_parents = 1, | |
1194 | .flags = CLK_SET_RATE_PARENT, | |
1195 | .ops = &clk_branch2_ops, | |
1196 | }, | |
1197 | }, | |
1198 | }; | |
1199 | ||
1200 | static struct clk_branch avsync_pclk1_clk = { | |
1201 | .halt_reg = 0x2420, | |
1202 | .clkr = { | |
1203 | .enable_reg = 0x2420, | |
1204 | .enable_mask = BIT(0), | |
1205 | .hw.init = &(struct clk_init_data){ | |
1206 | .name = "avsync_pclk1_clk", | |
1207 | .parent_names = (const char *[]){ | |
1208 | "pclk1_clk_src", | |
1209 | }, | |
1210 | .num_parents = 1, | |
1211 | .flags = CLK_SET_RATE_PARENT, | |
1212 | .ops = &clk_branch2_ops, | |
1213 | }, | |
1214 | }, | |
1215 | }; | |
1216 | ||
1217 | static struct clk_branch avsync_vp_clk = { | |
1218 | .halt_reg = 0x2404, | |
1219 | .clkr = { | |
1220 | .enable_reg = 0x2404, | |
1221 | .enable_mask = BIT(0), | |
1222 | .hw.init = &(struct clk_init_data){ | |
1223 | .name = "avsync_vp_clk", | |
1224 | .parent_names = (const char *[]){ | |
1225 | "vp_clk_src", | |
1226 | }, | |
1227 | .num_parents = 1, | |
1228 | .flags = CLK_SET_RATE_PARENT, | |
1229 | .ops = &clk_branch2_ops, | |
1230 | }, | |
1231 | }, | |
1232 | }; | |
1233 | ||
1234 | static struct clk_branch camss_ahb_clk = { | |
1235 | .halt_reg = 0x348c, | |
1236 | .clkr = { | |
1237 | .enable_reg = 0x348c, | |
1238 | .enable_mask = BIT(0), | |
1239 | .hw.init = &(struct clk_init_data){ | |
1240 | .name = "camss_ahb_clk", | |
1241 | .parent_names = (const char *[]){ | |
1242 | "mmss_ahb_clk_src", | |
1243 | }, | |
1244 | .num_parents = 1, | |
1245 | .flags = CLK_SET_RATE_PARENT, | |
1246 | .ops = &clk_branch2_ops, | |
1247 | }, | |
1248 | }, | |
1249 | }; | |
1250 | ||
1251 | static struct clk_branch camss_cci_cci_ahb_clk = { | |
1252 | .halt_reg = 0x3348, | |
1253 | .clkr = { | |
1254 | .enable_reg = 0x3348, | |
1255 | .enable_mask = BIT(0), | |
1256 | .hw.init = &(struct clk_init_data){ | |
1257 | .name = "camss_cci_cci_ahb_clk", | |
1258 | .parent_names = (const char *[]){ | |
1259 | "mmss_ahb_clk_src", | |
1260 | }, | |
1261 | .num_parents = 1, | |
1262 | .ops = &clk_branch2_ops, | |
1263 | }, | |
1264 | }, | |
1265 | }; | |
1266 | ||
1267 | static struct clk_branch camss_cci_cci_clk = { | |
1268 | .halt_reg = 0x3344, | |
1269 | .clkr = { | |
1270 | .enable_reg = 0x3344, | |
1271 | .enable_mask = BIT(0), | |
1272 | .hw.init = &(struct clk_init_data){ | |
1273 | .name = "camss_cci_cci_clk", | |
1274 | .parent_names = (const char *[]){ | |
1275 | "cci_clk_src", | |
1276 | }, | |
1277 | .num_parents = 1, | |
1278 | .flags = CLK_SET_RATE_PARENT, | |
1279 | .ops = &clk_branch2_ops, | |
1280 | }, | |
1281 | }, | |
1282 | }; | |
1283 | ||
1284 | static struct clk_branch camss_csi0_ahb_clk = { | |
1285 | .halt_reg = 0x30bc, | |
1286 | .clkr = { | |
1287 | .enable_reg = 0x30bc, | |
1288 | .enable_mask = BIT(0), | |
1289 | .hw.init = &(struct clk_init_data){ | |
1290 | .name = "camss_csi0_ahb_clk", | |
1291 | .parent_names = (const char *[]){ | |
1292 | "mmss_ahb_clk_src", | |
1293 | }, | |
1294 | .num_parents = 1, | |
1295 | .ops = &clk_branch2_ops, | |
1296 | }, | |
1297 | }, | |
1298 | }; | |
1299 | ||
1300 | static struct clk_branch camss_csi0_clk = { | |
1301 | .halt_reg = 0x30b4, | |
1302 | .clkr = { | |
1303 | .enable_reg = 0x30b4, | |
1304 | .enable_mask = BIT(0), | |
1305 | .hw.init = &(struct clk_init_data){ | |
1306 | .name = "camss_csi0_clk", | |
1307 | .parent_names = (const char *[]){ | |
1308 | "csi0_clk_src", | |
1309 | }, | |
1310 | .num_parents = 1, | |
1311 | .flags = CLK_SET_RATE_PARENT, | |
1312 | .ops = &clk_branch2_ops, | |
1313 | }, | |
1314 | }, | |
1315 | }; | |
1316 | ||
1317 | static struct clk_branch camss_csi0phy_clk = { | |
1318 | .halt_reg = 0x30c4, | |
1319 | .clkr = { | |
1320 | .enable_reg = 0x30c4, | |
1321 | .enable_mask = BIT(0), | |
1322 | .hw.init = &(struct clk_init_data){ | |
1323 | .name = "camss_csi0phy_clk", | |
1324 | .parent_names = (const char *[]){ | |
1325 | "csi0_clk_src", | |
1326 | }, | |
1327 | .num_parents = 1, | |
1328 | .flags = CLK_SET_RATE_PARENT, | |
1329 | .ops = &clk_branch2_ops, | |
1330 | }, | |
1331 | }, | |
1332 | }; | |
1333 | ||
1334 | static struct clk_branch camss_csi0pix_clk = { | |
1335 | .halt_reg = 0x30e4, | |
1336 | .clkr = { | |
1337 | .enable_reg = 0x30e4, | |
1338 | .enable_mask = BIT(0), | |
1339 | .hw.init = &(struct clk_init_data){ | |
1340 | .name = "camss_csi0pix_clk", | |
1341 | .parent_names = (const char *[]){ | |
1342 | "csi0_clk_src", | |
1343 | }, | |
1344 | .num_parents = 1, | |
1345 | .flags = CLK_SET_RATE_PARENT, | |
1346 | .ops = &clk_branch2_ops, | |
1347 | }, | |
1348 | }, | |
1349 | }; | |
1350 | ||
1351 | static struct clk_branch camss_csi0rdi_clk = { | |
1352 | .halt_reg = 0x30d4, | |
1353 | .clkr = { | |
1354 | .enable_reg = 0x30d4, | |
1355 | .enable_mask = BIT(0), | |
1356 | .hw.init = &(struct clk_init_data){ | |
1357 | .name = "camss_csi0rdi_clk", | |
1358 | .parent_names = (const char *[]){ | |
1359 | "csi0_clk_src", | |
1360 | }, | |
1361 | .num_parents = 1, | |
1362 | .flags = CLK_SET_RATE_PARENT, | |
1363 | .ops = &clk_branch2_ops, | |
1364 | }, | |
1365 | }, | |
1366 | }; | |
1367 | ||
1368 | static struct clk_branch camss_csi1_ahb_clk = { | |
1369 | .halt_reg = 0x3128, | |
1370 | .clkr = { | |
1371 | .enable_reg = 0x3128, | |
1372 | .enable_mask = BIT(0), | |
1373 | .hw.init = &(struct clk_init_data){ | |
1374 | .name = "camss_csi1_ahb_clk", | |
1375 | .parent_names = (const char *[]){ | |
1376 | "mmss_ahb_clk_src", | |
1377 | }, | |
1378 | .num_parents = 1, | |
1379 | .flags = CLK_SET_RATE_PARENT, | |
1380 | .ops = &clk_branch2_ops, | |
1381 | }, | |
1382 | }, | |
1383 | }; | |
1384 | ||
1385 | static struct clk_branch camss_csi1_clk = { | |
1386 | .halt_reg = 0x3124, | |
1387 | .clkr = { | |
1388 | .enable_reg = 0x3124, | |
1389 | .enable_mask = BIT(0), | |
1390 | .hw.init = &(struct clk_init_data){ | |
1391 | .name = "camss_csi1_clk", | |
1392 | .parent_names = (const char *[]){ | |
1393 | "csi1_clk_src", | |
1394 | }, | |
1395 | .num_parents = 1, | |
1396 | .flags = CLK_SET_RATE_PARENT, | |
1397 | .ops = &clk_branch2_ops, | |
1398 | }, | |
1399 | }, | |
1400 | }; | |
1401 | ||
1402 | static struct clk_branch camss_csi1phy_clk = { | |
1403 | .halt_reg = 0x3134, | |
1404 | .clkr = { | |
1405 | .enable_reg = 0x3134, | |
1406 | .enable_mask = BIT(0), | |
1407 | .hw.init = &(struct clk_init_data){ | |
1408 | .name = "camss_csi1phy_clk", | |
1409 | .parent_names = (const char *[]){ | |
1410 | "csi1_clk_src", | |
1411 | }, | |
1412 | .num_parents = 1, | |
1413 | .flags = CLK_SET_RATE_PARENT, | |
1414 | .ops = &clk_branch2_ops, | |
1415 | }, | |
1416 | }, | |
1417 | }; | |
1418 | ||
1419 | static struct clk_branch camss_csi1pix_clk = { | |
1420 | .halt_reg = 0x3154, | |
1421 | .clkr = { | |
1422 | .enable_reg = 0x3154, | |
1423 | .enable_mask = BIT(0), | |
1424 | .hw.init = &(struct clk_init_data){ | |
1425 | .name = "camss_csi1pix_clk", | |
1426 | .parent_names = (const char *[]){ | |
1427 | "csi1_clk_src", | |
1428 | }, | |
1429 | .num_parents = 1, | |
1430 | .flags = CLK_SET_RATE_PARENT, | |
1431 | .ops = &clk_branch2_ops, | |
1432 | }, | |
1433 | }, | |
1434 | }; | |
1435 | ||
1436 | static struct clk_branch camss_csi1rdi_clk = { | |
1437 | .halt_reg = 0x3144, | |
1438 | .clkr = { | |
1439 | .enable_reg = 0x3144, | |
1440 | .enable_mask = BIT(0), | |
1441 | .hw.init = &(struct clk_init_data){ | |
1442 | .name = "camss_csi1rdi_clk", | |
1443 | .parent_names = (const char *[]){ | |
1444 | "csi1_clk_src", | |
1445 | }, | |
1446 | .num_parents = 1, | |
1447 | .flags = CLK_SET_RATE_PARENT, | |
1448 | .ops = &clk_branch2_ops, | |
1449 | }, | |
1450 | }, | |
1451 | }; | |
1452 | ||
1453 | static struct clk_branch camss_csi2_ahb_clk = { | |
1454 | .halt_reg = 0x3188, | |
1455 | .clkr = { | |
1456 | .enable_reg = 0x3188, | |
1457 | .enable_mask = BIT(0), | |
1458 | .hw.init = &(struct clk_init_data){ | |
1459 | .name = "camss_csi2_ahb_clk", | |
1460 | .parent_names = (const char *[]){ | |
1461 | "mmss_ahb_clk_src", | |
1462 | }, | |
1463 | .num_parents = 1, | |
1464 | .ops = &clk_branch2_ops, | |
1465 | }, | |
1466 | }, | |
1467 | }; | |
1468 | ||
1469 | static struct clk_branch camss_csi2_clk = { | |
1470 | .halt_reg = 0x3184, | |
1471 | .clkr = { | |
1472 | .enable_reg = 0x3184, | |
1473 | .enable_mask = BIT(0), | |
1474 | .hw.init = &(struct clk_init_data){ | |
1475 | .name = "camss_csi2_clk", | |
1476 | .parent_names = (const char *[]){ | |
1477 | "csi2_clk_src", | |
1478 | }, | |
1479 | .num_parents = 1, | |
1480 | .flags = CLK_SET_RATE_PARENT, | |
1481 | .ops = &clk_branch2_ops, | |
1482 | }, | |
1483 | }, | |
1484 | }; | |
1485 | ||
1486 | static struct clk_branch camss_csi2phy_clk = { | |
1487 | .halt_reg = 0x3194, | |
1488 | .clkr = { | |
1489 | .enable_reg = 0x3194, | |
1490 | .enable_mask = BIT(0), | |
1491 | .hw.init = &(struct clk_init_data){ | |
1492 | .name = "camss_csi2phy_clk", | |
1493 | .parent_names = (const char *[]){ | |
1494 | "csi2_clk_src", | |
1495 | }, | |
1496 | .num_parents = 1, | |
1497 | .flags = CLK_SET_RATE_PARENT, | |
1498 | .ops = &clk_branch2_ops, | |
1499 | }, | |
1500 | }, | |
1501 | }; | |
1502 | ||
1503 | static struct clk_branch camss_csi2pix_clk = { | |
1504 | .halt_reg = 0x31b4, | |
1505 | .clkr = { | |
1506 | .enable_reg = 0x31b4, | |
1507 | .enable_mask = BIT(0), | |
1508 | .hw.init = &(struct clk_init_data){ | |
1509 | .name = "camss_csi2pix_clk", | |
1510 | .parent_names = (const char *[]){ | |
1511 | "csi2_clk_src", | |
1512 | }, | |
1513 | .num_parents = 1, | |
1514 | .flags = CLK_SET_RATE_PARENT, | |
1515 | .ops = &clk_branch2_ops, | |
1516 | }, | |
1517 | }, | |
1518 | }; | |
1519 | ||
1520 | static struct clk_branch camss_csi2rdi_clk = { | |
1521 | .halt_reg = 0x31a4, | |
1522 | .clkr = { | |
1523 | .enable_reg = 0x31a4, | |
1524 | .enable_mask = BIT(0), | |
1525 | .hw.init = &(struct clk_init_data){ | |
1526 | .name = "camss_csi2rdi_clk", | |
1527 | .parent_names = (const char *[]){ | |
1528 | "csi2_clk_src", | |
1529 | }, | |
1530 | .num_parents = 1, | |
1531 | .flags = CLK_SET_RATE_PARENT, | |
1532 | .ops = &clk_branch2_ops, | |
1533 | }, | |
1534 | }, | |
1535 | }; | |
1536 | ||
1537 | static struct clk_branch camss_csi3_ahb_clk = { | |
1538 | .halt_reg = 0x31e8, | |
1539 | .clkr = { | |
1540 | .enable_reg = 0x31e8, | |
1541 | .enable_mask = BIT(0), | |
1542 | .hw.init = &(struct clk_init_data){ | |
1543 | .name = "camss_csi3_ahb_clk", | |
1544 | .parent_names = (const char *[]){ | |
1545 | "mmss_ahb_clk_src", | |
1546 | }, | |
1547 | .num_parents = 1, | |
1548 | .ops = &clk_branch2_ops, | |
1549 | }, | |
1550 | }, | |
1551 | }; | |
1552 | ||
1553 | static struct clk_branch camss_csi3_clk = { | |
1554 | .halt_reg = 0x31e4, | |
1555 | .clkr = { | |
1556 | .enable_reg = 0x31e4, | |
1557 | .enable_mask = BIT(0), | |
1558 | .hw.init = &(struct clk_init_data){ | |
1559 | .name = "camss_csi3_clk", | |
1560 | .parent_names = (const char *[]){ | |
1561 | "csi3_clk_src", | |
1562 | }, | |
1563 | .num_parents = 1, | |
1564 | .flags = CLK_SET_RATE_PARENT, | |
1565 | .ops = &clk_branch2_ops, | |
1566 | }, | |
1567 | }, | |
1568 | }; | |
1569 | ||
1570 | static struct clk_branch camss_csi3phy_clk = { | |
1571 | .halt_reg = 0x31f4, | |
1572 | .clkr = { | |
1573 | .enable_reg = 0x31f4, | |
1574 | .enable_mask = BIT(0), | |
1575 | .hw.init = &(struct clk_init_data){ | |
1576 | .name = "camss_csi3phy_clk", | |
1577 | .parent_names = (const char *[]){ | |
1578 | "csi3_clk_src", | |
1579 | }, | |
1580 | .num_parents = 1, | |
1581 | .flags = CLK_SET_RATE_PARENT, | |
1582 | .ops = &clk_branch2_ops, | |
1583 | }, | |
1584 | }, | |
1585 | }; | |
1586 | ||
1587 | static struct clk_branch camss_csi3pix_clk = { | |
1588 | .halt_reg = 0x3214, | |
1589 | .clkr = { | |
1590 | .enable_reg = 0x3214, | |
1591 | .enable_mask = BIT(0), | |
1592 | .hw.init = &(struct clk_init_data){ | |
1593 | .name = "camss_csi3pix_clk", | |
1594 | .parent_names = (const char *[]){ | |
1595 | "csi3_clk_src", | |
1596 | }, | |
1597 | .num_parents = 1, | |
1598 | .flags = CLK_SET_RATE_PARENT, | |
1599 | .ops = &clk_branch2_ops, | |
1600 | }, | |
1601 | }, | |
1602 | }; | |
1603 | ||
1604 | static struct clk_branch camss_csi3rdi_clk = { | |
1605 | .halt_reg = 0x3204, | |
1606 | .clkr = { | |
1607 | .enable_reg = 0x3204, | |
1608 | .enable_mask = BIT(0), | |
1609 | .hw.init = &(struct clk_init_data){ | |
1610 | .name = "camss_csi3rdi_clk", | |
1611 | .parent_names = (const char *[]){ | |
1612 | "csi3_clk_src", | |
1613 | }, | |
1614 | .num_parents = 1, | |
1615 | .flags = CLK_SET_RATE_PARENT, | |
1616 | .ops = &clk_branch2_ops, | |
1617 | }, | |
1618 | }, | |
1619 | }; | |
1620 | ||
1621 | static struct clk_branch camss_csi_vfe0_clk = { | |
1622 | .halt_reg = 0x3704, | |
1623 | .clkr = { | |
1624 | .enable_reg = 0x3704, | |
1625 | .enable_mask = BIT(0), | |
1626 | .hw.init = &(struct clk_init_data){ | |
1627 | .name = "camss_csi_vfe0_clk", | |
1628 | .parent_names = (const char *[]){ | |
1629 | "vfe0_clk_src", | |
1630 | }, | |
1631 | .num_parents = 1, | |
1632 | .flags = CLK_SET_RATE_PARENT, | |
1633 | .ops = &clk_branch2_ops, | |
1634 | }, | |
1635 | }, | |
1636 | }; | |
1637 | ||
1638 | static struct clk_branch camss_csi_vfe1_clk = { | |
1639 | .halt_reg = 0x3714, | |
1640 | .clkr = { | |
1641 | .enable_reg = 0x3714, | |
1642 | .enable_mask = BIT(0), | |
1643 | .hw.init = &(struct clk_init_data){ | |
1644 | .name = "camss_csi_vfe1_clk", | |
1645 | .parent_names = (const char *[]){ | |
1646 | "vfe1_clk_src", | |
1647 | }, | |
1648 | .num_parents = 1, | |
1649 | .flags = CLK_SET_RATE_PARENT, | |
1650 | .ops = &clk_branch2_ops, | |
1651 | }, | |
1652 | }, | |
1653 | }; | |
1654 | ||
1655 | static struct clk_branch camss_gp0_clk = { | |
1656 | .halt_reg = 0x3444, | |
1657 | .clkr = { | |
1658 | .enable_reg = 0x3444, | |
1659 | .enable_mask = BIT(0), | |
1660 | .hw.init = &(struct clk_init_data){ | |
1661 | .name = "camss_gp0_clk", | |
1662 | .parent_names = (const char *[]){ | |
1663 | "camss_gp0_clk_src", | |
1664 | }, | |
1665 | .num_parents = 1, | |
1666 | .flags = CLK_SET_RATE_PARENT, | |
1667 | .ops = &clk_branch2_ops, | |
1668 | }, | |
1669 | }, | |
1670 | }; | |
1671 | ||
1672 | static struct clk_branch camss_gp1_clk = { | |
1673 | .halt_reg = 0x3474, | |
1674 | .clkr = { | |
1675 | .enable_reg = 0x3474, | |
1676 | .enable_mask = BIT(0), | |
1677 | .hw.init = &(struct clk_init_data){ | |
1678 | .name = "camss_gp1_clk", | |
1679 | .parent_names = (const char *[]){ | |
1680 | "camss_gp1_clk_src", | |
1681 | }, | |
1682 | .num_parents = 1, | |
1683 | .flags = CLK_SET_RATE_PARENT, | |
1684 | .ops = &clk_branch2_ops, | |
1685 | }, | |
1686 | }, | |
1687 | }; | |
1688 | ||
1689 | static struct clk_branch camss_ispif_ahb_clk = { | |
1690 | .halt_reg = 0x3224, | |
1691 | .clkr = { | |
1692 | .enable_reg = 0x3224, | |
1693 | .enable_mask = BIT(0), | |
1694 | .hw.init = &(struct clk_init_data){ | |
1695 | .name = "camss_ispif_ahb_clk", | |
1696 | .parent_names = (const char *[]){ | |
1697 | "mmss_ahb_clk_src", | |
1698 | }, | |
1699 | .num_parents = 1, | |
1700 | .flags = CLK_SET_RATE_PARENT, | |
1701 | .ops = &clk_branch2_ops, | |
1702 | }, | |
1703 | }, | |
1704 | }; | |
1705 | ||
1706 | static struct clk_branch camss_jpeg_jpeg0_clk = { | |
1707 | .halt_reg = 0x35a8, | |
1708 | .clkr = { | |
1709 | .enable_reg = 0x35a8, | |
1710 | .enable_mask = BIT(0), | |
1711 | .hw.init = &(struct clk_init_data){ | |
1712 | .name = "camss_jpeg_jpeg0_clk", | |
1713 | .parent_names = (const char *[]){ | |
1714 | "jpeg0_clk_src", | |
1715 | }, | |
1716 | .num_parents = 1, | |
1717 | .flags = CLK_SET_RATE_PARENT, | |
1718 | .ops = &clk_branch2_ops, | |
1719 | }, | |
1720 | }, | |
1721 | }; | |
1722 | ||
1723 | static struct clk_branch camss_jpeg_jpeg1_clk = { | |
1724 | .halt_reg = 0x35ac, | |
1725 | .clkr = { | |
1726 | .enable_reg = 0x35ac, | |
1727 | .enable_mask = BIT(0), | |
1728 | .hw.init = &(struct clk_init_data){ | |
1729 | .name = "camss_jpeg_jpeg1_clk", | |
1730 | .parent_names = (const char *[]){ | |
1731 | "jpeg1_clk_src", | |
1732 | }, | |
1733 | .num_parents = 1, | |
1734 | .flags = CLK_SET_RATE_PARENT, | |
1735 | .ops = &clk_branch2_ops, | |
1736 | }, | |
1737 | }, | |
1738 | }; | |
1739 | ||
1740 | static struct clk_branch camss_jpeg_jpeg2_clk = { | |
1741 | .halt_reg = 0x35b0, | |
1742 | .clkr = { | |
1743 | .enable_reg = 0x35b0, | |
1744 | .enable_mask = BIT(0), | |
1745 | .hw.init = &(struct clk_init_data){ | |
1746 | .name = "camss_jpeg_jpeg2_clk", | |
1747 | .parent_names = (const char *[]){ | |
1748 | "jpeg2_clk_src", | |
1749 | }, | |
1750 | .num_parents = 1, | |
1751 | .flags = CLK_SET_RATE_PARENT, | |
1752 | .ops = &clk_branch2_ops, | |
1753 | }, | |
1754 | }, | |
1755 | }; | |
1756 | ||
1757 | static struct clk_branch camss_jpeg_jpeg_ahb_clk = { | |
1758 | .halt_reg = 0x35b4, | |
1759 | .clkr = { | |
1760 | .enable_reg = 0x35b4, | |
1761 | .enable_mask = BIT(0), | |
1762 | .hw.init = &(struct clk_init_data){ | |
1763 | .name = "camss_jpeg_jpeg_ahb_clk", | |
1764 | .parent_names = (const char *[]){ | |
1765 | "mmss_ahb_clk_src", | |
1766 | }, | |
1767 | .num_parents = 1, | |
1768 | .ops = &clk_branch2_ops, | |
1769 | }, | |
1770 | }, | |
1771 | }; | |
1772 | ||
1773 | static struct clk_branch camss_jpeg_jpeg_axi_clk = { | |
1774 | .halt_reg = 0x35b8, | |
1775 | .clkr = { | |
1776 | .enable_reg = 0x35b8, | |
1777 | .enable_mask = BIT(0), | |
1778 | .hw.init = &(struct clk_init_data){ | |
1779 | .name = "camss_jpeg_jpeg_axi_clk", | |
1780 | .parent_names = (const char *[]){ | |
1781 | "mmss_axi_clk_src", | |
1782 | }, | |
1783 | .num_parents = 1, | |
1784 | .ops = &clk_branch2_ops, | |
1785 | }, | |
1786 | }, | |
1787 | }; | |
1788 | ||
1789 | static struct clk_branch camss_mclk0_clk = { | |
1790 | .halt_reg = 0x3384, | |
1791 | .clkr = { | |
1792 | .enable_reg = 0x3384, | |
1793 | .enable_mask = BIT(0), | |
1794 | .hw.init = &(struct clk_init_data){ | |
1795 | .name = "camss_mclk0_clk", | |
1796 | .parent_names = (const char *[]){ | |
1797 | "mclk0_clk_src", | |
1798 | }, | |
1799 | .num_parents = 1, | |
1800 | .flags = CLK_SET_RATE_PARENT, | |
1801 | .ops = &clk_branch2_ops, | |
1802 | }, | |
1803 | }, | |
1804 | }; | |
1805 | ||
1806 | static struct clk_branch camss_mclk1_clk = { | |
1807 | .halt_reg = 0x33b4, | |
1808 | .clkr = { | |
1809 | .enable_reg = 0x33b4, | |
1810 | .enable_mask = BIT(0), | |
1811 | .hw.init = &(struct clk_init_data){ | |
1812 | .name = "camss_mclk1_clk", | |
1813 | .parent_names = (const char *[]){ | |
1814 | "mclk1_clk_src", | |
1815 | }, | |
1816 | .num_parents = 1, | |
1817 | .flags = CLK_SET_RATE_PARENT, | |
1818 | .ops = &clk_branch2_ops, | |
1819 | }, | |
1820 | }, | |
1821 | }; | |
1822 | ||
1823 | static struct clk_branch camss_mclk2_clk = { | |
1824 | .halt_reg = 0x33e4, | |
1825 | .clkr = { | |
1826 | .enable_reg = 0x33e4, | |
1827 | .enable_mask = BIT(0), | |
1828 | .hw.init = &(struct clk_init_data){ | |
1829 | .name = "camss_mclk2_clk", | |
1830 | .parent_names = (const char *[]){ | |
1831 | "mclk2_clk_src", | |
1832 | }, | |
1833 | .num_parents = 1, | |
1834 | .flags = CLK_SET_RATE_PARENT, | |
1835 | .ops = &clk_branch2_ops, | |
1836 | }, | |
1837 | }, | |
1838 | }; | |
1839 | ||
1840 | static struct clk_branch camss_mclk3_clk = { | |
1841 | .halt_reg = 0x3414, | |
1842 | .clkr = { | |
1843 | .enable_reg = 0x3414, | |
1844 | .enable_mask = BIT(0), | |
1845 | .hw.init = &(struct clk_init_data){ | |
1846 | .name = "camss_mclk3_clk", | |
1847 | .parent_names = (const char *[]){ | |
1848 | "mclk3_clk_src", | |
1849 | }, | |
1850 | .num_parents = 1, | |
1851 | .flags = CLK_SET_RATE_PARENT, | |
1852 | .ops = &clk_branch2_ops, | |
1853 | }, | |
1854 | }, | |
1855 | }; | |
1856 | ||
1857 | static struct clk_branch camss_micro_ahb_clk = { | |
1858 | .halt_reg = 0x3494, | |
1859 | .clkr = { | |
1860 | .enable_reg = 0x3494, | |
1861 | .enable_mask = BIT(0), | |
1862 | .hw.init = &(struct clk_init_data){ | |
1863 | .name = "camss_micro_ahb_clk", | |
1864 | .parent_names = (const char *[]){ | |
1865 | "mmss_ahb_clk_src", | |
1866 | }, | |
1867 | .num_parents = 1, | |
1868 | .ops = &clk_branch2_ops, | |
1869 | }, | |
1870 | }, | |
1871 | }; | |
1872 | ||
1873 | static struct clk_branch camss_phy0_csi0phytimer_clk = { | |
1874 | .halt_reg = 0x3024, | |
1875 | .clkr = { | |
1876 | .enable_reg = 0x3024, | |
1877 | .enable_mask = BIT(0), | |
1878 | .hw.init = &(struct clk_init_data){ | |
1879 | .name = "camss_phy0_csi0phytimer_clk", | |
1880 | .parent_names = (const char *[]){ | |
1881 | "csi0phytimer_clk_src", | |
1882 | }, | |
1883 | .num_parents = 1, | |
1884 | .flags = CLK_SET_RATE_PARENT, | |
1885 | .ops = &clk_branch2_ops, | |
1886 | }, | |
1887 | }, | |
1888 | }; | |
1889 | ||
1890 | static struct clk_branch camss_phy1_csi1phytimer_clk = { | |
1891 | .halt_reg = 0x3054, | |
1892 | .clkr = { | |
1893 | .enable_reg = 0x3054, | |
1894 | .enable_mask = BIT(0), | |
1895 | .hw.init = &(struct clk_init_data){ | |
1896 | .name = "camss_phy1_csi1phytimer_clk", | |
1897 | .parent_names = (const char *[]){ | |
1898 | "csi1phytimer_clk_src", | |
1899 | }, | |
1900 | .num_parents = 1, | |
1901 | .flags = CLK_SET_RATE_PARENT, | |
1902 | .ops = &clk_branch2_ops, | |
1903 | }, | |
1904 | }, | |
1905 | }; | |
1906 | ||
1907 | static struct clk_branch camss_phy2_csi2phytimer_clk = { | |
1908 | .halt_reg = 0x3084, | |
1909 | .clkr = { | |
1910 | .enable_reg = 0x3084, | |
1911 | .enable_mask = BIT(0), | |
1912 | .hw.init = &(struct clk_init_data){ | |
1913 | .name = "camss_phy2_csi2phytimer_clk", | |
1914 | .parent_names = (const char *[]){ | |
1915 | "csi2phytimer_clk_src", | |
1916 | }, | |
1917 | .num_parents = 1, | |
1918 | .flags = CLK_SET_RATE_PARENT, | |
1919 | .ops = &clk_branch2_ops, | |
1920 | }, | |
1921 | }, | |
1922 | }; | |
1923 | ||
1924 | static struct clk_branch camss_top_ahb_clk = { | |
1925 | .halt_reg = 0x3484, | |
1926 | .clkr = { | |
1927 | .enable_reg = 0x3484, | |
1928 | .enable_mask = BIT(0), | |
1929 | .hw.init = &(struct clk_init_data){ | |
1930 | .name = "camss_top_ahb_clk", | |
1931 | .parent_names = (const char *[]){ | |
1932 | "mmss_ahb_clk_src", | |
1933 | }, | |
1934 | .num_parents = 1, | |
1935 | .flags = CLK_SET_RATE_PARENT, | |
1936 | .ops = &clk_branch2_ops, | |
1937 | }, | |
1938 | }, | |
1939 | }; | |
1940 | ||
1941 | static struct clk_branch camss_vfe_cpp_ahb_clk = { | |
1942 | .halt_reg = 0x36b4, | |
1943 | .clkr = { | |
1944 | .enable_reg = 0x36b4, | |
1945 | .enable_mask = BIT(0), | |
1946 | .hw.init = &(struct clk_init_data){ | |
1947 | .name = "camss_vfe_cpp_ahb_clk", | |
1948 | .parent_names = (const char *[]){ | |
1949 | "mmss_ahb_clk_src", | |
1950 | }, | |
1951 | .num_parents = 1, | |
1952 | .flags = CLK_SET_RATE_PARENT, | |
1953 | .ops = &clk_branch2_ops, | |
1954 | }, | |
1955 | }, | |
1956 | }; | |
1957 | ||
1958 | static struct clk_branch camss_vfe_cpp_clk = { | |
1959 | .halt_reg = 0x36b0, | |
1960 | .clkr = { | |
1961 | .enable_reg = 0x36b0, | |
1962 | .enable_mask = BIT(0), | |
1963 | .hw.init = &(struct clk_init_data){ | |
1964 | .name = "camss_vfe_cpp_clk", | |
1965 | .parent_names = (const char *[]){ | |
1966 | "cpp_clk_src", | |
1967 | }, | |
1968 | .num_parents = 1, | |
1969 | .flags = CLK_SET_RATE_PARENT, | |
1970 | .ops = &clk_branch2_ops, | |
1971 | }, | |
1972 | }, | |
1973 | }; | |
1974 | ||
1975 | static struct clk_branch camss_vfe_vfe0_clk = { | |
1976 | .halt_reg = 0x36a8, | |
1977 | .clkr = { | |
1978 | .enable_reg = 0x36a8, | |
1979 | .enable_mask = BIT(0), | |
1980 | .hw.init = &(struct clk_init_data){ | |
1981 | .name = "camss_vfe_vfe0_clk", | |
1982 | .parent_names = (const char *[]){ | |
1983 | "vfe0_clk_src", | |
1984 | }, | |
1985 | .num_parents = 1, | |
1986 | .flags = CLK_SET_RATE_PARENT, | |
1987 | .ops = &clk_branch2_ops, | |
1988 | }, | |
1989 | }, | |
1990 | }; | |
1991 | ||
1992 | static struct clk_branch camss_vfe_vfe1_clk = { | |
1993 | .halt_reg = 0x36ac, | |
1994 | .clkr = { | |
1995 | .enable_reg = 0x36ac, | |
1996 | .enable_mask = BIT(0), | |
1997 | .hw.init = &(struct clk_init_data){ | |
1998 | .name = "camss_vfe_vfe1_clk", | |
1999 | .parent_names = (const char *[]){ | |
2000 | "vfe1_clk_src", | |
2001 | }, | |
2002 | .num_parents = 1, | |
2003 | .flags = CLK_SET_RATE_PARENT, | |
2004 | .ops = &clk_branch2_ops, | |
2005 | }, | |
2006 | }, | |
2007 | }; | |
2008 | ||
2009 | static struct clk_branch camss_vfe_vfe_ahb_clk = { | |
2010 | .halt_reg = 0x36b8, | |
2011 | .clkr = { | |
2012 | .enable_reg = 0x36b8, | |
2013 | .enable_mask = BIT(0), | |
2014 | .hw.init = &(struct clk_init_data){ | |
2015 | .name = "camss_vfe_vfe_ahb_clk", | |
2016 | .parent_names = (const char *[]){ | |
2017 | "mmss_ahb_clk_src", | |
2018 | }, | |
2019 | .num_parents = 1, | |
2020 | .flags = CLK_SET_RATE_PARENT, | |
2021 | .ops = &clk_branch2_ops, | |
2022 | }, | |
2023 | }, | |
2024 | }; | |
2025 | ||
2026 | static struct clk_branch camss_vfe_vfe_axi_clk = { | |
2027 | .halt_reg = 0x36bc, | |
2028 | .clkr = { | |
2029 | .enable_reg = 0x36bc, | |
2030 | .enable_mask = BIT(0), | |
2031 | .hw.init = &(struct clk_init_data){ | |
2032 | .name = "camss_vfe_vfe_axi_clk", | |
2033 | .parent_names = (const char *[]){ | |
2034 | "mmss_axi_clk_src", | |
2035 | }, | |
2036 | .num_parents = 1, | |
2037 | .flags = CLK_SET_RATE_PARENT, | |
2038 | .ops = &clk_branch2_ops, | |
2039 | }, | |
2040 | }, | |
2041 | }; | |
2042 | ||
2043 | static struct clk_branch mdss_ahb_clk = { | |
2044 | .halt_reg = 0x2308, | |
2045 | .clkr = { | |
2046 | .enable_reg = 0x2308, | |
2047 | .enable_mask = BIT(0), | |
2048 | .hw.init = &(struct clk_init_data){ | |
2049 | .name = "mdss_ahb_clk", | |
2050 | .parent_names = (const char *[]){ | |
2051 | "mmss_ahb_clk_src", | |
2052 | }, | |
2053 | .num_parents = 1, | |
2054 | .flags = CLK_SET_RATE_PARENT, | |
2055 | .ops = &clk_branch2_ops, | |
2056 | }, | |
2057 | }, | |
2058 | }; | |
2059 | ||
2060 | static struct clk_branch mdss_axi_clk = { | |
2061 | .halt_reg = 0x2310, | |
2062 | .clkr = { | |
2063 | .enable_reg = 0x2310, | |
2064 | .enable_mask = BIT(0), | |
2065 | .hw.init = &(struct clk_init_data){ | |
2066 | .name = "mdss_axi_clk", | |
2067 | .parent_names = (const char *[]){ | |
2068 | "mmss_axi_clk_src", | |
2069 | }, | |
2070 | .num_parents = 1, | |
2071 | .flags = CLK_SET_RATE_PARENT, | |
2072 | .ops = &clk_branch2_ops, | |
2073 | }, | |
2074 | }, | |
2075 | }; | |
2076 | ||
2077 | static struct clk_branch mdss_byte0_clk = { | |
2078 | .halt_reg = 0x233c, | |
2079 | .clkr = { | |
2080 | .enable_reg = 0x233c, | |
2081 | .enable_mask = BIT(0), | |
2082 | .hw.init = &(struct clk_init_data){ | |
2083 | .name = "mdss_byte0_clk", | |
2084 | .parent_names = (const char *[]){ | |
2085 | "byte0_clk_src", | |
2086 | }, | |
2087 | .num_parents = 1, | |
2088 | .flags = CLK_SET_RATE_PARENT, | |
2089 | .ops = &clk_branch2_ops, | |
2090 | }, | |
2091 | }, | |
2092 | }; | |
2093 | ||
2094 | static struct clk_branch mdss_byte1_clk = { | |
2095 | .halt_reg = 0x2340, | |
2096 | .clkr = { | |
2097 | .enable_reg = 0x2340, | |
2098 | .enable_mask = BIT(0), | |
2099 | .hw.init = &(struct clk_init_data){ | |
2100 | .name = "mdss_byte1_clk", | |
2101 | .parent_names = (const char *[]){ | |
2102 | "byte1_clk_src", | |
2103 | }, | |
2104 | .num_parents = 1, | |
2105 | .flags = CLK_SET_RATE_PARENT, | |
2106 | .ops = &clk_branch2_ops, | |
2107 | }, | |
2108 | }, | |
2109 | }; | |
2110 | ||
2111 | static struct clk_branch mdss_edpaux_clk = { | |
2112 | .halt_reg = 0x2334, | |
2113 | .clkr = { | |
2114 | .enable_reg = 0x2334, | |
2115 | .enable_mask = BIT(0), | |
2116 | .hw.init = &(struct clk_init_data){ | |
2117 | .name = "mdss_edpaux_clk", | |
2118 | .parent_names = (const char *[]){ | |
2119 | "edpaux_clk_src", | |
2120 | }, | |
2121 | .num_parents = 1, | |
2122 | .flags = CLK_SET_RATE_PARENT, | |
2123 | .ops = &clk_branch2_ops, | |
2124 | }, | |
2125 | }, | |
2126 | }; | |
2127 | ||
2128 | static struct clk_branch mdss_edplink_clk = { | |
2129 | .halt_reg = 0x2330, | |
2130 | .clkr = { | |
2131 | .enable_reg = 0x2330, | |
2132 | .enable_mask = BIT(0), | |
2133 | .hw.init = &(struct clk_init_data){ | |
2134 | .name = "mdss_edplink_clk", | |
2135 | .parent_names = (const char *[]){ | |
2136 | "edplink_clk_src", | |
2137 | }, | |
2138 | .num_parents = 1, | |
2139 | .flags = CLK_SET_RATE_PARENT, | |
2140 | .ops = &clk_branch2_ops, | |
2141 | }, | |
2142 | }, | |
2143 | }; | |
2144 | ||
2145 | static struct clk_branch mdss_edppixel_clk = { | |
2146 | .halt_reg = 0x232c, | |
2147 | .clkr = { | |
2148 | .enable_reg = 0x232c, | |
2149 | .enable_mask = BIT(0), | |
2150 | .hw.init = &(struct clk_init_data){ | |
2151 | .name = "mdss_edppixel_clk", | |
2152 | .parent_names = (const char *[]){ | |
2153 | "edppixel_clk_src", | |
2154 | }, | |
2155 | .num_parents = 1, | |
2156 | .flags = CLK_SET_RATE_PARENT, | |
2157 | .ops = &clk_branch2_ops, | |
2158 | }, | |
2159 | }, | |
2160 | }; | |
2161 | ||
2162 | static struct clk_branch mdss_esc0_clk = { | |
2163 | .halt_reg = 0x2344, | |
2164 | .clkr = { | |
2165 | .enable_reg = 0x2344, | |
2166 | .enable_mask = BIT(0), | |
2167 | .hw.init = &(struct clk_init_data){ | |
2168 | .name = "mdss_esc0_clk", | |
2169 | .parent_names = (const char *[]){ | |
2170 | "esc0_clk_src", | |
2171 | }, | |
2172 | .num_parents = 1, | |
2173 | .flags = CLK_SET_RATE_PARENT, | |
2174 | .ops = &clk_branch2_ops, | |
2175 | }, | |
2176 | }, | |
2177 | }; | |
2178 | ||
2179 | static struct clk_branch mdss_esc1_clk = { | |
2180 | .halt_reg = 0x2348, | |
2181 | .clkr = { | |
2182 | .enable_reg = 0x2348, | |
2183 | .enable_mask = BIT(0), | |
2184 | .hw.init = &(struct clk_init_data){ | |
2185 | .name = "mdss_esc1_clk", | |
2186 | .parent_names = (const char *[]){ | |
2187 | "esc1_clk_src", | |
2188 | }, | |
2189 | .num_parents = 1, | |
2190 | .flags = CLK_SET_RATE_PARENT, | |
2191 | .ops = &clk_branch2_ops, | |
2192 | }, | |
2193 | }, | |
2194 | }; | |
2195 | ||
2196 | static struct clk_branch mdss_extpclk_clk = { | |
2197 | .halt_reg = 0x2324, | |
2198 | .clkr = { | |
2199 | .enable_reg = 0x2324, | |
2200 | .enable_mask = BIT(0), | |
2201 | .hw.init = &(struct clk_init_data){ | |
2202 | .name = "mdss_extpclk_clk", | |
2203 | .parent_names = (const char *[]){ | |
2204 | "extpclk_clk_src", | |
2205 | }, | |
2206 | .num_parents = 1, | |
2207 | .flags = CLK_SET_RATE_PARENT, | |
2208 | .ops = &clk_branch2_ops, | |
2209 | }, | |
2210 | }, | |
2211 | }; | |
2212 | ||
2213 | static struct clk_branch mdss_hdmi_ahb_clk = { | |
2214 | .halt_reg = 0x230c, | |
2215 | .clkr = { | |
2216 | .enable_reg = 0x230c, | |
2217 | .enable_mask = BIT(0), | |
2218 | .hw.init = &(struct clk_init_data){ | |
2219 | .name = "mdss_hdmi_ahb_clk", | |
2220 | .parent_names = (const char *[]){ | |
2221 | "mmss_ahb_clk_src", | |
2222 | }, | |
2223 | .num_parents = 1, | |
2224 | .flags = CLK_SET_RATE_PARENT, | |
2225 | .ops = &clk_branch2_ops, | |
2226 | }, | |
2227 | }, | |
2228 | }; | |
2229 | ||
2230 | static struct clk_branch mdss_hdmi_clk = { | |
2231 | .halt_reg = 0x2338, | |
2232 | .clkr = { | |
2233 | .enable_reg = 0x2338, | |
2234 | .enable_mask = BIT(0), | |
2235 | .hw.init = &(struct clk_init_data){ | |
2236 | .name = "mdss_hdmi_clk", | |
2237 | .parent_names = (const char *[]){ | |
2238 | "hdmi_clk_src", | |
2239 | }, | |
2240 | .num_parents = 1, | |
2241 | .flags = CLK_SET_RATE_PARENT, | |
2242 | .ops = &clk_branch2_ops, | |
2243 | }, | |
2244 | }, | |
2245 | }; | |
2246 | ||
2247 | static struct clk_branch mdss_mdp_clk = { | |
2248 | .halt_reg = 0x231c, | |
2249 | .clkr = { | |
2250 | .enable_reg = 0x231c, | |
2251 | .enable_mask = BIT(0), | |
2252 | .hw.init = &(struct clk_init_data){ | |
2253 | .name = "mdss_mdp_clk", | |
2254 | .parent_names = (const char *[]){ | |
2255 | "mdp_clk_src", | |
2256 | }, | |
2257 | .num_parents = 1, | |
2258 | .flags = CLK_SET_RATE_PARENT, | |
2259 | .ops = &clk_branch2_ops, | |
2260 | }, | |
2261 | }, | |
2262 | }; | |
2263 | ||
2264 | static struct clk_branch mdss_mdp_lut_clk = { | |
2265 | .halt_reg = 0x2320, | |
2266 | .clkr = { | |
2267 | .enable_reg = 0x2320, | |
2268 | .enable_mask = BIT(0), | |
2269 | .hw.init = &(struct clk_init_data){ | |
2270 | .name = "mdss_mdp_lut_clk", | |
2271 | .parent_names = (const char *[]){ | |
2272 | "mdp_clk_src", | |
2273 | }, | |
2274 | .num_parents = 1, | |
2275 | .flags = CLK_SET_RATE_PARENT, | |
2276 | .ops = &clk_branch2_ops, | |
2277 | }, | |
2278 | }, | |
2279 | }; | |
2280 | ||
2281 | static struct clk_branch mdss_pclk0_clk = { | |
2282 | .halt_reg = 0x2314, | |
2283 | .clkr = { | |
2284 | .enable_reg = 0x2314, | |
2285 | .enable_mask = BIT(0), | |
2286 | .hw.init = &(struct clk_init_data){ | |
2287 | .name = "mdss_pclk0_clk", | |
2288 | .parent_names = (const char *[]){ | |
2289 | "pclk0_clk_src", | |
2290 | }, | |
2291 | .num_parents = 1, | |
2292 | .flags = CLK_SET_RATE_PARENT, | |
2293 | .ops = &clk_branch2_ops, | |
2294 | }, | |
2295 | }, | |
2296 | }; | |
2297 | ||
2298 | static struct clk_branch mdss_pclk1_clk = { | |
2299 | .halt_reg = 0x2318, | |
2300 | .clkr = { | |
2301 | .enable_reg = 0x2318, | |
2302 | .enable_mask = BIT(0), | |
2303 | .hw.init = &(struct clk_init_data){ | |
2304 | .name = "mdss_pclk1_clk", | |
2305 | .parent_names = (const char *[]){ | |
2306 | "pclk1_clk_src", | |
2307 | }, | |
2308 | .num_parents = 1, | |
2309 | .flags = CLK_SET_RATE_PARENT, | |
2310 | .ops = &clk_branch2_ops, | |
2311 | }, | |
2312 | }, | |
2313 | }; | |
2314 | ||
2315 | static struct clk_branch mdss_vsync_clk = { | |
2316 | .halt_reg = 0x2328, | |
2317 | .clkr = { | |
2318 | .enable_reg = 0x2328, | |
2319 | .enable_mask = BIT(0), | |
2320 | .hw.init = &(struct clk_init_data){ | |
2321 | .name = "mdss_vsync_clk", | |
2322 | .parent_names = (const char *[]){ | |
2323 | "vsync_clk_src", | |
2324 | }, | |
2325 | .num_parents = 1, | |
2326 | .flags = CLK_SET_RATE_PARENT, | |
2327 | .ops = &clk_branch2_ops, | |
2328 | }, | |
2329 | }, | |
2330 | }; | |
2331 | ||
2332 | static struct clk_branch mmss_rbcpr_ahb_clk = { | |
2333 | .halt_reg = 0x4088, | |
2334 | .clkr = { | |
2335 | .enable_reg = 0x4088, | |
2336 | .enable_mask = BIT(0), | |
2337 | .hw.init = &(struct clk_init_data){ | |
2338 | .name = "mmss_rbcpr_ahb_clk", | |
2339 | .parent_names = (const char *[]){ | |
2340 | "mmss_ahb_clk_src", | |
2341 | }, | |
2342 | .num_parents = 1, | |
2343 | .flags = CLK_SET_RATE_PARENT, | |
2344 | .ops = &clk_branch2_ops, | |
2345 | }, | |
2346 | }, | |
2347 | }; | |
2348 | ||
2349 | static struct clk_branch mmss_rbcpr_clk = { | |
2350 | .halt_reg = 0x4084, | |
2351 | .clkr = { | |
2352 | .enable_reg = 0x4084, | |
2353 | .enable_mask = BIT(0), | |
2354 | .hw.init = &(struct clk_init_data){ | |
2355 | .name = "mmss_rbcpr_clk", | |
2356 | .parent_names = (const char *[]){ | |
2357 | "rbcpr_clk_src", | |
2358 | }, | |
2359 | .num_parents = 1, | |
2360 | .flags = CLK_SET_RATE_PARENT, | |
2361 | .ops = &clk_branch2_ops, | |
2362 | }, | |
2363 | }, | |
2364 | }; | |
2365 | ||
2366 | static struct clk_branch mmss_spdm_ahb_clk = { | |
2367 | .halt_reg = 0x0230, | |
2368 | .clkr = { | |
2369 | .enable_reg = 0x0230, | |
2370 | .enable_mask = BIT(0), | |
2371 | .hw.init = &(struct clk_init_data){ | |
2372 | .name = "mmss_spdm_ahb_clk", | |
2373 | .parent_names = (const char *[]){ | |
2374 | "mmss_spdm_ahb_div_clk", | |
2375 | }, | |
2376 | .num_parents = 1, | |
2377 | .flags = CLK_SET_RATE_PARENT, | |
2378 | .ops = &clk_branch2_ops, | |
2379 | }, | |
2380 | }, | |
2381 | }; | |
2382 | ||
2383 | static struct clk_branch mmss_spdm_axi_clk = { | |
2384 | .halt_reg = 0x0210, | |
2385 | .clkr = { | |
2386 | .enable_reg = 0x0210, | |
2387 | .enable_mask = BIT(0), | |
2388 | .hw.init = &(struct clk_init_data){ | |
2389 | .name = "mmss_spdm_axi_clk", | |
2390 | .parent_names = (const char *[]){ | |
2391 | "mmss_spdm_axi_div_clk", | |
2392 | }, | |
2393 | .num_parents = 1, | |
2394 | .flags = CLK_SET_RATE_PARENT, | |
2395 | .ops = &clk_branch2_ops, | |
2396 | }, | |
2397 | }, | |
2398 | }; | |
2399 | ||
2400 | static struct clk_branch mmss_spdm_csi0_clk = { | |
2401 | .halt_reg = 0x023c, | |
2402 | .clkr = { | |
2403 | .enable_reg = 0x023c, | |
2404 | .enable_mask = BIT(0), | |
2405 | .hw.init = &(struct clk_init_data){ | |
2406 | .name = "mmss_spdm_csi0_clk", | |
2407 | .parent_names = (const char *[]){ | |
2408 | "mmss_spdm_csi0_div_clk", | |
2409 | }, | |
2410 | .num_parents = 1, | |
2411 | .flags = CLK_SET_RATE_PARENT, | |
2412 | .ops = &clk_branch2_ops, | |
2413 | }, | |
2414 | }, | |
2415 | }; | |
2416 | ||
2417 | static struct clk_branch mmss_spdm_gfx3d_clk = { | |
2418 | .halt_reg = 0x022c, | |
2419 | .clkr = { | |
2420 | .enable_reg = 0x022c, | |
2421 | .enable_mask = BIT(0), | |
2422 | .hw.init = &(struct clk_init_data){ | |
2423 | .name = "mmss_spdm_gfx3d_clk", | |
2424 | .parent_names = (const char *[]){ | |
2425 | "mmss_spdm_gfx3d_div_clk", | |
2426 | }, | |
2427 | .num_parents = 1, | |
2428 | .flags = CLK_SET_RATE_PARENT, | |
2429 | .ops = &clk_branch2_ops, | |
2430 | }, | |
2431 | }, | |
2432 | }; | |
2433 | ||
2434 | static struct clk_branch mmss_spdm_jpeg0_clk = { | |
2435 | .halt_reg = 0x0204, | |
2436 | .clkr = { | |
2437 | .enable_reg = 0x0204, | |
2438 | .enable_mask = BIT(0), | |
2439 | .hw.init = &(struct clk_init_data){ | |
2440 | .name = "mmss_spdm_jpeg0_clk", | |
2441 | .parent_names = (const char *[]){ | |
2442 | "mmss_spdm_jpeg0_div_clk", | |
2443 | }, | |
2444 | .num_parents = 1, | |
2445 | .flags = CLK_SET_RATE_PARENT, | |
2446 | .ops = &clk_branch2_ops, | |
2447 | }, | |
2448 | }, | |
2449 | }; | |
2450 | ||
2451 | static struct clk_branch mmss_spdm_jpeg1_clk = { | |
2452 | .halt_reg = 0x0208, | |
2453 | .clkr = { | |
2454 | .enable_reg = 0x0208, | |
2455 | .enable_mask = BIT(0), | |
2456 | .hw.init = &(struct clk_init_data){ | |
2457 | .name = "mmss_spdm_jpeg1_clk", | |
2458 | .parent_names = (const char *[]){ | |
2459 | "mmss_spdm_jpeg1_div_clk", | |
2460 | }, | |
2461 | .num_parents = 1, | |
2462 | .flags = CLK_SET_RATE_PARENT, | |
2463 | .ops = &clk_branch2_ops, | |
2464 | }, | |
2465 | }, | |
2466 | }; | |
2467 | ||
2468 | static struct clk_branch mmss_spdm_jpeg2_clk = { | |
2469 | .halt_reg = 0x0224, | |
2470 | .clkr = { | |
2471 | .enable_reg = 0x0224, | |
2472 | .enable_mask = BIT(0), | |
2473 | .hw.init = &(struct clk_init_data){ | |
2474 | .name = "mmss_spdm_jpeg2_clk", | |
2475 | .parent_names = (const char *[]){ | |
2476 | "mmss_spdm_jpeg2_div_clk", | |
2477 | }, | |
2478 | .num_parents = 1, | |
2479 | .flags = CLK_SET_RATE_PARENT, | |
2480 | .ops = &clk_branch2_ops, | |
2481 | }, | |
2482 | }, | |
2483 | }; | |
2484 | ||
2485 | static struct clk_branch mmss_spdm_mdp_clk = { | |
2486 | .halt_reg = 0x020c, | |
2487 | .clkr = { | |
2488 | .enable_reg = 0x020c, | |
2489 | .enable_mask = BIT(0), | |
2490 | .hw.init = &(struct clk_init_data){ | |
2491 | .name = "mmss_spdm_mdp_clk", | |
2492 | .parent_names = (const char *[]){ | |
2493 | "mmss_spdm_mdp_div_clk", | |
2494 | }, | |
2495 | .num_parents = 1, | |
2496 | .flags = CLK_SET_RATE_PARENT, | |
2497 | .ops = &clk_branch2_ops, | |
2498 | }, | |
2499 | }, | |
2500 | }; | |
2501 | ||
2502 | static struct clk_branch mmss_spdm_pclk0_clk = { | |
2503 | .halt_reg = 0x0234, | |
2504 | .clkr = { | |
2505 | .enable_reg = 0x0234, | |
2506 | .enable_mask = BIT(0), | |
2507 | .hw.init = &(struct clk_init_data){ | |
2508 | .name = "mmss_spdm_pclk0_clk", | |
2509 | .parent_names = (const char *[]){ | |
2510 | "mmss_spdm_pclk0_div_clk", | |
2511 | }, | |
2512 | .num_parents = 1, | |
2513 | .flags = CLK_SET_RATE_PARENT, | |
2514 | .ops = &clk_branch2_ops, | |
2515 | }, | |
2516 | }, | |
2517 | }; | |
2518 | ||
2519 | static struct clk_branch mmss_spdm_pclk1_clk = { | |
2520 | .halt_reg = 0x0228, | |
2521 | .clkr = { | |
2522 | .enable_reg = 0x0228, | |
2523 | .enable_mask = BIT(0), | |
2524 | .hw.init = &(struct clk_init_data){ | |
2525 | .name = "mmss_spdm_pclk1_clk", | |
2526 | .parent_names = (const char *[]){ | |
2527 | "mmss_spdm_pclk1_div_clk", | |
2528 | }, | |
2529 | .num_parents = 1, | |
2530 | .flags = CLK_SET_RATE_PARENT, | |
2531 | .ops = &clk_branch2_ops, | |
2532 | }, | |
2533 | }, | |
2534 | }; | |
2535 | ||
2536 | static struct clk_branch mmss_spdm_vcodec0_clk = { | |
2537 | .halt_reg = 0x0214, | |
2538 | .clkr = { | |
2539 | .enable_reg = 0x0214, | |
2540 | .enable_mask = BIT(0), | |
2541 | .hw.init = &(struct clk_init_data){ | |
2542 | .name = "mmss_spdm_vcodec0_clk", | |
2543 | .parent_names = (const char *[]){ | |
2544 | "mmss_spdm_vcodec0_div_clk", | |
2545 | }, | |
2546 | .num_parents = 1, | |
2547 | .flags = CLK_SET_RATE_PARENT, | |
2548 | .ops = &clk_branch2_ops, | |
2549 | }, | |
2550 | }, | |
2551 | }; | |
2552 | ||
2553 | static struct clk_branch mmss_spdm_vfe0_clk = { | |
2554 | .halt_reg = 0x0218, | |
2555 | .clkr = { | |
2556 | .enable_reg = 0x0218, | |
2557 | .enable_mask = BIT(0), | |
2558 | .hw.init = &(struct clk_init_data){ | |
2559 | .name = "mmss_spdm_vfe0_clk", | |
2560 | .parent_names = (const char *[]){ | |
2561 | "mmss_spdm_vfe0_div_clk", | |
2562 | }, | |
2563 | .num_parents = 1, | |
2564 | .flags = CLK_SET_RATE_PARENT, | |
2565 | .ops = &clk_branch2_ops, | |
2566 | }, | |
2567 | }, | |
2568 | }; | |
2569 | ||
2570 | static struct clk_branch mmss_spdm_vfe1_clk = { | |
2571 | .halt_reg = 0x021c, | |
2572 | .clkr = { | |
2573 | .enable_reg = 0x021c, | |
2574 | .enable_mask = BIT(0), | |
2575 | .hw.init = &(struct clk_init_data){ | |
2576 | .name = "mmss_spdm_vfe1_clk", | |
2577 | .parent_names = (const char *[]){ | |
2578 | "mmss_spdm_vfe1_div_clk", | |
2579 | }, | |
2580 | .num_parents = 1, | |
2581 | .flags = CLK_SET_RATE_PARENT, | |
2582 | .ops = &clk_branch2_ops, | |
2583 | }, | |
2584 | }, | |
2585 | }; | |
2586 | ||
2587 | static struct clk_branch mmss_spdm_rm_axi_clk = { | |
2588 | .halt_reg = 0x0304, | |
2589 | .clkr = { | |
2590 | .enable_reg = 0x0304, | |
2591 | .enable_mask = BIT(0), | |
2592 | .hw.init = &(struct clk_init_data){ | |
2593 | .name = "mmss_spdm_rm_axi_clk", | |
2594 | .parent_names = (const char *[]){ | |
2595 | "mmss_axi_clk_src", | |
2596 | }, | |
2597 | .num_parents = 1, | |
2598 | .flags = CLK_SET_RATE_PARENT, | |
2599 | .ops = &clk_branch2_ops, | |
2600 | }, | |
2601 | }, | |
2602 | }; | |
2603 | ||
2604 | static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = { | |
2605 | .halt_reg = 0x0308, | |
2606 | .clkr = { | |
2607 | .enable_reg = 0x0308, | |
2608 | .enable_mask = BIT(0), | |
2609 | .hw.init = &(struct clk_init_data){ | |
2610 | .name = "mmss_spdm_rm_ocmemnoc_clk", | |
2611 | .parent_names = (const char *[]){ | |
2612 | "ocmemnoc_clk_src", | |
2613 | }, | |
2614 | .num_parents = 1, | |
2615 | .flags = CLK_SET_RATE_PARENT, | |
2616 | .ops = &clk_branch2_ops, | |
2617 | }, | |
2618 | }, | |
2619 | }; | |
2620 | ||
2621 | ||
2622 | static struct clk_branch mmss_misc_ahb_clk = { | |
2623 | .halt_reg = 0x502c, | |
2624 | .clkr = { | |
2625 | .enable_reg = 0x502c, | |
2626 | .enable_mask = BIT(0), | |
2627 | .hw.init = &(struct clk_init_data){ | |
2628 | .name = "mmss_misc_ahb_clk", | |
2629 | .parent_names = (const char *[]){ | |
2630 | "mmss_ahb_clk_src", | |
2631 | }, | |
2632 | .num_parents = 1, | |
2633 | .flags = CLK_SET_RATE_PARENT, | |
2634 | .ops = &clk_branch2_ops, | |
2635 | }, | |
2636 | }, | |
2637 | }; | |
2638 | ||
2639 | static struct clk_branch mmss_mmssnoc_ahb_clk = { | |
2640 | .halt_reg = 0x5024, | |
2641 | .clkr = { | |
2642 | .enable_reg = 0x5024, | |
2643 | .enable_mask = BIT(0), | |
2644 | .hw.init = &(struct clk_init_data){ | |
2645 | .name = "mmss_mmssnoc_ahb_clk", | |
2646 | .parent_names = (const char *[]){ | |
2647 | "mmss_ahb_clk_src", | |
2648 | }, | |
2649 | .num_parents = 1, | |
2650 | .ops = &clk_branch2_ops, | |
2651 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2652 | }, | |
2653 | }, | |
2654 | }; | |
2655 | ||
2656 | static struct clk_branch mmss_mmssnoc_bto_ahb_clk = { | |
2657 | .halt_reg = 0x5028, | |
2658 | .clkr = { | |
2659 | .enable_reg = 0x5028, | |
2660 | .enable_mask = BIT(0), | |
2661 | .hw.init = &(struct clk_init_data){ | |
2662 | .name = "mmss_mmssnoc_bto_ahb_clk", | |
2663 | .parent_names = (const char *[]){ | |
2664 | "mmss_ahb_clk_src", | |
2665 | }, | |
2666 | .num_parents = 1, | |
2667 | .ops = &clk_branch2_ops, | |
2668 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2669 | }, | |
2670 | }, | |
2671 | }; | |
2672 | ||
2673 | static struct clk_branch mmss_mmssnoc_axi_clk = { | |
2674 | .halt_reg = 0x506c, | |
2675 | .clkr = { | |
2676 | .enable_reg = 0x506c, | |
2677 | .enable_mask = BIT(0), | |
2678 | .hw.init = &(struct clk_init_data){ | |
2679 | .name = "mmss_mmssnoc_axi_clk", | |
2680 | .parent_names = (const char *[]){ | |
2681 | "mmss_axi_clk_src", | |
2682 | }, | |
2683 | .num_parents = 1, | |
2684 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2685 | .ops = &clk_branch2_ops, | |
2686 | }, | |
2687 | }, | |
2688 | }; | |
2689 | ||
2690 | static struct clk_branch mmss_s0_axi_clk = { | |
2691 | .halt_reg = 0x5064, | |
2692 | .clkr = { | |
2693 | .enable_reg = 0x5064, | |
2694 | .enable_mask = BIT(0), | |
2695 | .hw.init = &(struct clk_init_data){ | |
2696 | .name = "mmss_s0_axi_clk", | |
2697 | .parent_names = (const char *[]){ | |
2698 | "mmss_axi_clk_src", | |
2699 | }, | |
2700 | .num_parents = 1, | |
2701 | .ops = &clk_branch2_ops, | |
2702 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2703 | }, | |
2704 | }, | |
2705 | }; | |
2706 | ||
2707 | static struct clk_branch ocmemcx_ahb_clk = { | |
2708 | .halt_reg = 0x405c, | |
2709 | .clkr = { | |
2710 | .enable_reg = 0x405c, | |
2711 | .enable_mask = BIT(0), | |
2712 | .hw.init = &(struct clk_init_data){ | |
2713 | .name = "ocmemcx_ahb_clk", | |
2714 | .parent_names = (const char *[]){ | |
2715 | "mmss_ahb_clk_src", | |
2716 | }, | |
2717 | .num_parents = 1, | |
2718 | .flags = CLK_SET_RATE_PARENT, | |
2719 | .ops = &clk_branch2_ops, | |
2720 | }, | |
2721 | }, | |
2722 | }; | |
2723 | ||
2724 | static struct clk_branch ocmemcx_ocmemnoc_clk = { | |
2725 | .halt_reg = 0x4058, | |
2726 | .clkr = { | |
2727 | .enable_reg = 0x4058, | |
2728 | .enable_mask = BIT(0), | |
2729 | .hw.init = &(struct clk_init_data){ | |
2730 | .name = "ocmemcx_ocmemnoc_clk", | |
2731 | .parent_names = (const char *[]){ | |
2732 | "ocmemnoc_clk_src", | |
2733 | }, | |
2734 | .num_parents = 1, | |
2735 | .flags = CLK_SET_RATE_PARENT, | |
2736 | .ops = &clk_branch2_ops, | |
2737 | }, | |
2738 | }, | |
2739 | }; | |
2740 | ||
2741 | static struct clk_branch oxili_ocmemgx_clk = { | |
2742 | .halt_reg = 0x402c, | |
2743 | .clkr = { | |
2744 | .enable_reg = 0x402c, | |
2745 | .enable_mask = BIT(0), | |
2746 | .hw.init = &(struct clk_init_data){ | |
2747 | .name = "oxili_ocmemgx_clk", | |
2748 | .parent_names = (const char *[]){ | |
2749 | "gfx3d_clk_src", | |
2750 | }, | |
2751 | .num_parents = 1, | |
2752 | .flags = CLK_SET_RATE_PARENT, | |
2753 | .ops = &clk_branch2_ops, | |
2754 | }, | |
2755 | }, | |
2756 | }; | |
2757 | ||
2758 | static struct clk_branch oxili_gfx3d_clk = { | |
2759 | .halt_reg = 0x4028, | |
2760 | .clkr = { | |
2761 | .enable_reg = 0x4028, | |
2762 | .enable_mask = BIT(0), | |
2763 | .hw.init = &(struct clk_init_data){ | |
2764 | .name = "oxili_gfx3d_clk", | |
2765 | .parent_names = (const char *[]){ | |
2766 | "gfx3d_clk_src", | |
2767 | }, | |
2768 | .num_parents = 1, | |
2769 | .flags = CLK_SET_RATE_PARENT, | |
2770 | .ops = &clk_branch2_ops, | |
2771 | }, | |
2772 | }, | |
2773 | }; | |
2774 | ||
2775 | static struct clk_branch oxili_rbbmtimer_clk = { | |
2776 | .halt_reg = 0x40b0, | |
2777 | .clkr = { | |
2778 | .enable_reg = 0x40b0, | |
2779 | .enable_mask = BIT(0), | |
2780 | .hw.init = &(struct clk_init_data){ | |
2781 | .name = "oxili_rbbmtimer_clk", | |
2782 | .parent_names = (const char *[]){ | |
2783 | "rbbmtimer_clk_src", | |
2784 | }, | |
2785 | .num_parents = 1, | |
2786 | .flags = CLK_SET_RATE_PARENT, | |
2787 | .ops = &clk_branch2_ops, | |
2788 | }, | |
2789 | }, | |
2790 | }; | |
2791 | ||
2792 | static struct clk_branch oxilicx_ahb_clk = { | |
2793 | .halt_reg = 0x403c, | |
2794 | .clkr = { | |
2795 | .enable_reg = 0x403c, | |
2796 | .enable_mask = BIT(0), | |
2797 | .hw.init = &(struct clk_init_data){ | |
2798 | .name = "oxilicx_ahb_clk", | |
2799 | .parent_names = (const char *[]){ | |
2800 | "mmss_ahb_clk_src", | |
2801 | }, | |
2802 | .num_parents = 1, | |
2803 | .flags = CLK_SET_RATE_PARENT, | |
2804 | .ops = &clk_branch2_ops, | |
2805 | }, | |
2806 | }, | |
2807 | }; | |
2808 | ||
2809 | static struct clk_branch venus0_ahb_clk = { | |
2810 | .halt_reg = 0x1030, | |
2811 | .clkr = { | |
2812 | .enable_reg = 0x1030, | |
2813 | .enable_mask = BIT(0), | |
2814 | .hw.init = &(struct clk_init_data){ | |
2815 | .name = "venus0_ahb_clk", | |
2816 | .parent_names = (const char *[]){ | |
2817 | "mmss_ahb_clk_src", | |
2818 | }, | |
2819 | .num_parents = 1, | |
2820 | .flags = CLK_SET_RATE_PARENT, | |
2821 | .ops = &clk_branch2_ops, | |
2822 | }, | |
2823 | }, | |
2824 | }; | |
2825 | ||
2826 | static struct clk_branch venus0_axi_clk = { | |
2827 | .halt_reg = 0x1034, | |
2828 | .clkr = { | |
2829 | .enable_reg = 0x1034, | |
2830 | .enable_mask = BIT(0), | |
2831 | .hw.init = &(struct clk_init_data){ | |
2832 | .name = "venus0_axi_clk", | |
2833 | .parent_names = (const char *[]){ | |
2834 | "mmss_axi_clk_src", | |
2835 | }, | |
2836 | .num_parents = 1, | |
2837 | .flags = CLK_SET_RATE_PARENT, | |
2838 | .ops = &clk_branch2_ops, | |
2839 | }, | |
2840 | }, | |
2841 | }; | |
2842 | ||
2843 | static struct clk_branch venus0_core0_vcodec_clk = { | |
2844 | .halt_reg = 0x1048, | |
2845 | .clkr = { | |
2846 | .enable_reg = 0x1048, | |
2847 | .enable_mask = BIT(0), | |
2848 | .hw.init = &(struct clk_init_data){ | |
2849 | .name = "venus0_core0_vcodec_clk", | |
2850 | .parent_names = (const char *[]){ | |
2851 | "vcodec0_clk_src", | |
2852 | }, | |
2853 | .num_parents = 1, | |
2854 | .flags = CLK_SET_RATE_PARENT, | |
2855 | .ops = &clk_branch2_ops, | |
2856 | }, | |
2857 | }, | |
2858 | }; | |
2859 | ||
2860 | static struct clk_branch venus0_core1_vcodec_clk = { | |
2861 | .halt_reg = 0x104c, | |
2862 | .clkr = { | |
2863 | .enable_reg = 0x104c, | |
2864 | .enable_mask = BIT(0), | |
2865 | .hw.init = &(struct clk_init_data){ | |
2866 | .name = "venus0_core1_vcodec_clk", | |
2867 | .parent_names = (const char *[]){ | |
2868 | "vcodec0_clk_src", | |
2869 | }, | |
2870 | .num_parents = 1, | |
2871 | .flags = CLK_SET_RATE_PARENT, | |
2872 | .ops = &clk_branch2_ops, | |
2873 | }, | |
2874 | }, | |
2875 | }; | |
2876 | ||
2877 | static struct clk_branch venus0_ocmemnoc_clk = { | |
2878 | .halt_reg = 0x1038, | |
2879 | .clkr = { | |
2880 | .enable_reg = 0x1038, | |
2881 | .enable_mask = BIT(0), | |
2882 | .hw.init = &(struct clk_init_data){ | |
2883 | .name = "venus0_ocmemnoc_clk", | |
2884 | .parent_names = (const char *[]){ | |
2885 | "ocmemnoc_clk_src", | |
2886 | }, | |
2887 | .num_parents = 1, | |
2888 | .flags = CLK_SET_RATE_PARENT, | |
2889 | .ops = &clk_branch2_ops, | |
2890 | }, | |
2891 | }, | |
2892 | }; | |
2893 | ||
2894 | static struct clk_branch venus0_vcodec0_clk = { | |
2895 | .halt_reg = 0x1028, | |
2896 | .clkr = { | |
2897 | .enable_reg = 0x1028, | |
2898 | .enable_mask = BIT(0), | |
2899 | .hw.init = &(struct clk_init_data){ | |
2900 | .name = "venus0_vcodec0_clk", | |
2901 | .parent_names = (const char *[]){ | |
2902 | "vcodec0_clk_src", | |
2903 | }, | |
2904 | .num_parents = 1, | |
2905 | .flags = CLK_SET_RATE_PARENT, | |
2906 | .ops = &clk_branch2_ops, | |
2907 | }, | |
2908 | }, | |
2909 | }; | |
2910 | ||
2911 | static struct clk_branch vpu_ahb_clk = { | |
2912 | .halt_reg = 0x1430, | |
2913 | .clkr = { | |
2914 | .enable_reg = 0x1430, | |
2915 | .enable_mask = BIT(0), | |
2916 | .hw.init = &(struct clk_init_data){ | |
2917 | .name = "vpu_ahb_clk", | |
2918 | .parent_names = (const char *[]){ | |
2919 | "mmss_ahb_clk_src", | |
2920 | }, | |
2921 | .num_parents = 1, | |
2922 | .flags = CLK_SET_RATE_PARENT, | |
2923 | .ops = &clk_branch2_ops, | |
2924 | }, | |
2925 | }, | |
2926 | }; | |
2927 | ||
2928 | static struct clk_branch vpu_axi_clk = { | |
2929 | .halt_reg = 0x143c, | |
2930 | .clkr = { | |
2931 | .enable_reg = 0x143c, | |
2932 | .enable_mask = BIT(0), | |
2933 | .hw.init = &(struct clk_init_data){ | |
2934 | .name = "vpu_axi_clk", | |
2935 | .parent_names = (const char *[]){ | |
2936 | "mmss_axi_clk_src", | |
2937 | }, | |
2938 | .num_parents = 1, | |
2939 | .flags = CLK_SET_RATE_PARENT, | |
2940 | .ops = &clk_branch2_ops, | |
2941 | }, | |
2942 | }, | |
2943 | }; | |
2944 | ||
2945 | static struct clk_branch vpu_bus_clk = { | |
2946 | .halt_reg = 0x1440, | |
2947 | .clkr = { | |
2948 | .enable_reg = 0x1440, | |
2949 | .enable_mask = BIT(0), | |
2950 | .hw.init = &(struct clk_init_data){ | |
2951 | .name = "vpu_bus_clk", | |
2952 | .parent_names = (const char *[]){ | |
2953 | "vpu_bus_clk_src", | |
2954 | }, | |
2955 | .num_parents = 1, | |
2956 | .flags = CLK_SET_RATE_PARENT, | |
2957 | .ops = &clk_branch2_ops, | |
2958 | }, | |
2959 | }, | |
2960 | }; | |
2961 | ||
2962 | static struct clk_branch vpu_cxo_clk = { | |
2963 | .halt_reg = 0x1434, | |
2964 | .clkr = { | |
2965 | .enable_reg = 0x1434, | |
2966 | .enable_mask = BIT(0), | |
2967 | .hw.init = &(struct clk_init_data){ | |
2968 | .name = "vpu_cxo_clk", | |
2969 | .parent_names = (const char *[]){ "xo" }, | |
2970 | .num_parents = 1, | |
2971 | .flags = CLK_SET_RATE_PARENT, | |
2972 | .ops = &clk_branch2_ops, | |
2973 | }, | |
2974 | }, | |
2975 | }; | |
2976 | ||
2977 | static struct clk_branch vpu_maple_clk = { | |
2978 | .halt_reg = 0x142c, | |
2979 | .clkr = { | |
2980 | .enable_reg = 0x142c, | |
2981 | .enable_mask = BIT(0), | |
2982 | .hw.init = &(struct clk_init_data){ | |
2983 | .name = "vpu_maple_clk", | |
2984 | .parent_names = (const char *[]){ | |
2985 | "maple_clk_src", | |
2986 | }, | |
2987 | .num_parents = 1, | |
2988 | .flags = CLK_SET_RATE_PARENT, | |
2989 | .ops = &clk_branch2_ops, | |
2990 | }, | |
2991 | }, | |
2992 | }; | |
2993 | ||
2994 | static struct clk_branch vpu_sleep_clk = { | |
2995 | .halt_reg = 0x1438, | |
2996 | .clkr = { | |
2997 | .enable_reg = 0x1438, | |
2998 | .enable_mask = BIT(0), | |
2999 | .hw.init = &(struct clk_init_data){ | |
3000 | .name = "vpu_sleep_clk", | |
3001 | .parent_names = (const char *[]){ | |
3002 | "sleep_clk_src", | |
3003 | }, | |
3004 | .num_parents = 1, | |
3005 | .flags = CLK_SET_RATE_PARENT, | |
3006 | .ops = &clk_branch2_ops, | |
3007 | }, | |
3008 | }, | |
3009 | }; | |
3010 | ||
3011 | static struct clk_branch vpu_vdp_clk = { | |
3012 | .halt_reg = 0x1428, | |
3013 | .clkr = { | |
3014 | .enable_reg = 0x1428, | |
3015 | .enable_mask = BIT(0), | |
3016 | .hw.init = &(struct clk_init_data){ | |
3017 | .name = "vpu_vdp_clk", | |
3018 | .parent_names = (const char *[]){ | |
3019 | "vdp_clk_src", | |
3020 | }, | |
3021 | .num_parents = 1, | |
3022 | .flags = CLK_SET_RATE_PARENT, | |
3023 | .ops = &clk_branch2_ops, | |
3024 | }, | |
3025 | }, | |
3026 | }; | |
3027 | ||
3028 | static const struct pll_config mmpll1_config = { | |
3029 | .l = 60, | |
3030 | .m = 25, | |
3031 | .n = 32, | |
3032 | .vco_val = 0x0, | |
3033 | .vco_mask = 0x3 << 20, | |
3034 | .pre_div_val = 0x0, | |
3035 | .pre_div_mask = 0x7 << 12, | |
3036 | .post_div_val = 0x0, | |
3037 | .post_div_mask = 0x3 << 8, | |
3038 | .mn_ena_mask = BIT(24), | |
3039 | .main_output_mask = BIT(0), | |
3040 | }; | |
3041 | ||
3042 | static const struct pll_config mmpll3_config = { | |
3043 | .l = 48, | |
3044 | .m = 7, | |
3045 | .n = 16, | |
3046 | .vco_val = 0x0, | |
3047 | .vco_mask = 0x3 << 20, | |
3048 | .pre_div_val = 0x0, | |
3049 | .pre_div_mask = 0x7 << 12, | |
3050 | .post_div_val = 0x0, | |
3051 | .post_div_mask = 0x3 << 8, | |
3052 | .mn_ena_mask = BIT(24), | |
3053 | .main_output_mask = BIT(0), | |
3054 | .aux_output_mask = BIT(1), | |
3055 | }; | |
3056 | ||
cb2eb7de SV |
3057 | static struct gdsc venus0_gdsc = { |
3058 | .gdscr = 0x1024, | |
3059 | .pd = { | |
3060 | .name = "venus0", | |
3061 | }, | |
3062 | .pwrsts = PWRSTS_OFF_ON, | |
3063 | }; | |
3064 | ||
3065 | static struct gdsc venus0_core0_gdsc = { | |
3066 | .gdscr = 0x1040, | |
3067 | .pd = { | |
3068 | .name = "venus0_core0", | |
3069 | }, | |
3070 | .pwrsts = PWRSTS_OFF_ON, | |
3071 | }; | |
3072 | ||
3073 | static struct gdsc venus0_core1_gdsc = { | |
3074 | .gdscr = 0x1044, | |
3075 | .pd = { | |
3076 | .name = "venus0_core1", | |
3077 | }, | |
3078 | .pwrsts = PWRSTS_OFF_ON, | |
3079 | }; | |
3080 | ||
3081 | static struct gdsc mdss_gdsc = { | |
3082 | .gdscr = 0x2304, | |
3083 | .cxcs = (unsigned int []){ 0x231c, 0x2320 }, | |
3084 | .cxc_count = 2, | |
3085 | .pd = { | |
3086 | .name = "mdss", | |
3087 | }, | |
3088 | .pwrsts = PWRSTS_OFF_ON, | |
3089 | }; | |
3090 | ||
3091 | static struct gdsc camss_jpeg_gdsc = { | |
3092 | .gdscr = 0x35a4, | |
3093 | .pd = { | |
3094 | .name = "camss_jpeg", | |
3095 | }, | |
3096 | .pwrsts = PWRSTS_OFF_ON, | |
3097 | }; | |
3098 | ||
3099 | static struct gdsc camss_vfe_gdsc = { | |
3100 | .gdscr = 0x36a4, | |
3101 | .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 }, | |
3102 | .cxc_count = 3, | |
3103 | .pd = { | |
3104 | .name = "camss_vfe", | |
3105 | }, | |
3106 | .pwrsts = PWRSTS_OFF_ON, | |
3107 | }; | |
3108 | ||
3109 | static struct gdsc oxili_gdsc = { | |
3110 | .gdscr = 0x4024, | |
3111 | .cxcs = (unsigned int []){ 0x4028 }, | |
3112 | .cxc_count = 1, | |
3113 | .pd = { | |
3114 | .name = "oxili", | |
3115 | }, | |
3116 | .pwrsts = PWRSTS_OFF_ON, | |
3117 | }; | |
3118 | ||
3119 | static struct gdsc oxilicx_gdsc = { | |
3120 | .gdscr = 0x4034, | |
3121 | .pd = { | |
3122 | .name = "oxilicx", | |
3123 | }, | |
3124 | .pwrsts = PWRSTS_OFF_ON, | |
3125 | }; | |
3126 | ||
2b46cd23 GD |
3127 | static struct clk_regmap *mmcc_apq8084_clocks[] = { |
3128 | [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr, | |
3129 | [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr, | |
3130 | [MMPLL0] = &mmpll0.clkr, | |
3131 | [MMPLL0_VOTE] = &mmpll0_vote, | |
3132 | [MMPLL1] = &mmpll1.clkr, | |
3133 | [MMPLL1_VOTE] = &mmpll1_vote, | |
3134 | [MMPLL2] = &mmpll2.clkr, | |
3135 | [MMPLL3] = &mmpll3.clkr, | |
3136 | [MMPLL4] = &mmpll4.clkr, | |
3137 | [CSI0_CLK_SRC] = &csi0_clk_src.clkr, | |
3138 | [CSI1_CLK_SRC] = &csi1_clk_src.clkr, | |
3139 | [CSI2_CLK_SRC] = &csi2_clk_src.clkr, | |
3140 | [CSI3_CLK_SRC] = &csi3_clk_src.clkr, | |
3141 | [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr, | |
3142 | [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, | |
3143 | [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, | |
3144 | [MDP_CLK_SRC] = &mdp_clk_src.clkr, | |
3145 | [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, | |
3146 | [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, | |
3147 | [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr, | |
3148 | [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, | |
3149 | [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, | |
3150 | [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr, | |
3151 | [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr, | |
3152 | [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr, | |
3153 | [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr, | |
3154 | [VP_CLK_SRC] = &vp_clk_src.clkr, | |
3155 | [CCI_CLK_SRC] = &cci_clk_src.clkr, | |
3156 | [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, | |
3157 | [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, | |
3158 | [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, | |
3159 | [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, | |
3160 | [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, | |
3161 | [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, | |
3162 | [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, | |
3163 | [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, | |
3164 | [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, | |
3165 | [CPP_CLK_SRC] = &cpp_clk_src.clkr, | |
3166 | [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, | |
3167 | [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, | |
3168 | [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr, | |
3169 | [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr, | |
3170 | [ESC0_CLK_SRC] = &esc0_clk_src.clkr, | |
3171 | [ESC1_CLK_SRC] = &esc1_clk_src.clkr, | |
3172 | [HDMI_CLK_SRC] = &hdmi_clk_src.clkr, | |
3173 | [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, | |
9a6cb70f | 3174 | [MMSS_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, |
2b46cd23 GD |
3175 | [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, |
3176 | [MAPLE_CLK_SRC] = &maple_clk_src.clkr, | |
3177 | [VDP_CLK_SRC] = &vdp_clk_src.clkr, | |
3178 | [VPU_BUS_CLK_SRC] = &vpu_bus_clk_src.clkr, | |
3179 | [MMSS_CXO_CLK] = &mmss_cxo_clk.clkr, | |
3180 | [MMSS_SLEEPCLK_CLK] = &mmss_sleepclk_clk.clkr, | |
3181 | [AVSYNC_AHB_CLK] = &avsync_ahb_clk.clkr, | |
3182 | [AVSYNC_EDPPIXEL_CLK] = &avsync_edppixel_clk.clkr, | |
3183 | [AVSYNC_EXTPCLK_CLK] = &avsync_extpclk_clk.clkr, | |
3184 | [AVSYNC_PCLK0_CLK] = &avsync_pclk0_clk.clkr, | |
3185 | [AVSYNC_PCLK1_CLK] = &avsync_pclk1_clk.clkr, | |
3186 | [AVSYNC_VP_CLK] = &avsync_vp_clk.clkr, | |
3187 | [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr, | |
3188 | [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr, | |
3189 | [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr, | |
3190 | [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr, | |
3191 | [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr, | |
3192 | [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr, | |
3193 | [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr, | |
3194 | [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr, | |
3195 | [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr, | |
3196 | [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr, | |
3197 | [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr, | |
3198 | [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr, | |
3199 | [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr, | |
3200 | [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr, | |
3201 | [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr, | |
3202 | [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr, | |
3203 | [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr, | |
3204 | [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr, | |
3205 | [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr, | |
3206 | [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr, | |
3207 | [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr, | |
3208 | [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr, | |
3209 | [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr, | |
3210 | [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr, | |
3211 | [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr, | |
3212 | [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr, | |
3213 | [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr, | |
3214 | [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr, | |
3215 | [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr, | |
3216 | [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr, | |
3217 | [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr, | |
3218 | [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr, | |
3219 | [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr, | |
3220 | [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr, | |
3221 | [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr, | |
3222 | [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr, | |
3223 | [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr, | |
3224 | [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr, | |
3225 | [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr, | |
3226 | [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr, | |
3227 | [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr, | |
3228 | [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr, | |
3229 | [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr, | |
3230 | [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr, | |
3231 | [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr, | |
3232 | [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr, | |
3233 | [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr, | |
3234 | [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr, | |
3235 | [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr, | |
3236 | [MDSS_AXI_CLK] = &mdss_axi_clk.clkr, | |
3237 | [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr, | |
3238 | [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr, | |
3239 | [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr, | |
3240 | [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr, | |
3241 | [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr, | |
3242 | [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr, | |
3243 | [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr, | |
3244 | [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr, | |
3245 | [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr, | |
3246 | [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr, | |
3247 | [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr, | |
3248 | [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr, | |
3249 | [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr, | |
3250 | [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr, | |
3251 | [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr, | |
3252 | [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr, | |
3253 | [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr, | |
3254 | [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr, | |
3255 | [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr, | |
3256 | [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr, | |
3257 | [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr, | |
3258 | [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr, | |
3259 | [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr, | |
3260 | [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr, | |
3261 | [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr, | |
3262 | [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr, | |
3263 | [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr, | |
3264 | [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr, | |
3265 | [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr, | |
3266 | [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr, | |
3267 | [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr, | |
3268 | [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr, | |
3269 | [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, | |
3270 | [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr, | |
3271 | [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr, | |
3272 | [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr, | |
3273 | [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr, | |
3274 | [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr, | |
3275 | [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr, | |
3276 | [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr, | |
3277 | [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr, | |
3278 | [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr, | |
3279 | [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr, | |
3280 | [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr, | |
3281 | [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr, | |
3282 | [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr, | |
3283 | [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr, | |
3284 | [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr, | |
3285 | [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr, | |
3286 | [VPU_AHB_CLK] = &vpu_ahb_clk.clkr, | |
3287 | [VPU_AXI_CLK] = &vpu_axi_clk.clkr, | |
3288 | [VPU_BUS_CLK] = &vpu_bus_clk.clkr, | |
3289 | [VPU_CXO_CLK] = &vpu_cxo_clk.clkr, | |
3290 | [VPU_MAPLE_CLK] = &vpu_maple_clk.clkr, | |
3291 | [VPU_SLEEP_CLK] = &vpu_sleep_clk.clkr, | |
3292 | [VPU_VDP_CLK] = &vpu_vdp_clk.clkr, | |
3293 | }; | |
3294 | ||
3295 | static const struct qcom_reset_map mmcc_apq8084_resets[] = { | |
3296 | [MMSS_SPDM_RESET] = { 0x0200 }, | |
3297 | [MMSS_SPDM_RM_RESET] = { 0x0300 }, | |
3298 | [VENUS0_RESET] = { 0x1020 }, | |
3299 | [VPU_RESET] = { 0x1400 }, | |
3300 | [MDSS_RESET] = { 0x2300 }, | |
3301 | [AVSYNC_RESET] = { 0x2400 }, | |
3302 | [CAMSS_PHY0_RESET] = { 0x3020 }, | |
3303 | [CAMSS_PHY1_RESET] = { 0x3050 }, | |
3304 | [CAMSS_PHY2_RESET] = { 0x3080 }, | |
3305 | [CAMSS_CSI0_RESET] = { 0x30b0 }, | |
3306 | [CAMSS_CSI0PHY_RESET] = { 0x30c0 }, | |
3307 | [CAMSS_CSI0RDI_RESET] = { 0x30d0 }, | |
3308 | [CAMSS_CSI0PIX_RESET] = { 0x30e0 }, | |
3309 | [CAMSS_CSI1_RESET] = { 0x3120 }, | |
3310 | [CAMSS_CSI1PHY_RESET] = { 0x3130 }, | |
3311 | [CAMSS_CSI1RDI_RESET] = { 0x3140 }, | |
3312 | [CAMSS_CSI1PIX_RESET] = { 0x3150 }, | |
3313 | [CAMSS_CSI2_RESET] = { 0x3180 }, | |
3314 | [CAMSS_CSI2PHY_RESET] = { 0x3190 }, | |
3315 | [CAMSS_CSI2RDI_RESET] = { 0x31a0 }, | |
3316 | [CAMSS_CSI2PIX_RESET] = { 0x31b0 }, | |
3317 | [CAMSS_CSI3_RESET] = { 0x31e0 }, | |
3318 | [CAMSS_CSI3PHY_RESET] = { 0x31f0 }, | |
3319 | [CAMSS_CSI3RDI_RESET] = { 0x3200 }, | |
3320 | [CAMSS_CSI3PIX_RESET] = { 0x3210 }, | |
3321 | [CAMSS_ISPIF_RESET] = { 0x3220 }, | |
3322 | [CAMSS_CCI_RESET] = { 0x3340 }, | |
3323 | [CAMSS_MCLK0_RESET] = { 0x3380 }, | |
3324 | [CAMSS_MCLK1_RESET] = { 0x33b0 }, | |
3325 | [CAMSS_MCLK2_RESET] = { 0x33e0 }, | |
3326 | [CAMSS_MCLK3_RESET] = { 0x3410 }, | |
3327 | [CAMSS_GP0_RESET] = { 0x3440 }, | |
3328 | [CAMSS_GP1_RESET] = { 0x3470 }, | |
3329 | [CAMSS_TOP_RESET] = { 0x3480 }, | |
3330 | [CAMSS_AHB_RESET] = { 0x3488 }, | |
3331 | [CAMSS_MICRO_RESET] = { 0x3490 }, | |
3332 | [CAMSS_JPEG_RESET] = { 0x35a0 }, | |
3333 | [CAMSS_VFE_RESET] = { 0x36a0 }, | |
3334 | [CAMSS_CSI_VFE0_RESET] = { 0x3700 }, | |
3335 | [CAMSS_CSI_VFE1_RESET] = { 0x3710 }, | |
3336 | [OXILI_RESET] = { 0x4020 }, | |
3337 | [OXILICX_RESET] = { 0x4030 }, | |
3338 | [OCMEMCX_RESET] = { 0x4050 }, | |
3339 | [MMSS_RBCRP_RESET] = { 0x4080 }, | |
3340 | [MMSSNOCAHB_RESET] = { 0x5020 }, | |
3341 | [MMSSNOCAXI_RESET] = { 0x5060 }, | |
3342 | }; | |
3343 | ||
cb2eb7de SV |
3344 | static struct gdsc *mmcc_apq8084_gdscs[] = { |
3345 | [VENUS0_GDSC] = &venus0_gdsc, | |
3346 | [VENUS0_CORE0_GDSC] = &venus0_core0_gdsc, | |
3347 | [VENUS0_CORE1_GDSC] = &venus0_core1_gdsc, | |
3348 | [MDSS_GDSC] = &mdss_gdsc, | |
3349 | [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc, | |
3350 | [CAMSS_VFE_GDSC] = &camss_vfe_gdsc, | |
3351 | [OXILI_GDSC] = &oxili_gdsc, | |
3352 | [OXILICX_GDSC] = &oxilicx_gdsc, | |
3353 | }; | |
3354 | ||
2b46cd23 GD |
3355 | static const struct regmap_config mmcc_apq8084_regmap_config = { |
3356 | .reg_bits = 32, | |
3357 | .reg_stride = 4, | |
3358 | .val_bits = 32, | |
3359 | .max_register = 0x5104, | |
3360 | .fast_io = true, | |
3361 | }; | |
3362 | ||
3363 | static const struct qcom_cc_desc mmcc_apq8084_desc = { | |
3364 | .config = &mmcc_apq8084_regmap_config, | |
3365 | .clks = mmcc_apq8084_clocks, | |
3366 | .num_clks = ARRAY_SIZE(mmcc_apq8084_clocks), | |
3367 | .resets = mmcc_apq8084_resets, | |
3368 | .num_resets = ARRAY_SIZE(mmcc_apq8084_resets), | |
cb2eb7de SV |
3369 | .gdscs = mmcc_apq8084_gdscs, |
3370 | .num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs), | |
2b46cd23 GD |
3371 | }; |
3372 | ||
3373 | static const struct of_device_id mmcc_apq8084_match_table[] = { | |
3374 | { .compatible = "qcom,mmcc-apq8084" }, | |
3375 | { } | |
3376 | }; | |
3377 | MODULE_DEVICE_TABLE(of, mmcc_apq8084_match_table); | |
3378 | ||
3379 | static int mmcc_apq8084_probe(struct platform_device *pdev) | |
3380 | { | |
3381 | int ret; | |
3382 | struct regmap *regmap; | |
3383 | ||
3384 | ret = qcom_cc_probe(pdev, &mmcc_apq8084_desc); | |
3385 | if (ret) | |
3386 | return ret; | |
3387 | ||
3388 | regmap = dev_get_regmap(&pdev->dev, NULL); | |
3389 | clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true); | |
3390 | clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false); | |
3391 | ||
3392 | return 0; | |
3393 | } | |
3394 | ||
2b46cd23 GD |
3395 | static struct platform_driver mmcc_apq8084_driver = { |
3396 | .probe = mmcc_apq8084_probe, | |
2b46cd23 GD |
3397 | .driver = { |
3398 | .name = "mmcc-apq8084", | |
2b46cd23 GD |
3399 | .of_match_table = mmcc_apq8084_match_table, |
3400 | }, | |
3401 | }; | |
3402 | module_platform_driver(mmcc_apq8084_driver); | |
3403 | ||
3404 | MODULE_DESCRIPTION("QCOM MMCC APQ8084 Driver"); | |
3405 | MODULE_LICENSE("GPL v2"); | |
3406 | MODULE_ALIAS("platform:mmcc-apq8084"); |